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source: vbox/trunk/include/VBox/x86.h@ 8155

Last change on this file since 8155 was 8155, checked in by vboxsync, 16 years ago
The Big Sun Rebranding Header Change
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 79.2 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chick. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CR0
505	* @{ */
506	/** Bit 0 - PE - Protection Enabled */
507	#define X86_CR0_PE RT_BIT(0)
508	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
509	/** Bit 1 - MP - Monitor Coprocessor */
510	#define X86_CR0_MP RT_BIT(1)
511	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
512	/** Bit 2 - EM - Emulation. */
513	#define X86_CR0_EM RT_BIT(2)
514	#define X86_CR0_EMULATE_FPU RT_BIT(2)
515	/** Bit 3 - TS - Task Switch. */
516	#define X86_CR0_TS RT_BIT(3)
517	#define X86_CR0_TASK_SWITCH RT_BIT(3)
518	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
519	#define X86_CR0_ET RT_BIT(4)
520	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
521	/** Bit 5 - NE - Numeric error. */
522	#define X86_CR0_NE RT_BIT(5)
523	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
524	/** Bit 16 - WP - Write Protect. */
525	#define X86_CR0_WP RT_BIT(16)
526	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
527	/** Bit 18 - AM - Alignment Mask. */
528	#define X86_CR0_AM RT_BIT(18)
529	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
530	/** Bit 29 - NW - Not Write-though. */
531	#define X86_CR0_NW RT_BIT(29)
532	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
533	/** Bit 30 - WP - Cache Disable. */
534	#define X86_CR0_CD RT_BIT(30)
535	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
536	/** Bit 31 - PG - Paging. */
537	#define X86_CR0_PG RT_BIT(31)
538	#define X86_CR0_PAGING RT_BIT(31)
539	/** @} */
540
541
542	/** @name CR3
543	* @{ */
544	/** Bit 3 - PWT - Page-level Writes Transparent. */
545	#define X86_CR3_PWT RT_BIT(3)
546	/** Bit 4 - PCD - Page-level Cache Disable. */
547	#define X86_CR3_PCD RT_BIT(4)
548	/** Bits 12-31 - - Page directory page number. */
549	#define X86_CR3_PAGE_MASK (0xfffff000)
550	/** Bits 5-31 - - PAE Page directory page number. */
551	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
552	/** @} */
553
554
555	/** @name CR4
556	* @{ */
557	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
558	#define X86_CR4_VME RT_BIT(0)
559	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
560	#define X86_CR4_PVI RT_BIT(1)
561	/** Bit 2 - TSD - Time Stamp Disable. */
562	#define X86_CR4_TSD RT_BIT(2)
563	/** Bit 3 - DE - Debugging Extensions. */
564	#define X86_CR4_DE RT_BIT(3)
565	/** Bit 4 - PSE - Page Size Extension. */
566	#define X86_CR4_PSE RT_BIT(4)
567	/** Bit 5 - PAE - Physical Address Extension. */
568	#define X86_CR4_PAE RT_BIT(5)
569	/** Bit 6 - MCE - Machine-Check Enable. */
570	#define X86_CR4_MCE RT_BIT(6)
571	/** Bit 7 - PGE - Page Global Enable. */
572	#define X86_CR4_PGE RT_BIT(7)
573	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
574	#define X86_CR4_PCE RT_BIT(8)
575	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
576	#define X86_CR4_OSFSXR RT_BIT(9)
577	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
578	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
579	/** Bit 13 - VMXE - VMX mode is enabled. */
580	#define X86_CR4_VMXE RT_BIT(13)
581	/** @} */
582
583
584	/** @name DR6
585	* @{ */
586	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
587	#define X86_DR6_B0 RT_BIT(0)
588	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
589	#define X86_DR6_B1 RT_BIT(1)
590	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
591	#define X86_DR6_B2 RT_BIT(2)
592	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
593	#define X86_DR6_B3 RT_BIT(3)
594	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
595	#define X86_DR6_BD RT_BIT(13)
596	/** Bit 14 - BS - Single step */
597	#define X86_DR6_BS RT_BIT(14)
598	/** Bit 15 - BT - Task switch. (TSS T bit.) */
599	#define X86_DR6_BT RT_BIT(15)
600	/** @} */
601
602
603	/** @name DR7
604	* @{ */
605	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
606	#define X86_DR7_L0 RT_BIT(0)
607	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
608	#define X86_DR7_G0 RT_BIT(1)
609	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
610	#define X86_DR7_L1 RT_BIT(2)
611	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
612	#define X86_DR7_G1 RT_BIT(3)
613	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
614	#define X86_DR7_L2 RT_BIT(4)
615	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
616	#define X86_DR7_G2 RT_BIT(5)
617	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
618	#define X86_DR7_L3 RT_BIT(6)
619	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
620	#define X86_DR7_G3 RT_BIT(7)
621	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
622	#define X86_DR7_LE RT_BIT(8)
623	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
624	#define X86_DR7_GE RT_BIT(9)
625
626	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
627	* any DR register is accessed. */
628	#define X86_DR7_GD RT_BIT(13)
629	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
630	#define X86_DR7_RW0_MASK (3 << 16)
631	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
632	#define X86_DR7_LEN0_MASK (3 << 18)
633	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
634	#define X86_DR7_RW1_MASK (3 << 20)
635	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
636	#define X86_DR7_LEN1_MASK (3 << 22)
637	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
638	#define X86_DR7_RW2_MASK (3 << 24)
639	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
640	#define X86_DR7_LEN2_MASK (3 << 26)
641	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
642	#define X86_DR7_RW3_MASK (3 << 28)
643	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
644	#define X86_DR7_LEN3_MASK (3 << 30)
645
646	/** Bits which must be 1s. */
647	#define X86_DR7_MB1_MASK (RT_BIT(10))
648
649	/** Calcs the L bit of Nth breakpoint.
650	* @param iBp The breakpoint number [0..3].
651	*/
652	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
653
654	/** Calcs the G bit of Nth breakpoint.
655	* @param iBp The breakpoint number [0..3].
656	*/
657	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
658
659	/** @name Read/Write values.
660	* @{ */
661	/** Break on instruction fetch only. */
662	#define X86_DR7_RW_EO 0
663	/** Break on write only. */
664	#define X86_DR7_RW_WO 1
665	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
666	#define X86_DR7_RW_IO 2
667	/** Break on read or write (but not instruction fetches). */
668	#define X86_DR7_RW_RW 3
669	/** @} */
670
671	/** Shifts a X86_DR7_RW_* value to its right place.
672	* @param iBp The breakpoint number [0..3].
673	* @param fRw One of the X86_DR7_RW_* value.
674	*/
675	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
676
677	/** @name Length values.
678	* @{ */
679	#define X86_DR7_LEN_BYTE 0
680	#define X86_DR7_LEN_WORD 1
681	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
682	#define X86_DR7_LEN_DWORD 3
683	/** @} */
684
685	/** Shifts a X86_DR7_LEN_* value to its right place.
686	* @param iBp The breakpoint number [0..3].
687	* @param cb One of the X86_DR7_LEN_* values.
688	*/
689	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
690
691	/** Mask used to check if any breakpoints are enabled. */
692	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
693
694	/** @} */
695
696
697	/** @name Machine Specific Registers
698	* @{
699	*/
700	/** CPU Feature control. */
701	#define MSR_IA32_FEATURE_CONTROL 0x3A
702	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
703	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
704
705
706	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
707	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
708	* R0 SS == CS + 8
709	* R3 CS == CS + 16
710	* R3 SS == CS + 24
711	*/
712	#define MSR_IA32_SYSENTER_CS 0x174
713	/** SYSENTER_ESP - the R0 ESP. */
714	#define MSR_IA32_SYSENTER_ESP 0x175
715	/** SYSENTER_EIP - the R0 EIP. */
716	#define MSR_IA32_SYSENTER_EIP 0x176
717	#endif
718
719	/* Page Attribute Table. */
720	#define IA32_CR_PAT 0x277
721
722	/** Basic VMX information. */
723	#define MSR_IA32_VMX_BASIC_INFO 0x480
724	/** Allowed settings for pin-based VM execution controls */
725	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
726	/** Allowed settings for proc-based VM execution controls */
727	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
728	/** Allowed settings for the VMX exit controls. */
729	#define MSR_IA32_VMX_EXIT_CTLS 0x483
730	/** Allowed settings for the VMX entry controls. */
731	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
732	/** Misc VMX info. */
733	#define MSR_IA32_VMX_MISC 0x485
734	/** Fixed cleared bits in CR0. */
735	#define MSR_IA32_VMX_CR0_FIXED0 0x486
736	/** Fixed set bits in CR0. */
737	#define MSR_IA32_VMX_CR0_FIXED1 0x487
738	/** Fixed cleared bits in CR4. */
739	#define MSR_IA32_VMX_CR4_FIXED0 0x488
740	/** Fixed set bits in CR4. */
741	#define MSR_IA32_VMX_CR4_FIXED1 0x489
742	/** Information for enumerating fields in the VMCS. */
743	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
744
745
746	/** K6 EFER - Extended Feature Enable Register. */
747	#define MSR_K6_EFER 0xc0000080
748	/** @todo document EFER */
749	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
750	#define MSR_K6_EFER_SCE RT_BIT(0)
751	/** Bit 8 - LME - Long mode enabled. (R/W) */
752	#define MSR_K6_EFER_LME RT_BIT(8)
753	/** Bit 10 - LMA - Long mode active. (R) */
754	#define MSR_K6_EFER_LMA RT_BIT(10)
755	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
756	#define MSR_K6_EFER_NXE RT_BIT(11)
757	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
758	#define MSR_K6_EFER_SVME RT_BIT(12)
759	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
760	#define MSR_K6_EFER_LMSLE RT_BIT(13)
761	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
762	#define MSR_K6_EFER_FFXSR RT_BIT(14)
763	/** K6 STAR - SYSCALL/RET targets. */
764	#define MSR_K6_STAR 0xc0000081
765	/** Shift value for getting the SYSRET CS and SS value. */
766	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
767	/** Shift value for getting the SYSCALL CS and SS value. */
768	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
769	/** Selector mask for use after shifting. */
770	#define MSR_K6_STAR_SEL_MASK 0xffff
771	/** The mask which give the SYSCALL EIP. */
772	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
773	/** K6 WHCR - Write Handling Control Register. */
774	#define MSR_K6_WHCR 0xc0000082
775	/** K6 UWCCR - UC/WC Cacheability Control Register. */
776	#define MSR_K6_UWCCR 0xc0000085
777	/** K6 PSOR - Processor State Observability Register. */
778	#define MSR_K6_PSOR 0xc0000087
779	/** K6 PFIR - Page Flush/Invalidate Register. */
780	#define MSR_K6_PFIR 0xc0000088
781
782	#define MSR_K7_EVNTSEL0 0xc0010000
783	#define MSR_K7_EVNTSEL1 0xc0010001
784	#define MSR_K7_EVNTSEL2 0xc0010002
785	#define MSR_K7_EVNTSEL3 0xc0010003
786	#define MSR_K7_PERFCTR0 0xc0010004
787	#define MSR_K7_PERFCTR1 0xc0010005
788	#define MSR_K7_PERFCTR2 0xc0010006
789	#define MSR_K7_PERFCTR3 0xc0010007
790
791	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
792	#define MSR_K8_LSTAR 0xc0000082
793	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
794	#define MSR_K8_CSTAR 0xc0000083
795	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
796	#define MSR_K8_SF_MASK 0xc0000084
797	/** K8 FS.base - The 64-bit base FS register. */
798	#define MSR_K8_FS_BASE 0xc0000100
799	/** K8 GS.base - The 64-bit base GS register. */
800	#define MSR_K8_GS_BASE 0xc0000101
801	/** K8 KernelGSbase - Used with SWAPGS. */
802	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
803	#define MSR_K8_TSC_AUX 0xc0000103
804	#define MSR_K8_SYSCFG 0xc0010010
805	#define MSR_K8_HWCR 0xc0010015
806	#define MSR_K8_IORRBASE0 0xc0010016
807	#define MSR_K8_IORRMASK0 0xc0010017
808	#define MSR_K8_IORRBASE1 0xc0010018
809	#define MSR_K8_IORRMASK1 0xc0010019
810	#define MSR_K8_TOP_MEM1 0xc001001a
811	#define MSR_K8_TOP_MEM2 0xc001001d
812	#define MSR_K8_VM_CR 0xc0010114
813	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
814
815	#define MSR_K8_IGNNE 0xc0010115
816	#define MSR_K8_SMM_CTL 0xc0010116
817	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
818	* host state during world switch.
819	*/
820	#define MSR_K8_VM_HSAVE_PA 0xc0010117
821
822	/** @} */
823
824
825	/** @name Page Table / Directory / Directory Pointers / L4.
826	* @{
827	*/
828
829	/** Page table/directory entry as an unsigned integer. */
830	typedef uint32_t X86PGUINT;
831	/** Pointer to a page table/directory table entry as an unsigned integer. */
832	typedef X86PGUINT *PX86PGUINT;
833
834	/** Number of entries in a 32-bit PT/PD. */
835	#define X86_PG_ENTRIES 1024
836
837
838	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
839	typedef uint64_t X86PGPAEUINT;
840	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
841	typedef X86PGPAEUINT *PX86PGPAEUINT;
842
843	/** Number of entries in a PAE PT/PD. */
844	#define X86_PG_PAE_ENTRIES 512
845	/** Number of entries in a PAE PDPT. */
846	#define X86_PG_PAE_PDPE_ENTRIES 4
847
848	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
849	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
850	/** Number of entries in an AMD64 PDPT.
851	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
852	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
853
854	/** The size of a 4KB page. */
855	#define X86_PAGE_4K_SIZE _4K
856	/** The page shift of a 4KB page. */
857	#define X86_PAGE_4K_SHIFT 12
858	/** The 4KB page offset mask. */
859	#define X86_PAGE_4K_OFFSET_MASK 0xfff
860	/** The 4KB page base mask for virtual addresses. */
861	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
862	/** The 4KB page base mask for virtual addresses - 32bit version. */
863	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
864
865	/** The size of a 2MB page. */
866	#define X86_PAGE_2M_SIZE _2M
867	/** The page shift of a 2MB page. */
868	#define X86_PAGE_2M_SHIFT 21
869	/** The 2MB page offset mask. */
870	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
871	/** The 2MB page base mask for virtual addresses. */
872	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
873	/** The 2MB page base mask for virtual addresses - 32bit version. */
874	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
875
876	/** The size of a 4MB page. */
877	#define X86_PAGE_4M_SIZE _4M
878	/** The page shift of a 4MB page. */
879	#define X86_PAGE_4M_SHIFT 22
880	/** The 4MB page offset mask. */
881	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
882	/** The 4MB page base mask for virtual addresses. */
883	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
884	/** The 4MB page base mask for virtual addresses - 32bit version. */
885	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
886
887
888
889	/** @name Page Table Entry
890	* @{
891	*/
892	/** Bit 0 - P - Present bit. */
893	#define X86_PTE_P RT_BIT(0)
894	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
895	#define X86_PTE_RW RT_BIT(1)
896	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
897	#define X86_PTE_US RT_BIT(2)
898	/** Bit 3 - PWT - Page level write thru bit. */
899	#define X86_PTE_PWT RT_BIT(3)
900	/** Bit 4 - PCD - Page level cache disable bit. */
901	#define X86_PTE_PCD RT_BIT(4)
902	/** Bit 5 - A - Access bit. */
903	#define X86_PTE_A RT_BIT(5)
904	/** Bit 6 - D - Dirty bit. */
905	#define X86_PTE_D RT_BIT(6)
906	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
907	#define X86_PTE_PAT RT_BIT(7)
908	/** Bit 8 - G - Global flag. */
909	#define X86_PTE_G RT_BIT(8)
910	/** Bits 9-11 - - Available for use to system software. */
911	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
912	/** Bits 12-31 - - Physical Page number of the next level. */
913	#define X86_PTE_PG_MASK ( 0xfffff000 )
914
915	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
916	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
917	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
918	#else
919	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
920	#endif
921	/** Bits 63 - NX - PAE - No execution flag. */
922	#define X86_PTE_PAE_NX RT_BIT_64(63)
923
924	/**
925	* Page table entry.
926	*/
927	typedef struct X86PTEBITS
928	{
929	/** Flags whether(=1) or not the page is present. */
930	unsigned u1Present : 1;
931	/** Read(=0) / Write(=1) flag. */
932	unsigned u1Write : 1;
933	/** User(=1) / Supervisor (=0) flag. */
934	unsigned u1User : 1;
935	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
936	unsigned u1WriteThru : 1;
937	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
938	unsigned u1CacheDisable : 1;
939	/** Accessed flag.
940	* Indicates that the page have been read or written to. */
941	unsigned u1Accessed : 1;
942	/** Dirty flag.
943	* Indicates that the page have been written to. */
944	unsigned u1Dirty : 1;
945	/** Reserved / If PAT enabled, bit 2 of the index. */
946	unsigned u1PAT : 1;
947	/** Global flag. (Ignored in all but final level.) */
948	unsigned u1Global : 1;
949	/** Available for use to system software. */
950	unsigned u3Available : 3;
951	/** Physical Page number of the next level. */
952	unsigned u20PageNo : 20;
953	} X86PTEBITS;
954	/** Pointer to a page table entry. */
955	typedef X86PTEBITS *PX86PTEBITS;
956	/** Pointer to a const page table entry. */
957	typedef const X86PTEBITS *PCX86PTEBITS;
958
959	/**
960	* Page table entry.
961	*/
962	typedef union X86PTE
963	{
964	/** Bit field view. */
965	X86PTEBITS n;
966	/** Unsigned integer view */
967	X86PGUINT u;
968	/** 32-bit view. */
969	uint32_t au32[1];
970	/** 16-bit view. */
971	uint16_t au16[2];
972	/** 8-bit view. */
973	uint8_t au8[4];
974	} X86PTE;
975	/** Pointer to a page table entry. */
976	typedef X86PTE *PX86PTE;
977	/** Pointer to a const page table entry. */
978	typedef const X86PTE *PCX86PTE;
979
980
981	/**
982	* PAE page table entry.
983	*/
984	typedef struct X86PTEPAEBITS
985	{
986	/** Flags whether(=1) or not the page is present. */
987	uint32_t u1Present : 1;
988	/** Read(=0) / Write(=1) flag. */
989	uint32_t u1Write : 1;
990	/** User(=1) / Supervisor(=0) flag. */
991	uint32_t u1User : 1;
992	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
993	uint32_t u1WriteThru : 1;
994	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
995	uint32_t u1CacheDisable : 1;
996	/** Accessed flag.
997	* Indicates that the page have been read or written to. */
998	uint32_t u1Accessed : 1;
999	/** Dirty flag.
1000	* Indicates that the page have been written to. */
1001	uint32_t u1Dirty : 1;
1002	/** Reserved / If PAT enabled, bit 2 of the index. */
1003	uint32_t u1PAT : 1;
1004	/** Global flag. (Ignored in all but final level.) */
1005	uint32_t u1Global : 1;
1006	/** Available for use to system software. */
1007	uint32_t u3Available : 3;
1008	/** Physical Page number of the next level - Low Part. Don't use this. */
1009	uint32_t u20PageNoLow : 20;
1010	/** Physical Page number of the next level - High Part. Don't use this. */
1011	uint32_t u20PageNoHigh : 20;
1012	/** MBZ bits */
1013	uint32_t u11Reserved : 11;
1014	/** No Execute flag. */
1015	uint32_t u1NoExecute : 1;
1016	} X86PTEPAEBITS;
1017	/** Pointer to a page table entry. */
1018	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1019	/** Pointer to a page table entry. */
1020	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1021
1022	/**
1023	* PAE Page table entry.
1024	*/
1025	typedef union X86PTEPAE
1026	{
1027	/** Bit field view. */
1028	X86PTEPAEBITS n;
1029	/** Unsigned integer view */
1030	X86PGPAEUINT u;
1031	/** 32-bit view. */
1032	uint32_t au32[2];
1033	/** 16-bit view. */
1034	uint16_t au16[4];
1035	/** 8-bit view. */
1036	uint8_t au8[8];
1037	} X86PTEPAE;
1038	/** Pointer to a PAE page table entry. */
1039	typedef X86PTEPAE *PX86PTEPAE;
1040	/** Pointer to a const PAE page table entry. */
1041	typedef const X86PTEPAE *PCX86PTEPAE;
1042	/** @} */
1043
1044	/**
1045	* Page table.
1046	*/
1047	typedef struct X86PT
1048	{
1049	/** PTE Array. */
1050	X86PTE a[X86_PG_ENTRIES];
1051	} X86PT;
1052	/** Pointer to a page table. */
1053	typedef X86PT *PX86PT;
1054	/** Pointer to a const page table. */
1055	typedef const X86PT *PCX86PT;
1056
1057	/** The page shift to get the PT index. */
1058	#define X86_PT_SHIFT 12
1059	/** The PT index mask (apply to a shifted page address). */
1060	#define X86_PT_MASK 0x3ff
1061
1062
1063	/**
1064	* Page directory.
1065	*/
1066	typedef struct X86PTPAE
1067	{
1068	/** PTE Array. */
1069	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1070	} X86PTPAE;
1071	/** Pointer to a page table. */
1072	typedef X86PTPAE *PX86PTPAE;
1073	/** Pointer to a const page table. */
1074	typedef const X86PTPAE *PCX86PTPAE;
1075
1076	/** The page shift to get the PA PTE index. */
1077	#define X86_PT_PAE_SHIFT 12
1078	/** The PAE PT index mask (apply to a shifted page address). */
1079	#define X86_PT_PAE_MASK 0x1ff
1080
1081
1082	/** @name 4KB Page Directory Entry
1083	* @{
1084	*/
1085	/** Bit 0 - P - Present bit. */
1086	#define X86_PDE_P RT_BIT(0)
1087	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1088	#define X86_PDE_RW RT_BIT(1)
1089	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1090	#define X86_PDE_US RT_BIT(2)
1091	/** Bit 3 - PWT - Page level write thru bit. */
1092	#define X86_PDE_PWT RT_BIT(3)
1093	/** Bit 4 - PCD - Page level cache disable bit. */
1094	#define X86_PDE_PCD RT_BIT(4)
1095	/** Bit 5 - A - Access bit. */
1096	#define X86_PDE_A RT_BIT(5)
1097	/** Bit 7 - PS - Page size attribute.
1098	* Clear mean 4KB pages, set means large pages (2/4MB). */
1099	#define X86_PDE_PS RT_BIT(7)
1100	/** Bits 9-11 - - Available for use to system software. */
1101	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1102	/** Bits 12-31 - - Physical Page number of the next level. */
1103	#define X86_PDE_PG_MASK ( 0xfffff000 )
1104
1105	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1106	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1107	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1108	#else
1109	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1110	#endif
1111	/** Bits 63 - NX - PAE - No execution flag. */
1112	#define X86_PDE_PAE_NX RT_BIT_64(63)
1113
1114	/**
1115	* Page directory entry.
1116	*/
1117	typedef struct X86PDEBITS
1118	{
1119	/** Flags whether(=1) or not the page is present. */
1120	unsigned u1Present : 1;
1121	/** Read(=0) / Write(=1) flag. */
1122	unsigned u1Write : 1;
1123	/** User(=1) / Supervisor (=0) flag. */
1124	unsigned u1User : 1;
1125	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1126	unsigned u1WriteThru : 1;
1127	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1128	unsigned u1CacheDisable : 1;
1129	/** Accessed flag.
1130	* Indicates that the page have been read or written to. */
1131	unsigned u1Accessed : 1;
1132	/** Reserved / Ignored (dirty bit). */
1133	unsigned u1Reserved0 : 1;
1134	/** Size bit if PSE is enabled - in any event it's 0. */
1135	unsigned u1Size : 1;
1136	/** Reserved / Ignored (global bit). */
1137	unsigned u1Reserved1 : 1;
1138	/** Available for use to system software. */
1139	unsigned u3Available : 3;
1140	/** Physical Page number of the next level. */
1141	unsigned u20PageNo : 20;
1142	} X86PDEBITS;
1143	/** Pointer to a page directory entry. */
1144	typedef X86PDEBITS *PX86PDEBITS;
1145	/** Pointer to a const page directory entry. */
1146	typedef const X86PDEBITS *PCX86PDEBITS;
1147
1148
1149	/**
1150	* PAE page directory entry.
1151	*/
1152	typedef struct X86PDEPAEBITS
1153	{
1154	/** Flags whether(=1) or not the page is present. */
1155	uint32_t u1Present : 1;
1156	/** Read(=0) / Write(=1) flag. */
1157	uint32_t u1Write : 1;
1158	/** User(=1) / Supervisor (=0) flag. */
1159	uint32_t u1User : 1;
1160	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1161	uint32_t u1WriteThru : 1;
1162	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1163	uint32_t u1CacheDisable : 1;
1164	/** Accessed flag.
1165	* Indicates that the page have been read or written to. */
1166	uint32_t u1Accessed : 1;
1167	/** Reserved / Ignored (dirty bit). */
1168	uint32_t u1Reserved0 : 1;
1169	/** Size bit if PSE is enabled - in any event it's 0. */
1170	uint32_t u1Size : 1;
1171	/** Reserved / Ignored (global bit). / */
1172	uint32_t u1Reserved1 : 1;
1173	/** Available for use to system software. */
1174	uint32_t u3Available : 3;
1175	/** Physical Page number of the next level - Low Part. Don't use! */
1176	uint32_t u20PageNoLow : 20;
1177	/** Physical Page number of the next level - High Part. Don't use! */
1178	uint32_t u20PageNoHigh : 20;
1179	/** MBZ bits */
1180	uint32_t u11Reserved : 11;
1181	/** No Execute flag. */
1182	uint32_t u1NoExecute : 1;
1183	} X86PDEPAEBITS;
1184	/** Pointer to a page directory entry. */
1185	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1186	/** Pointer to a const page directory entry. */
1187	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1188
1189	/** @} */
1190
1191
1192	/** @name 2/4MB Page Directory Entry
1193	* @{
1194	*/
1195	/** Bit 0 - P - Present bit. */
1196	#define X86_PDE4M_P RT_BIT(0)
1197	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1198	#define X86_PDE4M_RW RT_BIT(1)
1199	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1200	#define X86_PDE4M_US RT_BIT(2)
1201	/** Bit 3 - PWT - Page level write thru bit. */
1202	#define X86_PDE4M_PWT RT_BIT(3)
1203	/** Bit 4 - PCD - Page level cache disable bit. */
1204	#define X86_PDE4M_PCD RT_BIT(4)
1205	/** Bit 5 - A - Access bit. */
1206	#define X86_PDE4M_A RT_BIT(5)
1207	/** Bit 6 - D - Dirty bit. */
1208	#define X86_PDE4M_D RT_BIT(6)
1209	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1210	#define X86_PDE4M_PS RT_BIT(7)
1211	/** Bit 8 - G - Global flag. */
1212	#define X86_PDE4M_G RT_BIT(8)
1213	/** Bits 9-11 - AVL - Available for use to system software. */
1214	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1215	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1216	#define X86_PDE4M_PAT RT_BIT(12)
1217	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1218	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1219	/** Bits 22-31 - - Physical Page number. */
1220	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1221	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1222	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1223	/** The number of bits to the high part of the page number. */
1224	#define X86_PDE4M_PG_HIGH_SHIFT 19
1225
1226	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1227	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1228	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1229	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1230	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1231
1232	/**
1233	* 4MB page directory entry.
1234	*/
1235	typedef struct X86PDE4MBITS
1236	{
1237	/** Flags whether(=1) or not the page is present. */
1238	unsigned u1Present : 1;
1239	/** Read(=0) / Write(=1) flag. */
1240	unsigned u1Write : 1;
1241	/** User(=1) / Supervisor (=0) flag. */
1242	unsigned u1User : 1;
1243	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1244	unsigned u1WriteThru : 1;
1245	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1246	unsigned u1CacheDisable : 1;
1247	/** Accessed flag.
1248	* Indicates that the page have been read or written to. */
1249	unsigned u1Accessed : 1;
1250	/** Dirty flag.
1251	* Indicates that the page have been written to. */
1252	unsigned u1Dirty : 1;
1253	/** Page size flag - always 1 for 4MB entries. */
1254	unsigned u1Size : 1;
1255	/** Global flag. */
1256	unsigned u1Global : 1;
1257	/** Available for use to system software. */
1258	unsigned u3Available : 3;
1259	/** Reserved / If PAT enabled, bit 2 of the index. */
1260	unsigned u1PAT : 1;
1261	/** Bits 32-39 of the page number on AMD64.
1262	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1263	unsigned u8PageNoHigh : 8;
1264	/** Reserved. */
1265	unsigned u1Reserved : 1;
1266	/** Physical Page number of the page. */
1267	unsigned u10PageNo : 10;
1268	} X86PDE4MBITS;
1269	/** Pointer to a page table entry. */
1270	typedef X86PDE4MBITS *PX86PDE4MBITS;
1271	/** Pointer to a const page table entry. */
1272	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1273
1274
1275	/**
1276	* 2MB PAE page directory entry.
1277	*/
1278	typedef struct X86PDE2MPAEBITS
1279	{
1280	/** Flags whether(=1) or not the page is present. */
1281	uint32_t u1Present : 1;
1282	/** Read(=0) / Write(=1) flag. */
1283	uint32_t u1Write : 1;
1284	/** User(=1) / Supervisor(=0) flag. */
1285	uint32_t u1User : 1;
1286	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1287	uint32_t u1WriteThru : 1;
1288	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1289	uint32_t u1CacheDisable : 1;
1290	/** Accessed flag.
1291	* Indicates that the page have been read or written to. */
1292	uint32_t u1Accessed : 1;
1293	/** Dirty flag.
1294	* Indicates that the page have been written to. */
1295	uint32_t u1Dirty : 1;
1296	/** Page size flag - always 1 for 2MB entries. */
1297	uint32_t u1Size : 1;
1298	/** Global flag. */
1299	uint32_t u1Global : 1;
1300	/** Available for use to system software. */
1301	uint32_t u3Available : 3;
1302	/** Reserved / If PAT enabled, bit 2 of the index. */
1303	uint32_t u1PAT : 1;
1304	/** Reserved. */
1305	uint32_t u9Reserved : 9;
1306	/** Physical Page number of the next level - Low part. Don't use! */
1307	uint32_t u10PageNoLow : 10;
1308	/** Physical Page number of the next level - High part. Don't use! */
1309	uint32_t u20PageNoHigh : 20;
1310	/** MBZ bits */
1311	uint32_t u11Reserved : 11;
1312	/** No Execute flag. */
1313	uint32_t u1NoExecute : 1;
1314	} X86PDE2MPAEBITS;
1315	/** Pointer to a 4MB PAE page table entry. */
1316	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1317	/** Pointer to a 4MB PAE page table entry. */
1318	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1319
1320	/** @} */
1321
1322	/**
1323	* Page directory entry.
1324	*/
1325	typedef union X86PDE
1326	{
1327	/** Normal view. */
1328	X86PDEBITS n;
1329	/** 4MB view (big). */
1330	X86PDE4MBITS b;
1331	/** Unsigned integer view. */
1332	X86PGUINT u;
1333	/** 8 bit unsigned integer view. */
1334	uint8_t au8[4];
1335	/** 16 bit unsigned integer view. */
1336	uint16_t au16[2];
1337	/** 32 bit unsigned integer view. */
1338	uint32_t au32[1];
1339	} X86PDE;
1340	/** Pointer to a page directory entry. */
1341	typedef X86PDE *PX86PDE;
1342	/** Pointer to a const page directory entry. */
1343	typedef const X86PDE *PCX86PDE;
1344
1345	/**
1346	* PAE page directory entry.
1347	*/
1348	typedef union X86PDEPAE
1349	{
1350	/** Normal view. */
1351	X86PDEPAEBITS n;
1352	/** 2MB page view (big). */
1353	X86PDE2MPAEBITS b;
1354	/** Unsigned integer view. */
1355	X86PGPAEUINT u;
1356	/** 8 bit unsigned integer view. */
1357	uint8_t au8[8];
1358	/** 16 bit unsigned integer view. */
1359	uint16_t au16[4];
1360	/** 32 bit unsigned integer view. */
1361	uint32_t au32[2];
1362	} X86PDEPAE;
1363	/** Pointer to a page directory entry. */
1364	typedef X86PDEPAE *PX86PDEPAE;
1365	/** Pointer to a const page directory entry. */
1366	typedef const X86PDEPAE *PCX86PDEPAE;
1367
1368	/**
1369	* Page directory.
1370	*/
1371	typedef struct X86PD
1372	{
1373	/** PDE Array. */
1374	X86PDE a[X86_PG_ENTRIES];
1375	} X86PD;
1376	/** Pointer to a page directory. */
1377	typedef X86PD *PX86PD;
1378	/** Pointer to a const page directory. */
1379	typedef const X86PD *PCX86PD;
1380
1381	/** The page shift to get the PD index. */
1382	#define X86_PD_SHIFT 22
1383	/** The PD index mask (apply to a shifted page address). */
1384	#define X86_PD_MASK 0x3ff
1385
1386
1387	/**
1388	* PAE page directory.
1389	*/
1390	typedef struct X86PDPAE
1391	{
1392	/** PDE Array. */
1393	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1394	} X86PDPAE;
1395	/** Pointer to a PAE page directory. */
1396	typedef X86PDPAE *PX86PDPAE;
1397	/** Pointer to a const PAE page directory. */
1398	typedef const X86PDPAE *PCX86PDPAE;
1399
1400	/** The page shift to get the PAE PD index. */
1401	#define X86_PD_PAE_SHIFT 21
1402	/** The PAE PD index mask (apply to a shifted page address). */
1403	#define X86_PD_PAE_MASK 0x1ff
1404
1405
1406	/** @name Page Directory Pointer Table Entry (PAE)
1407	* @{
1408	*/
1409	/** Bit 0 - P - Present bit. */
1410	#define X86_PDPE_P RT_BIT(0)
1411	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1412	#define X86_PDPE_RW RT_BIT(1)
1413	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1414	#define X86_PDPE_US RT_BIT(2)
1415	/** Bit 3 - PWT - Page level write thru bit. */
1416	#define X86_PDPE_PWT RT_BIT(3)
1417	/** Bit 4 - PCD - Page level cache disable bit. */
1418	#define X86_PDPE_PCD RT_BIT(4)
1419	/** Bit 5 - A - Access bit. Long Mode only. */
1420	#define X86_PDPE_A RT_BIT(5)
1421	/** Bits 9-11 - - Available for use to system software. */
1422	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1423	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1424	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1425	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1426	#else
1427	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1428	#endif
1429	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1430	#define X86_PDPE_NX RT_BIT_64(63)
1431
1432	/**
1433	* Page directory pointer table entry.
1434	*/
1435	typedef struct X86PDPEBITS
1436	{
1437	/** Flags whether(=1) or not the page is present. */
1438	uint32_t u1Present : 1;
1439	/** Read(=0) / Write(=1) flag. */
1440	uint32_t u1Write : 1;
1441	/** User(=1) / Supervisor (=0) flag. */
1442	uint32_t u1User : 1;
1443	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1444	uint32_t u1WriteThru : 1;
1445	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1446	uint32_t u1CacheDisable : 1;
1447	/** Accessed flag.
1448	* Indicates that the page have been read or written to. */
1449	uint32_t u1Accessed : 1;
1450	/** Chunk of reserved bits. */
1451	uint32_t u3Reserved : 3;
1452	/** Available for use to system software. */
1453	uint32_t u3Available : 3;
1454	/** Physical Page number of the next level - Low Part. Don't use! */
1455	uint32_t u20PageNoLow : 20;
1456	/** Physical Page number of the next level - High Part. Don't use! */
1457	uint32_t u20PageNoHigh : 20;
1458	/** MBZ bits */
1459	uint32_t u11Reserved : 11;
1460	/** No Execute flag. */
1461	uint32_t u1NoExecute : 1;
1462	} X86PDPEBITS;
1463	/** Pointer to a page directory pointer table entry. */
1464	typedef X86PDPEBITS *PX86PTPEBITS;
1465	/** Pointer to a const page directory pointer table entry. */
1466	typedef const X86PDPEBITS *PCX86PTPEBITS;
1467
1468	/**
1469	* Page directory pointer table entry.
1470	*/
1471	typedef union X86PDPE
1472	{
1473	/** Normal view. */
1474	X86PDPEBITS n;
1475	/** Unsigned integer view. */
1476	X86PGPAEUINT u;
1477	/** 8 bit unsigned integer view. */
1478	uint8_t au8[8];
1479	/** 16 bit unsigned integer view. */
1480	uint16_t au16[4];
1481	/** 32 bit unsigned integer view. */
1482	uint32_t au32[2];
1483	} X86PDPE;
1484	/** Pointer to a page directory pointer table entry. */
1485	typedef X86PDPE *PX86PDPE;
1486	/** Pointer to a const page directory pointer table entry. */
1487	typedef const X86PDPE *PCX86PDPE;
1488
1489
1490	/**
1491	* Page directory pointer table.
1492	*/
1493	typedef struct X86PDPT
1494	{
1495	/** PDE Array. */
1496	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1497	} X86PDPT;
1498	/** Pointer to a page directory pointer table. */
1499	typedef X86PDPT *PX86PDPT;
1500	/** Pointer to a const page directory pointer table. */
1501	typedef const X86PDPT *PCX86PDPT;
1502
1503	/** The page shift to get the PDPT index. */
1504	#define X86_PDPT_SHIFT 30
1505	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1506	#define X86_PDPT_MASK_PAE 0x3
1507	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1508	#define X86_PDPT_MASK_AMD64 0x1ff
1509
1510	/** @} */
1511
1512
1513	/** @name Page Map Level-4 Entry (Long Mode PAE)
1514	* @{
1515	*/
1516	/** Bit 0 - P - Present bit. */
1517	#define X86_PML4E_P RT_BIT(0)
1518	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1519	#define X86_PML4E_RW RT_BIT(1)
1520	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1521	#define X86_PML4E_US RT_BIT(2)
1522	/** Bit 3 - PWT - Page level write thru bit. */
1523	#define X86_PML4E_PWT RT_BIT(3)
1524	/** Bit 4 - PCD - Page level cache disable bit. */
1525	#define X86_PML4E_PCD RT_BIT(4)
1526	/** Bit 5 - A - Access bit. */
1527	#define X86_PML4E_A RT_BIT(5)
1528	/** Bits 9-11 - - Available for use to system software. */
1529	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1530	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1531	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1532	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1533	#else
1534	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1535	#endif
1536	/** Bits 63 - NX - PAE - No execution flag. */
1537	#define X86_PML4E_NX RT_BIT_64(63)
1538
1539	/**
1540	* Page Map Level-4 Entry
1541	*/
1542	typedef struct X86PML4EBITS
1543	{
1544	/** Flags whether(=1) or not the page is present. */
1545	uint32_t u1Present : 1;
1546	/** Read(=0) / Write(=1) flag. */
1547	uint32_t u1Write : 1;
1548	/** User(=1) / Supervisor (=0) flag. */
1549	uint32_t u1User : 1;
1550	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1551	uint32_t u1WriteThru : 1;
1552	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1553	uint32_t u1CacheDisable : 1;
1554	/** Accessed flag.
1555	* Indicates that the page have been read or written to. */
1556	uint32_t u1Accessed : 1;
1557	/** Chunk of reserved bits. */
1558	uint32_t u3Reserved : 3;
1559	/** Available for use to system software. */
1560	uint32_t u3Available : 3;
1561	/** Physical Page number of the next level - Low Part. Don't use! */
1562	uint32_t u20PageNoLow : 20;
1563	/** Physical Page number of the next level - High Part. Don't use! */
1564	uint32_t u20PageNoHigh : 20;
1565	/** MBZ bits */
1566	uint32_t u11Reserved : 11;
1567	/** No Execute flag. */
1568	uint32_t u1NoExecute : 1;
1569	} X86PML4EBITS;
1570	/** Pointer to a page map level-4 entry. */
1571	typedef X86PML4EBITS *PX86PML4EBITS;
1572	/** Pointer to a const page map level-4 entry. */
1573	typedef const X86PML4EBITS *PCX86PML4EBITS;
1574
1575	/**
1576	* Page Map Level-4 Entry.
1577	*/
1578	typedef union X86PML4E
1579	{
1580	/** Normal view. */
1581	X86PML4EBITS n;
1582	/** Unsigned integer view. */
1583	X86PGPAEUINT u;
1584	/** 8 bit unsigned integer view. */
1585	uint8_t au8[8];
1586	/** 16 bit unsigned integer view. */
1587	uint16_t au16[4];
1588	/** 32 bit unsigned integer view. */
1589	uint32_t au32[2];
1590	} X86PML4E;
1591	/** Pointer to a page map level-4 entry. */
1592	typedef X86PML4E *PX86PML4E;
1593	/** Pointer to a const page map level-4 entry. */
1594	typedef const X86PML4E *PCX86PML4E;
1595
1596
1597	/**
1598	* Page Map Level-4.
1599	*/
1600	typedef struct X86PML4
1601	{
1602	/** PDE Array. */
1603	X86PML4E a[X86_PG_PAE_ENTRIES];
1604	} X86PML4;
1605	/** Pointer to a page map level-4. */
1606	typedef X86PML4 *PX86PML4;
1607	/** Pointer to a const page map level-4. */
1608	typedef const X86PML4 *PCX86PML4;
1609
1610	/** The page shift to get the PML4 index. */
1611	#define X86_PML4_SHIFT 39
1612	/** The PML4 index mask (apply to a shifted page address). */
1613	#define X86_PML4_MASK 0x1ff
1614
1615	/** @} */
1616
1617	/** @} */
1618
1619
1620	/**
1621	* 80-bit MMX/FPU register type.
1622	*/
1623	typedef struct X86FPUMMX
1624	{
1625	uint8_t reg[10];
1626	} X86FPUMMX;
1627	/** Pointer to a 80-bit MMX/FPU register type. */
1628	typedef X86FPUMMX *PX86FPUMMX;
1629	/** Pointer to a const 80-bit MMX/FPU register type. */
1630	typedef const X86FPUMMX *PCX86FPUMMX;
1631
1632	/**
1633	* FPU state (aka FSAVE/FRSTOR Memory Region).
1634	*/
1635	#pragma pack(1)
1636	typedef struct X86FPUSTATE
1637	{
1638	/** Control word. */
1639	uint16_t FCW;
1640	/** Alignment word */
1641	uint16_t Dummy1;
1642	/** Status word. */
1643	uint16_t FSW;
1644	/** Alignment word */
1645	uint16_t Dummy2;
1646	/** Tag word */
1647	uint16_t FTW;
1648	/** Alignment word */
1649	uint16_t Dummy3;
1650
1651	/** Instruction pointer. */
1652	uint32_t FPUIP;
1653	/** Code selector. */
1654	uint16_t CS;
1655	/** Opcode. */
1656	uint16_t FOP;
1657	/** FOO. */
1658	uint32_t FPUOO;
1659	/** FOS. */
1660	uint32_t FPUOS;
1661	/** FPU view - todo. */
1662	X86FPUMMX regs[8];
1663	} X86FPUSTATE;
1664	#pragma pack()
1665	/** Pointer to a FPU state. */
1666	typedef X86FPUSTATE *PX86FPUSTATE;
1667	/** Pointer to a const FPU state. */
1668	typedef const X86FPUSTATE *PCX86FPUSTATE;
1669
1670	/**
1671	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1672	*/
1673	#pragma pack(1)
1674	typedef struct X86FXSTATE
1675	{
1676	/** Control word. */
1677	uint16_t FCW;
1678	/** Status word. */
1679	uint16_t FSW;
1680	/** Tag word (it's a byte actually). */
1681	uint8_t FTW;
1682	uint8_t huh1;
1683	/** Opcode. */
1684	uint16_t FOP;
1685	/** Instruction pointer. */
1686	uint32_t FPUIP;
1687	/** Code selector. */
1688	uint16_t CS;
1689	uint16_t Rsvrd1;
1690	/* - offset 16 - */
1691	/** Data pointer. */
1692	uint32_t FPUDP;
1693	/** Data segment */
1694	uint16_t DS;
1695	uint16_t Rsrvd2;
1696	uint32_t MXCSR;
1697	uint32_t MXCSR_MASK;
1698	/* - offset 32 - */
1699	union
1700	{
1701	/** MMX view. */
1702	uint64_t mmx;
1703	/** FPU view - todo. */
1704	X86FPUMMX fpu;
1705	/** 8-bit view. */
1706	uint8_t au8[16];
1707	/** 16-bit view. */
1708	uint16_t au16[8];
1709	/** 32-bit view. */
1710	uint32_t au32[4];
1711	/** 64-bit view. */
1712	uint64_t au64[2];
1713	/** 128-bit view. (yeah, very helpful) */
1714	uint128_t au128[1];
1715	} aRegs[8];
1716	/* - offset 160 - */
1717	union
1718	{
1719	/** XMM Register view . /
1720	uint128_t xmm;
1721	/** 8-bit view. */
1722	uint8_t au8[16];
1723	/** 16-bit view. */
1724	uint16_t au16[8];
1725	/** 32-bit view. */
1726	uint32_t au32[4];
1727	/** 64-bit view. */
1728	uint64_t au64[2];
1729	/** 128-bit view. (yeah, very helpful) */
1730	uint128_t au128[1];
1731	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1732	/* - offset 416 - */
1733	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1734	} X86FXSTATE;
1735	#pragma pack()
1736	/** Pointer to a FPU Extended state. */
1737	typedef X86FXSTATE *PX86FXSTATE;
1738	/** Pointer to a const FPU Extended state. */
1739	typedef const X86FXSTATE *PCX86FXSTATE;
1740
1741
1742	/** @name Selector Descriptor
1743	* @{
1744	*/
1745
1746	/**
1747	* Generic descriptor table entry
1748	*/
1749	#pragma pack(1)
1750	typedef struct X86DESCGENERIC
1751	{
1752	/** Limit - Low word. */
1753	unsigned u16LimitLow : 16;
1754	/** Base address - lowe word.
1755	* Don't try set this to 24 because MSC is doing studing things then. */
1756	unsigned u16BaseLow : 16;
1757	/** Base address - first 8 bits of high word. */
1758	unsigned u8BaseHigh1 : 8;
1759	/** Segment Type. */
1760	unsigned u4Type : 4;
1761	/** Descriptor Type. System(=0) or code/data selector */
1762	unsigned u1DescType : 1;
1763	/** Descriptor Privelege level. */
1764	unsigned u2Dpl : 2;
1765	/** Flags selector present(=1) or not. */
1766	unsigned u1Present : 1;
1767	/** Segment limit 16-19. */
1768	unsigned u4LimitHigh : 4;
1769	/** Available for system software. */
1770	unsigned u1Available : 1;
1771	/** Reserved - 0. */
1772	unsigned u1Reserved : 1;
1773	/** This flags meaning depends on the segment type. Try make sense out
1774	* of the intel manual yourself. */
1775	unsigned u1DefBig : 1;
1776	/** Granularity of the limit. If set 4KB granularity is used, if
1777	* clear byte. */
1778	unsigned u1Granularity : 1;
1779	/** Base address - highest 8 bits. */
1780	unsigned u8BaseHigh2 : 8;
1781	} X86DESCGENERIC;
1782	#pragma pack()
1783	/** Pointer to a generic descriptor entry. */
1784	typedef X86DESCGENERIC *PX86DESCGENERIC;
1785	/** Pointer to a const generic descriptor entry. */
1786	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1787
1788
1789	/**
1790	* Descriptor attributes.
1791	*/
1792	typedef struct X86DESCATTRBITS
1793	{
1794	/** Segment Type. */
1795	unsigned u4Type : 4;
1796	/** Descriptor Type. System(=0) or code/data selector */
1797	unsigned u1DescType : 1;
1798	/** Descriptor Privelege level. */
1799	unsigned u2Dpl : 2;
1800	/** Flags selector present(=1) or not. */
1801	unsigned u1Present : 1;
1802	/** Segment limit 16-19. */
1803	unsigned u4LimitHigh : 4;
1804	/** Available for system software. */
1805	unsigned u1Available : 1;
1806	/** Reserved - 0. */
1807	unsigned u1Reserved : 1;
1808	/** This flags meaning depends on the segment type. Try make sense out
1809	* of the intel manual yourself. */
1810	unsigned u1DefBig : 1;
1811	/** Granularity of the limit. If set 4KB granularity is used, if
1812	* clear byte. */
1813	unsigned u1Granularity : 1;
1814	} X86DESCATTRBITS;
1815
1816
1817	#pragma pack(1)
1818	typedef union X86DESCATTR
1819	{
1820	/** Normal view. */
1821	X86DESCATTRBITS n;
1822	/** Unsigned integer view. */
1823	uint32_t u;
1824	} X86DESCATTR;
1825	#pragma pack()
1826
1827	/** Pointer to descriptor attributes. */
1828	typedef X86DESCATTR *PX86DESCATTR;
1829	/** Pointer to const descriptor attributes. */
1830	typedef const X86DESCATTR *PCX86DESCATTR;
1831
1832
1833	/**
1834	* Descriptor table entry.
1835	*/
1836	#pragma pack(1)
1837	typedef union X86DESC
1838	{
1839	/** Generic descriptor view. */
1840	X86DESCGENERIC Gen;
1841	#if 0
1842	/** IDT view. */
1843	VBOXIDTE Idt;
1844	#endif
1845
1846	/** 8 bit unsigned interger view. */
1847	uint8_t au8[8];
1848	/** 16 bit unsigned interger view. */
1849	uint16_t au16[4];
1850	/** 32 bit unsigned interger view. */
1851	uint32_t au32[2];
1852	} X86DESC;
1853	#pragma pack()
1854	/** Pointer to descriptor table entry. */
1855	typedef X86DESC *PX86DESC;
1856	/** Pointer to const descriptor table entry. */
1857	typedef const X86DESC *PCX86DESC;
1858
1859
1860	/**
1861	* 64 bits generic descriptor table entry
1862	* Note: most of these bits have no meaning in long mode.
1863	*/
1864	#pragma pack(1)
1865	typedef struct X86DESC64GENERIC
1866	{
1867	/** Limit - Low word - IGNORED. */
1868	unsigned u16LimitLow : 16;
1869	/** Base address - lowe word. - IGNORED
1870	* Don't try set this to 24 because MSC is doing studing things then. */
1871	unsigned u16BaseLow : 16;
1872	/** Base address - first 8 bits of high word. - IGNORED */
1873	unsigned u8BaseHigh1 : 8;
1874	/** Segment Type. */
1875	unsigned u4Type : 4;
1876	/** Descriptor Type. System(=0) or code/data selector */
1877	unsigned u1DescType : 1;
1878	/** Descriptor Privelege level. */
1879	unsigned u2Dpl : 2;
1880	/** Flags selector present(=1) or not. */
1881	unsigned u1Present : 1;
1882	/** Segment limit 16-19. - IGNORED */
1883	unsigned u4LimitHigh : 4;
1884	/** Available for system software. - IGNORED */
1885	unsigned u1Available : 1;
1886	/** Long mode flag. */
1887	unsigned u1Long : 1;
1888	/** This flags meaning depends on the segment type. Try make sense out
1889	* of the intel manual yourself. */
1890	unsigned u1DefBig : 1;
1891	/** Granularity of the limit. If set 4KB granularity is used, if
1892	* clear byte. - IGNORED */
1893	unsigned u1Granularity : 1;
1894	/** Base address - highest 8 bits. - IGNORED */
1895	unsigned u8BaseHigh2 : 8;
1896	/** Base address - bits 63-32. */
1897	unsigned u32BaseHigh3 : 32;
1898	unsigned u8Reserved : 8;
1899	unsigned u5Zeros : 5;
1900	unsigned u19Reserved : 19;
1901	} X86DESC64GENERIC;
1902	#pragma pack()
1903	/** Pointer to a generic descriptor entry. */
1904	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1905	/** Pointer to a const generic descriptor entry. */
1906	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1907
1908	/**
1909	* System descriptor table entry (64 bits)
1910	*/
1911	#pragma pack(1)
1912	typedef struct X86DESC64SYSTEM
1913	{
1914	/** Limit - Low word. */
1915	unsigned u16LimitLow : 16;
1916	/** Base address - lowe word.
1917	* Don't try set this to 24 because MSC is doing studing things then. */
1918	unsigned u16BaseLow : 16;
1919	/** Base address - first 8 bits of high word. */
1920	unsigned u8BaseHigh1 : 8;
1921	/** Segment Type. */
1922	unsigned u4Type : 4;
1923	/** Descriptor Type. System(=0) or code/data selector */
1924	unsigned u1DescType : 1;
1925	/** Descriptor Privelege level. */
1926	unsigned u2Dpl : 2;
1927	/** Flags selector present(=1) or not. */
1928	unsigned u1Present : 1;
1929	/** Segment limit 16-19. */
1930	unsigned u4LimitHigh : 4;
1931	/** Available for system software. */
1932	unsigned u1Available : 1;
1933	/** Reserved - 0. */
1934	unsigned u1Reserved : 1;
1935	/** This flags meaning depends on the segment type. Try make sense out
1936	* of the intel manual yourself. */
1937	unsigned u1DefBig : 1;
1938	/** Granularity of the limit. If set 4KB granularity is used, if
1939	* clear byte. */
1940	unsigned u1Granularity : 1;
1941	/** Base address - bits 31-24. */
1942	unsigned u8BaseHigh2 : 8;
1943	/** Base address - bits 63-32. */
1944	unsigned u32BaseHigh3 : 32;
1945	unsigned u8Reserved : 8;
1946	unsigned u5Zeros : 5;
1947	unsigned u19Reserved : 19;
1948	} X86DESC64SYSTEM;
1949	#pragma pack()
1950	/** Pointer to a generic descriptor entry. */
1951	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1952	/** Pointer to a const generic descriptor entry. */
1953	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1954
1955
1956	/**
1957	* Descriptor table entry.
1958	*/
1959	#pragma pack(1)
1960	typedef union X86DESC64
1961	{
1962	/** Generic descriptor view. */
1963	X86DESC64GENERIC Gen;
1964	/** System descriptor view. */
1965	X86DESC64SYSTEM System;
1966	#if 0
1967	X86DESC64GATE Gate;
1968	#endif
1969
1970	/** 8 bit unsigned interger view. */
1971	uint8_t au8[16];
1972	/** 16 bit unsigned interger view. */
1973	uint16_t au16[8];
1974	/** 32 bit unsigned interger view. */
1975	uint32_t au32[4];
1976	/** 64 bit unsigned interger view. */
1977	uint64_t au64[2];
1978	} X86DESC64;
1979	#pragma pack()
1980	/** Pointer to descriptor table entry. */
1981	typedef X86DESC64 *PX86DESC64;
1982	/** Pointer to const descriptor table entry. */
1983	typedef const X86DESC64 *PCX86DESC64;
1984
1985	#if HC_ARCH_BITS == 64
1986	typedef X86DESC64 X86DESCHC;
1987	typedef X86DESC64 *PX86DESCHC;
1988	#else
1989	typedef X86DESC X86DESCHC;
1990	typedef X86DESC *PX86DESCHC;
1991	#endif
1992
1993	/** @name Selector Descriptor Types.
1994	* @{
1995	*/
1996
1997	/** @name Non-System Selector Types.
1998	* @{ */
1999	/** Code(=set)/Data(=clear) bit. */
2000	#define X86_SEL_TYPE_CODE 8
2001	/** Memory(=set)/System(=clear) bit. */
2002	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2003	/** Accessed bit. */
2004	#define X86_SEL_TYPE_ACCESSED 1
2005	/** Expand down bit (for data selectors only). */
2006	#define X86_SEL_TYPE_DOWN 4
2007	/** Conforming bit (for code selectors only). */
2008	#define X86_SEL_TYPE_CONF 4
2009	/** Write bit (for data selectors only). */
2010	#define X86_SEL_TYPE_WRITE 2
2011	/** Read bit (for code selectors only). */
2012	#define X86_SEL_TYPE_READ 2
2013
2014	/** Read only selector type. */
2015	#define X86_SEL_TYPE_RO 0
2016	/** Accessed read only selector type. */
2017	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2018	/** Read write selector type. */
2019	#define X86_SEL_TYPE_RW 2
2020	/** Accessed read write selector type. */
2021	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2022	/** Expand down read only selector type. */
2023	#define X86_SEL_TYPE_RO_DOWN 4
2024	/** Accessed expand down read only selector type. */
2025	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2026	/** Expand down read write selector type. */
2027	#define X86_SEL_TYPE_RW_DOWN 6
2028	/** Accessed expand down read write selector type. */
2029	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2030	/** Execute only selector type. */
2031	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2032	/** Accessed execute only selector type. */
2033	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2034	/** Execute and read selector type. */
2035	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2036	/** Accessed execute and read selector type. */
2037	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2038	/** Conforming execute only selector type. */
2039	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2040	/** Accessed Conforming execute only selector type. */
2041	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2042	/** Conforming execute and write selector type. */
2043	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2044	/** Accessed Conforming execute and write selector type. */
2045	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2046	/** @} */
2047
2048
2049	/** @name System Selector Types.
2050	* @{ */
2051	/** Undefined system selector type. */
2052	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2053	/** 286 TSS selector. */
2054	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2055	/** LDT selector. */
2056	#define X86_SEL_TYPE_SYS_LDT 2
2057	/** 286 TSS selector - Busy. */
2058	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2059	/** 286 Callgate selector. */
2060	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2061	/** Taskgate selector. */
2062	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2063	/** 286 Interrupt gate selector. */
2064	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2065	/** 286 Trapgate selector. */
2066	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2067	/** Undefined system selector. */
2068	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2069	/** 386 TSS selector. */
2070	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2071	/** Undefined system selector. */
2072	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2073	/** 386 TSS selector - Busy. */
2074	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2075	/** 386 Callgate selector. */
2076	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2077	/** Undefined system selector. */
2078	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2079	/** 386 Interruptgate selector. */
2080	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2081	/** 386 Trapgate selector. */
2082	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2083	/** @} */
2084
2085	/** @name AMD64 System Selector Types.
2086	* @{ */
2087	#define AMD64_SEL_TYPE_SYS_LDT 2
2088	/** 286 TSS selector - Busy. */
2089	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2090	/** 386 TSS selector - Busy. */
2091	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2092	/** 386 Callgate selector. */
2093	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2094	/** 386 Interruptgate selector. */
2095	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2096	/** 386 Trapgate selector. */
2097	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2098	/** @} */
2099
2100	/** @} */
2101
2102
2103	/** @name Descriptor Table Entry Flag Masks.
2104	* These are for the 2nd 32-bit word of a descriptor.
2105	* @{ */
2106	/** Bits 8-11 - TYPE - Descriptor type mask. */
2107	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2108	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2109	#define X86_DESC_S RT_BIT(12)
2110	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2111	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2112	/** Bit 15 - P - Present. */
2113	#define X86_DESC_P RT_BIT(15)
2114	/** Bit 20 - AVL - Available for system software. */
2115	#define X86_DESC_AVL RT_BIT(20)
2116	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2117	#define X86_DESC_DB RT_BIT(22)
2118	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2119	* used, if clear byte. */
2120	#define X86_DESC_G RT_BIT(23)
2121	/** @} */
2122
2123	/** @} */
2124
2125
2126	/** @name Selectors.
2127	* @{
2128	*/
2129
2130	/**
2131	* The shift used to convert a selector from and to index an index (C).
2132	*/
2133	#define X86_SEL_SHIFT 3
2134
2135	/**
2136	* The shift used to convert a selector from and to index an index (C).
2137	*/
2138	#define AMD64_SEL_SHIFT 4
2139
2140	#if HC_ARCH_BITS == 64
2141	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2142	#else
2143	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2144	#endif
2145
2146	/**
2147	* The mask used to mask off the table indicator and CPL of an selector.
2148	*/
2149	#define X86_SEL_MASK 0xfff8
2150
2151	/**
2152	* The bit indicating that a selector is in the LDT and not in the GDT.
2153	*/
2154	#define X86_SEL_LDT 0x0004
2155	/**
2156	* The bit mask for getting the RPL of a selector.
2157	*/
2158	#define X86_SEL_RPL 0x0003
2159
2160	/** @} */
2161
2162
2163	/**
2164	* x86 Exceptions/Faults/Traps.
2165	*/
2166	typedef enum X86XCPT
2167	{
2168	/** \#DE - Divide error. */
2169	X86_XCPT_DE = 0x00,
2170	/** \#DB - Debug event (single step, DRx, ..) */
2171	X86_XCPT_DB = 0x01,
2172	/** NMI - Non-Maskable Interrupt */
2173	X86_XCPT_NMI = 0x02,
2174	/** \#BP - Breakpoint (INT3). */
2175	X86_XCPT_BP = 0x03,
2176	/** \#OF - Overflow (INTO). */
2177	X86_XCPT_OF = 0x04,
2178	/** \#BR - Bound range exceeded (BOUND). */
2179	X86_XCPT_BR = 0x05,
2180	/** \#UD - Undefined opcode. */
2181	X86_XCPT_UD = 0x06,
2182	/** \#NM - Device not available (math coprocessor device). */
2183	X86_XCPT_NM = 0x07,
2184	/** \#DF - Double fault. */
2185	X86_XCPT_DF = 0x08,
2186	/** ??? - Coprocessor segment overrun (obsolete). */
2187	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2188	/** \#TS - Taskswitch (TSS). */
2189	X86_XCPT_TS = 0x0a,
2190	/** \#NP - Segment no present. */
2191	X86_XCPT_NP = 0x0b,
2192	/** \#SS - Stack segment fault. */
2193	X86_XCPT_SS = 0x0c,
2194	/** \#GP - General protection fault. */
2195	X86_XCPT_GP = 0x0d,
2196	/** \#PF - Page fault. */
2197	X86_XCPT_PF = 0x0e,
2198	/* 0x0f is reserved. */
2199	/** \#MF - Math fault (FPU). */
2200	X86_XCPT_MF = 0x10,
2201	/** \#AC - Alignment check. */
2202	X86_XCPT_AC = 0x11,
2203	/** \#MC - Machine check. */
2204	X86_XCPT_MC = 0x12,
2205	/** \#XF - SIMD Floating-Pointer Exception. */
2206	X86_XCPT_XF = 0x13
2207	} X86XCPT;
2208	/** Pointer to a x86 exception code. */
2209	typedef X86XCPT *PX86XCPT;
2210	/** Pointer to a const x86 exception code. */
2211	typedef const X86XCPT *PCX86XCPT;
2212
2213
2214	/** @name Trap Error Codes
2215	* @{
2216	*/
2217	/** External indicator. */
2218	#define X86_TRAP_ERR_EXTERNAL 1
2219	/** IDT indicator. */
2220	#define X86_TRAP_ERR_IDT 2
2221	/** Descriptor table indicator - If set LDT, if clear GDT. */
2222	#define X86_TRAP_ERR_TI 4
2223	/** Mask for getting the selector. */
2224	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2225	/** Shift for getting the selector table index (C type index). */
2226	#define X86_TRAP_ERR_SEL_SHIFT 3
2227	/** @} */
2228
2229
2230	/** @name \#PF Trap Error Codes
2231	* @{
2232	*/
2233	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2234	#define X86_TRAP_PF_P RT_BIT(0)
2235	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2236	#define X86_TRAP_PF_RW RT_BIT(1)
2237	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2238	#define X86_TRAP_PF_US RT_BIT(2)
2239	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2240	#define X86_TRAP_PF_RSVD RT_BIT(3)
2241	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2242	#define X86_TRAP_PF_ID RT_BIT(4)
2243	/** @} */
2244
2245	#pragma pack(1)
2246	/**
2247	* 32-bit IDTR/GDTR.
2248	*/
2249	typedef struct X86XDTR32
2250	{
2251	/** Size of the descriptor table. */
2252	uint16_t cb;
2253	/** Address of the descriptor table. */
2254	uint32_t uAddr;
2255	} X86XDTR32, *PX86XDTR32;
2256	#pragma pack()
2257
2258	#pragma pack(1)
2259	/**
2260	* 64-bit IDTR/GDTR.
2261	*/
2262	typedef struct X86XDTR64
2263	{
2264	/** Size of the descriptor table. */
2265	uint16_t cb;
2266	/** Address of the descriptor table. */
2267	uint64_t uAddr;
2268	} X86XDTR64, *PX86XDTR64;
2269	#pragma pack()
2270
2271	/** @} */
2272
2273	#endif
2274

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