[1] | 1 | /** @file
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| 2 | * X86 (and AMD64) Structures and Definitions.
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| 3 | */
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| 4 |
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| 5 | /*
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[2981] | 6 | * Copyright (C) 2006-2007 innotek GmbH
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[1] | 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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[1] | 24 | */
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| 25 |
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| 26 | /*
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| 27 | * x86.mac is generated from this file using:
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| 28 | * sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
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| 29 | */
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| 30 |
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[3632] | 31 | #ifndef ___VBox_x86_h
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| 32 | #define ___VBox_x86_h
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[1] | 33 |
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| 34 | #include <VBox/types.h>
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| 35 |
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[3913] | 36 | /* Workaround for Solaris sys/regset.h defining CS, DS */
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| 37 | #if defined(RT_OS_SOLARIS)
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| 38 | # undef CS
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| 39 | # undef DS
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| 40 | #endif
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| 41 |
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[1] | 42 | /** @defgroup grp_x86 x86 Types and Definitions
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| 43 | * @{
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| 44 | */
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| 45 |
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| 46 | /**
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| 47 | * EFLAGS Bits.
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| 48 | */
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| 49 | typedef struct X86EFLAGSBITS
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| 50 | {
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| 51 | /** Bit 0 - CF - Carry flag - Status flag. */
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| 52 | unsigned u1CF : 1;
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| 53 | /** Bit 1 - 1 - Reserved flag. */
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| 54 | unsigned u1Reserved0 : 1;
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| 55 | /** Bit 2 - PF - Parity flag - Status flag. */
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| 56 | unsigned u1PF : 1;
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| 57 | /** Bit 3 - 0 - Reserved flag. */
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| 58 | unsigned u1Reserved1 : 1;
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| 59 | /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
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| 60 | unsigned u1AF : 1;
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| 61 | /** Bit 5 - 0 - Reserved flag. */
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| 62 | unsigned u1Reserved2 : 1;
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| 63 | /** Bit 6 - ZF - Zero flag - Status flag. */
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| 64 | unsigned u1ZF : 1;
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| 65 | /** Bit 7 - SF - Signed flag - Status flag. */
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| 66 | unsigned u1SF : 1;
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| 67 | /** Bit 8 - TF - Trap flag - System flag. */
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| 68 | unsigned u1TF : 1;
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| 69 | /** Bit 9 - IF - Interrupt flag - System flag. */
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| 70 | unsigned u1IF : 1;
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| 71 | /** Bit 10 - DF - Direction flag - Control flag. */
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| 72 | unsigned u1DF : 1;
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| 73 | /** Bit 11 - OF - Overflow flag - Status flag. */
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| 74 | unsigned u1OF : 1;
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| 75 | /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
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| 76 | unsigned u2IOPL : 2;
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| 77 | /** Bit 14 - NT - Nested task flag - System flag. */
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| 78 | unsigned u1NT : 1;
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| 79 | /** Bit 15 - 0 - Reserved flag. */
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| 80 | unsigned u1Reserved3 : 1;
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| 81 | /** Bit 16 - RF - Resume flag - System flag. */
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| 82 | unsigned u1RF : 1;
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| 83 | /** Bit 17 - VM - Virtual 8086 mode - System flag. */
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| 84 | unsigned u1VM : 1;
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| 85 | /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
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| 86 | unsigned u1AC : 1;
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| 87 | /** Bit 19 - VIF - Virtual interupt flag - System flag. */
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| 88 | unsigned u1VIF : 1;
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| 89 | /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
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| 90 | unsigned u1VIP : 1;
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| 91 | /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
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| 92 | unsigned u1ID : 1;
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| 93 | /** Bit 22-31 - 0 - Reserved flag. */
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| 94 | unsigned u10Reserved4 : 10;
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| 95 | } X86EFLAGSBITS;
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| 96 | /** Pointer to EFLAGS bits. */
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| 97 | typedef X86EFLAGSBITS *PX86EFLAGSBITS;
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| 98 | /** Pointer to const EFLAGS bits. */
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| 99 | typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
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| 100 |
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| 101 | /**
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| 102 | * EFLAGS.
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| 103 | */
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| 104 | typedef union X86EFLAGS
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| 105 | {
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| 106 | /** The bitfield view. */
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| 107 | X86EFLAGSBITS Bits;
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| 108 | /** The 8-bit view. */
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| 109 | uint8_t au8[4];
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| 110 | /** The 16-bit view. */
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| 111 | uint16_t au16[2];
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| 112 | /** The 32-bit view. */
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| 113 | uint32_t au32[1];
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| 114 | /** The 32-bit view. */
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| 115 | uint32_t u32;
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[7121] | 116 | /** The plain unsigned view. */
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| 117 | uint32_t u;
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[1] | 118 | } X86EFLAGS;
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| 119 | /** Pointer to EFLAGS. */
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| 120 | typedef X86EFLAGS *PX86EFLAGS;
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| 121 | /** Pointer to const EFLAGS. */
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| 122 | typedef const X86EFLAGS *PCX86EFLAGS;
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| 123 |
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[7095] | 124 | /**
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[7121] | 125 | * RFLAGS (32 upper bits are reserved).
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[7095] | 126 | */
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| 127 | typedef union X86RFLAGS
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| 128 | {
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| 129 | /** The bitfield view. */
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| 130 | X86EFLAGSBITS Bits;
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| 131 | /** The 8-bit view. */
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| 132 | uint8_t au8[8];
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| 133 | /** The 16-bit view. */
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| 134 | uint16_t au16[4];
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| 135 | /** The 32-bit view. */
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| 136 | uint32_t au32[2];
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| 137 | /** The 64-bit view. */
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| 138 | uint64_t au64[1];
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| 139 | /** The 64-bit view. */
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[7096] | 140 | uint64_t u64;
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[7121] | 141 | /** The plain unsigned view. */
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| 142 | uint64_t u;
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[7095] | 143 | } X86RFLAGS;
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| 144 | /** Pointer to RFLAGS. */
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| 145 | typedef X86RFLAGS *PX86RFLAGS;
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| 146 | /** Pointer to const RFLAGS. */
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| 147 | typedef const X86RFLAGS *PCX86RFLAGS;
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[1] | 148 |
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[7095] | 149 |
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[1] | 150 | /** @name EFLAGS
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| 151 | * @{
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| 152 | */
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| 153 | /** Bit 0 - CF - Carry flag - Status flag. */
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[5605] | 154 | #define X86_EFL_CF RT_BIT(0)
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[1] | 155 | /** Bit 2 - PF - Parity flag - Status flag. */
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[5605] | 156 | #define X86_EFL_PF RT_BIT(2)
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[1] | 157 | /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
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[5605] | 158 | #define X86_EFL_AF RT_BIT(4)
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[1] | 159 | /** Bit 6 - ZF - Zero flag - Status flag. */
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[5605] | 160 | #define X86_EFL_ZF RT_BIT(6)
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[1] | 161 | /** Bit 7 - SF - Signed flag - Status flag. */
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[5605] | 162 | #define X86_EFL_SF RT_BIT(7)
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[1] | 163 | /** Bit 8 - TF - Trap flag - System flag. */
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[5605] | 164 | #define X86_EFL_TF RT_BIT(8)
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[1] | 165 | /** Bit 9 - IF - Interrupt flag - System flag. */
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[5605] | 166 | #define X86_EFL_IF RT_BIT(9)
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[1] | 167 | /** Bit 10 - DF - Direction flag - Control flag. */
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[5605] | 168 | #define X86_EFL_DF RT_BIT(10)
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[1] | 169 | /** Bit 11 - OF - Overflow flag - Status flag. */
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[5605] | 170 | #define X86_EFL_OF RT_BIT(11)
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[1] | 171 | /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
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[5605] | 172 | #define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
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[1] | 173 | /** Bit 14 - NT - Nested task flag - System flag. */
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[5605] | 174 | #define X86_EFL_NT RT_BIT(14)
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[1] | 175 | /** Bit 16 - RF - Resume flag - System flag. */
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[5605] | 176 | #define X86_EFL_RF RT_BIT(16)
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[1] | 177 | /** Bit 17 - VM - Virtual 8086 mode - System flag. */
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[5605] | 178 | #define X86_EFL_VM RT_BIT(17)
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[1] | 179 | /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
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[5605] | 180 | #define X86_EFL_AC RT_BIT(18)
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[1] | 181 | /** Bit 19 - VIF - Virtual interupt flag - System flag. */
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[5605] | 182 | #define X86_EFL_VIF RT_BIT(19)
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[1] | 183 | /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
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[5605] | 184 | #define X86_EFL_VIP RT_BIT(20)
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[1] | 185 | /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
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[5605] | 186 | #define X86_EFL_ID RT_BIT(21)
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[1] | 187 | /** IOPL shift. */
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| 188 | #define X86_EFL_IOPL_SHIFT 12
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| 189 | /** The the IOPL level from the flags. */
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| 190 | #define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
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| 191 | /** @} */
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| 192 |
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| 193 |
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| 194 | /** CPUID Feature information - ECX.
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| 195 | * CPUID query with EAX=1.
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| 196 | */
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| 197 | typedef struct X86CPUIDFEATECX
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| 198 | {
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| 199 | /** Bit 0 - SSE3 - Supports SSE3 or not. */
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| 200 | unsigned u1SSE3 : 1;
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| 201 | /** Reserved. */
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| 202 | unsigned u2Reserved1 : 2;
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| 203 | /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
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| 204 | unsigned u1Monitor : 1;
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| 205 | /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
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| 206 | unsigned u1CPLDS : 1;
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| 207 | /** Bit 5 - VMX - Virtual Machine Technology. */
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| 208 | unsigned u1VMX : 1;
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| 209 | /** Reserved. */
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| 210 | unsigned u1Reserved2 : 1;
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| 211 | /** Bit 7 - EST - Enh. SpeedStep Tech. */
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| 212 | unsigned u1EST : 1;
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| 213 | /** Bit 8 - TM2 - Terminal Monitor 2. */
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| 214 | unsigned u1TM2 : 1;
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[4425] | 215 | /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
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| 216 | unsigned u1SSSE3 : 1;
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[1] | 217 | /** Bit 10 - CNTX-ID - L1 Context ID. */
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| 218 | unsigned u1CNTXID : 1;
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| 219 | /** Reserved. */
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| 220 | unsigned u2Reserved4 : 2;
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| 221 | /** Bit 13 - CX16 - CMPXCHG16B. */
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| 222 | unsigned u1CX16 : 1;
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[4425] | 223 | /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
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| 224 | unsigned u1TPRUpdate : 1;
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[1] | 225 | /** Reserved. */
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[4425] | 226 | unsigned u17Reserved5 : 17;
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[1] | 227 |
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| 228 | } X86CPUIDFEATECX;
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| 229 | /** Pointer to CPUID Feature Information - ECX. */
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| 230 | typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
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| 231 | /** Pointer to const CPUID Feature Information - ECX. */
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| 232 | typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
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| 233 |
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| 234 |
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| 235 | /** CPUID Feature Information - EDX.
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| 236 | * CPUID query with EAX=1.
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| 237 | */
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| 238 | typedef struct X86CPUIDFEATEDX
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| 239 | {
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| 240 | /** Bit 0 - FPU - x87 FPU on Chip. */
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| 241 | unsigned u1FPU : 1;
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| 242 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
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| 243 | unsigned u1VME : 1;
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| 244 | /** Bit 2 - DE - Debugging extensions. */
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| 245 | unsigned u1DE : 1;
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| 246 | /** Bit 3 - PSE - Page Size Extension. */
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| 247 | unsigned u1PSE : 1;
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[5191] | 248 | /** Bit 4 - TSC - Time Stamp Counter. */
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[1] | 249 | unsigned u1TSC : 1;
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| 250 | /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
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| 251 | unsigned u1MSR : 1;
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| 252 | /** Bit 6 - PAE - Physical Address Extension. */
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| 253 | unsigned u1PAE : 1;
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| 254 | /** Bit 7 - MCE - Machine Check Exception. */
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| 255 | unsigned u1MCE : 1;
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| 256 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
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| 257 | unsigned u1CX8 : 1;
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| 258 | /** Bit 9 - APIC - APIC On-Chick. */
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| 259 | unsigned u1APIC : 1;
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| 260 | /** Bit 10 - Reserved. */
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| 261 | unsigned u1Reserved1 : 1;
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| 262 | /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
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| 263 | unsigned u1SEP : 1;
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| 264 | /** Bit 12 - MTRR - Memory Type Range Registers. */
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| 265 | unsigned u1MTRR : 1;
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| 266 | /** Bit 13 - PGE - PTE Global Bit. */
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| 267 | unsigned u1PGE : 1;
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| 268 | /** Bit 14 - MCA - Machine Check Architecture. */
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| 269 | unsigned u1MCA : 1;
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| 270 | /** Bit 15 - CMOV - Conditional Move Instructions. */
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| 271 | unsigned u1CMOV : 1;
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| 272 | /** Bit 16 - PAT - Page Attribute Table. */
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| 273 | unsigned u1PAT : 1;
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| 274 | /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
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| 275 | unsigned u1PSE36 : 1;
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| 276 | /** Bit 18 - PSN - Processor Serial Number. */
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| 277 | unsigned u1PSN : 1;
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| 278 | /** Bit 19 - CLFSH - CLFLUSH Instruction. */
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| 279 | unsigned u1CLFSH : 1;
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| 280 | /** Bit 20 - Reserved. */
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| 281 | unsigned u1Reserved2 : 1;
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| 282 | /** Bit 21 - DS - Debug Store. */
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| 283 | unsigned u1DS : 1;
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| 284 | /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
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| 285 | unsigned u1ACPI : 1;
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| 286 | /** Bit 23 - MMX - Intel MMX 'Technology'. */
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| 287 | unsigned u1MMX : 1;
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| 288 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
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| 289 | unsigned u1FXSR : 1;
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| 290 | /** Bit 25 - SSE - SSE Support. */
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| 291 | unsigned u1SSE : 1;
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| 292 | /** Bit 26 - SSE2 - SSE2 Support. */
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| 293 | unsigned u1SSE2 : 1;
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| 294 | /** Bit 27 - SS - Self Snoop. */
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| 295 | unsigned u1SS : 1;
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| 296 | /** Bit 28 - HTT - Hyper-Threading Technology. */
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| 297 | unsigned u1HTT : 1;
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| 298 | /** Bit 29 - TM - Thermal Monitor. */
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| 299 | unsigned u1TM : 1;
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| 300 | /** Bit 30 - Reserved - . */
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| 301 | unsigned u1Reserved3 : 1;
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| 302 | /** Bit 31 - PBE - Pending Break Enabled. */
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| 303 | unsigned u1PBE : 1;
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| 304 | } X86CPUIDFEATEDX;
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| 305 | /** Pointer to CPUID Feature Information - EDX. */
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| 306 | typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
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| 307 | /** Pointer to const CPUID Feature Information - EDX. */
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| 308 | typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
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| 309 |
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[3941] | 310 | /** @name CPUID Vendor information.
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| 311 | * CPUID query with EAX=0.
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| 312 | * @{
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| 313 | */
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[3942] | 314 | #define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
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| 315 | #define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
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| 316 | #define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
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[1] | 317 |
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[3942] | 318 | #define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
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| 319 | #define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
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| 320 | #define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
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[3941] | 321 | /** @} */
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| 322 |
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| 323 |
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[1] | 324 | /** @name CPUID Feature information.
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| 325 | * CPUID query with EAX=1.
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| 326 | * @{
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| 327 | */
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| 328 | /** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
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[5605] | 329 | #define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
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[1] | 330 | /** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
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[5605] | 331 | #define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
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[1] | 332 | /** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
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[5605] | 333 | #define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
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[1] | 334 | /** ECX Bit 5 - VMX - Virtual Machine Technology. */
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[5605] | 335 | #define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
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[1] | 336 | /** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
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[5605] | 337 | #define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
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[1] | 338 | /** ECX Bit 8 - TM2 - Terminal Monitor 2. */
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[5605] | 339 | #define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
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[4425] | 340 | /** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
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[5605] | 341 | #define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
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[1] | 342 | /** ECX Bit 10 - CNTX-ID - L1 Context ID. */
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[5605] | 343 | #define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
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[4425] | 344 | /** ECX Bit 13 - CX16 - CMPXCHG16B. */
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[5605] | 345 | #define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
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[4425] | 346 | /** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
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[5605] | 347 | #define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
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[4425] | 348 | /** ECX Bit 23 - POPCOUNT instruction. */
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[5605] | 349 | #define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
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[1] | 350 |
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| 351 |
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| 352 | /** Bit 0 - FPU - x87 FPU on Chip. */
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[5605] | 353 | #define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
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[1] | 354 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
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[5605] | 355 | #define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
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[1] | 356 | /** Bit 2 - DE - Debugging extensions. */
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[5605] | 357 | #define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
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[1] | 358 | /** Bit 3 - PSE - Page Size Extension. */
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[5605] | 359 | #define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
|
---|
[1] | 360 | /** Bit 4 - TSC - Time Stamp Counter. */
|
---|
[5605] | 361 | #define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
|
---|
[1] | 362 | /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
|
---|
[5605] | 363 | #define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
|
---|
[1] | 364 | /** Bit 6 - PAE - Physical Address Extension. */
|
---|
[5605] | 365 | #define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
|
---|
[1] | 366 | /** Bit 7 - MCE - Machine Check Exception. */
|
---|
[5605] | 367 | #define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
|
---|
[1] | 368 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
|
---|
[5605] | 369 | #define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
|
---|
[1] | 370 | /** Bit 9 - APIC - APIC On-Chip. */
|
---|
[5605] | 371 | #define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
|
---|
[1] | 372 | /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
|
---|
[5605] | 373 | #define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
|
---|
[1] | 374 | /** Bit 12 - MTRR - Memory Type Range Registers. */
|
---|
[5605] | 375 | #define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
|
---|
[1] | 376 | /** Bit 13 - PGE - PTE Global Bit. */
|
---|
[5605] | 377 | #define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
|
---|
[1] | 378 | /** Bit 14 - MCA - Machine Check Architecture. */
|
---|
[5605] | 379 | #define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
|
---|
[1] | 380 | /** Bit 15 - CMOV - Conditional Move Instructions. */
|
---|
[5605] | 381 | #define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
|
---|
[1] | 382 | /** Bit 16 - PAT - Page Attribute Table. */
|
---|
[5605] | 383 | #define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
|
---|
[1] | 384 | /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
|
---|
[5605] | 385 | #define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
|
---|
[1] | 386 | /** Bit 18 - PSN - Processor Serial Number. */
|
---|
[5605] | 387 | #define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
|
---|
[1] | 388 | /** Bit 19 - CLFSH - CLFLUSH Instruction. */
|
---|
[5605] | 389 | #define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
|
---|
[1] | 390 | /** Bit 21 - DS - Debug Store. */
|
---|
[5605] | 391 | #define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
|
---|
[1] | 392 | /** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
|
---|
[5605] | 393 | #define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
|
---|
[1] | 394 | /** Bit 23 - MMX - Intel MMX Technology. */
|
---|
[5605] | 395 | #define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
|
---|
[1] | 396 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
|
---|
[5605] | 397 | #define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
|
---|
[1] | 398 | /** Bit 25 - SSE - SSE Support. */
|
---|
[5605] | 399 | #define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
|
---|
[1] | 400 | /** Bit 26 - SSE2 - SSE2 Support. */
|
---|
[5605] | 401 | #define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
|
---|
[1] | 402 | /** Bit 27 - SS - Self Snoop. */
|
---|
[5605] | 403 | #define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
|
---|
[1] | 404 | /** Bit 28 - HTT - Hyper-Threading Technology. */
|
---|
[5605] | 405 | #define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
|
---|
[1] | 406 | /** Bit 29 - TM - Therm. Monitor. */
|
---|
[5605] | 407 | #define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
|
---|
[1] | 408 | /** Bit 31 - PBE - Pending Break Enabled. */
|
---|
[5605] | 409 | #define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
|
---|
[1] | 410 | /** @} */
|
---|
| 411 |
|
---|
| 412 |
|
---|
| 413 | /** @name CPUID AMD Feature information.
|
---|
| 414 | * CPUID query with EAX=0x80000001.
|
---|
| 415 | * @{
|
---|
| 416 | */
|
---|
| 417 | /** Bit 0 - FPU - x87 FPU on Chip. */
|
---|
[5605] | 418 | #define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
|
---|
[1] | 419 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
|
---|
[5605] | 420 | #define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
|
---|
[1] | 421 | /** Bit 2 - DE - Debugging extensions. */
|
---|
[5605] | 422 | #define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
|
---|
[1] | 423 | /** Bit 3 - PSE - Page Size Extension. */
|
---|
[5605] | 424 | #define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
|
---|
[1] | 425 | /** Bit 4 - TSC - Time Stamp Counter. */
|
---|
[5605] | 426 | #define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
|
---|
[1] | 427 | /** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
|
---|
[5605] | 428 | #define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
|
---|
[1] | 429 | /** Bit 6 - PAE - Physical Address Extension. */
|
---|
[5605] | 430 | #define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
|
---|
[1] | 431 | /** Bit 7 - MCE - Machine Check Exception. */
|
---|
[5605] | 432 | #define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
|
---|
[1] | 433 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
|
---|
[5605] | 434 | #define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
|
---|
[1] | 435 | /** Bit 9 - APIC - APIC On-Chip. */
|
---|
[5605] | 436 | #define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
|
---|
[1] | 437 | /** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
|
---|
[5605] | 438 | #define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
|
---|
[1] | 439 | /** Bit 12 - MTRR - Memory Type Range Registers. */
|
---|
[5605] | 440 | #define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
|
---|
[1] | 441 | /** Bit 13 - PGE - PTE Global Bit. */
|
---|
[5605] | 442 | #define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
|
---|
[1] | 443 | /** Bit 14 - MCA - Machine Check Architecture. */
|
---|
[5605] | 444 | #define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
|
---|
[1] | 445 | /** Bit 15 - CMOV - Conditional Move Instructions. */
|
---|
[5605] | 446 | #define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
|
---|
[1] | 447 | /** Bit 16 - PAT - Page Attribute Table. */
|
---|
[5605] | 448 | #define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
|
---|
[1] | 449 | /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
|
---|
[5605] | 450 | #define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
|
---|
[1] | 451 | /** Bit 20 - NX - AMD No-Execute Page Protection. */
|
---|
[5605] | 452 | #define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
|
---|
[1] | 453 | /** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
|
---|
[5605] | 454 | #define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
|
---|
[1] | 455 | /** Bit 23 - MMX - Intel MMX Technology. */
|
---|
[5605] | 456 | #define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
|
---|
[1] | 457 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
|
---|
[5605] | 458 | #define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
|
---|
[4425] | 459 | /** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
|
---|
[5605] | 460 | #define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
|
---|
[4425] | 461 | /** Bit 26 - PAGE1GB - AMD 1GB large page support. */
|
---|
[5605] | 462 | #define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
|
---|
[4425] | 463 | /** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
|
---|
[5605] | 464 | #define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
|
---|
[4425] | 465 | /** Bit 29 - LM - AMD Long Mode. */
|
---|
[5605] | 466 | #define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
|
---|
[4425] | 467 | /** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
|
---|
[5605] | 468 | #define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
|
---|
[4425] | 469 | /** Bit 31 - 3DNOW - AMD 3DNow. */
|
---|
[5605] | 470 | #define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
|
---|
[1] | 471 |
|
---|
[4425] | 472 | /** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
|
---|
[5605] | 473 | #define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
|
---|
[4425] | 474 | /** Bit 1 - CMPL - Core multi-processing legacy mode. */
|
---|
[5605] | 475 | #define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
|
---|
[1] | 476 | /** Bit 2 - SVM - AMD VM extensions. */
|
---|
[5605] | 477 | #define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
|
---|
[4425] | 478 | /** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
|
---|
[5605] | 479 | #define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
|
---|
[4425] | 480 | /** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
|
---|
[5605] | 481 | #define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
|
---|
[4425] | 482 | /** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
|
---|
[5605] | 483 | #define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
|
---|
[4425] | 484 | /** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
|
---|
[5605] | 485 | #define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
|
---|
[4425] | 486 | /** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
|
---|
[5605] | 487 | #define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
|
---|
[4425] | 488 | /** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
|
---|
[5605] | 489 | #define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
|
---|
[4425] | 490 | /** Bit 9 - OSVW - AMD OS visible workaround. */
|
---|
[5605] | 491 | #define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
|
---|
[4425] | 492 | /** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
|
---|
[5605] | 493 | #define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
|
---|
[4425] | 494 | /** Bit 13 - WDT - AMD Watchdog timer support. */
|
---|
[5605] | 495 | #define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
|
---|
[1] | 496 |
|
---|
| 497 | /** @} */
|
---|
| 498 |
|
---|
| 499 |
|
---|
| 500 | /** @name CR0
|
---|
| 501 | * @{ */
|
---|
| 502 | /** Bit 0 - PE - Protection Enabled */
|
---|
[5605] | 503 | #define X86_CR0_PE RT_BIT(0)
|
---|
| 504 | #define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
|
---|
[1] | 505 | /** Bit 1 - MP - Monitor Coprocessor */
|
---|
[5605] | 506 | #define X86_CR0_MP RT_BIT(1)
|
---|
| 507 | #define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
|
---|
[1] | 508 | /** Bit 2 - EM - Emulation. */
|
---|
[5605] | 509 | #define X86_CR0_EM RT_BIT(2)
|
---|
| 510 | #define X86_CR0_EMULATE_FPU RT_BIT(2)
|
---|
[1] | 511 | /** Bit 3 - TS - Task Switch. */
|
---|
[5605] | 512 | #define X86_CR0_TS RT_BIT(3)
|
---|
| 513 | #define X86_CR0_TASK_SWITCH RT_BIT(3)
|
---|
[1] | 514 | /** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
|
---|
[5605] | 515 | #define X86_CR0_ET RT_BIT(4)
|
---|
| 516 | #define X86_CR0_EXTENSION_TYPE RT_BIT(4)
|
---|
[1] | 517 | /** Bit 5 - NE - Numeric error. */
|
---|
[5605] | 518 | #define X86_CR0_NE RT_BIT(5)
|
---|
| 519 | #define X86_CR0_NUMERIC_ERROR RT_BIT(5)
|
---|
[1] | 520 | /** Bit 16 - WP - Write Protect. */
|
---|
[5605] | 521 | #define X86_CR0_WP RT_BIT(16)
|
---|
| 522 | #define X86_CR0_WRITE_PROTECT RT_BIT(16)
|
---|
[1] | 523 | /** Bit 18 - AM - Alignment Mask. */
|
---|
[5605] | 524 | #define X86_CR0_AM RT_BIT(18)
|
---|
| 525 | #define X86_CR0_ALIGMENT_MASK RT_BIT(18)
|
---|
[1] | 526 | /** Bit 29 - NW - Not Write-though. */
|
---|
[5605] | 527 | #define X86_CR0_NW RT_BIT(29)
|
---|
| 528 | #define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
|
---|
[1] | 529 | /** Bit 30 - WP - Cache Disable. */
|
---|
[5605] | 530 | #define X86_CR0_CD RT_BIT(30)
|
---|
| 531 | #define X86_CR0_CACHE_DISABLE RT_BIT(30)
|
---|
[1] | 532 | /** Bit 31 - PG - Paging. */
|
---|
[5605] | 533 | #define X86_CR0_PG RT_BIT(31)
|
---|
| 534 | #define X86_CR0_PAGING RT_BIT(31)
|
---|
[1] | 535 | /** @} */
|
---|
| 536 |
|
---|
| 537 |
|
---|
| 538 | /** @name CR3
|
---|
| 539 | * @{ */
|
---|
| 540 | /** Bit 3 - PWT - Page-level Writes Transparent. */
|
---|
[5605] | 541 | #define X86_CR3_PWT RT_BIT(3)
|
---|
[1] | 542 | /** Bit 4 - PCD - Page-level Cache Disable. */
|
---|
[5605] | 543 | #define X86_CR3_PCD RT_BIT(4)
|
---|
[1] | 544 | /** Bits 12-31 - - Page directory page number. */
|
---|
| 545 | #define X86_CR3_PAGE_MASK (0xfffff000)
|
---|
| 546 | /** Bits 5-31 - - PAE Page directory page number. */
|
---|
| 547 | #define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
|
---|
| 548 | /** @} */
|
---|
| 549 |
|
---|
| 550 |
|
---|
| 551 | /** @name CR4
|
---|
| 552 | * @{ */
|
---|
| 553 | /** Bit 0 - VME - Virtual-8086 Mode Extensions. */
|
---|
[5605] | 554 | #define X86_CR4_VME RT_BIT(0)
|
---|
[1] | 555 | /** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
|
---|
[5605] | 556 | #define X86_CR4_PVI RT_BIT(1)
|
---|
[1] | 557 | /** Bit 2 - TSD - Time Stamp Disable. */
|
---|
[5605] | 558 | #define X86_CR4_TSD RT_BIT(2)
|
---|
[1] | 559 | /** Bit 3 - DE - Debugging Extensions. */
|
---|
[5605] | 560 | #define X86_CR4_DE RT_BIT(3)
|
---|
[1] | 561 | /** Bit 4 - PSE - Page Size Extension. */
|
---|
[5605] | 562 | #define X86_CR4_PSE RT_BIT(4)
|
---|
[1] | 563 | /** Bit 5 - PAE - Physical Address Extension. */
|
---|
[5605] | 564 | #define X86_CR4_PAE RT_BIT(5)
|
---|
[1] | 565 | /** Bit 6 - MCE - Machine-Check Enable. */
|
---|
[5605] | 566 | #define X86_CR4_MCE RT_BIT(6)
|
---|
[1] | 567 | /** Bit 7 - PGE - Page Global Enable. */
|
---|
[5605] | 568 | #define X86_CR4_PGE RT_BIT(7)
|
---|
[1] | 569 | /** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
|
---|
[5605] | 570 | #define X86_CR4_PCE RT_BIT(8)
|
---|
[1] | 571 | /** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
|
---|
[5605] | 572 | #define X86_CR4_OSFSXR RT_BIT(9)
|
---|
[1] | 573 | /** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
|
---|
[5605] | 574 | #define X86_CR4_OSXMMEEXCPT RT_BIT(10)
|
---|
[1] | 575 | /** Bit 13 - VMXE - VMX mode is enabled. */
|
---|
[5605] | 576 | #define X86_CR4_VMXE RT_BIT(13)
|
---|
[1] | 577 | /** @} */
|
---|
| 578 |
|
---|
| 579 |
|
---|
| 580 | /** @name DR6
|
---|
| 581 | * @{ */
|
---|
| 582 | /** Bit 0 - B0 - Breakpoint 0 condition detected. */
|
---|
[5605] | 583 | #define X86_DR6_B0 RT_BIT(0)
|
---|
[1] | 584 | /** Bit 1 - B1 - Breakpoint 1 condition detected. */
|
---|
[5605] | 585 | #define X86_DR6_B1 RT_BIT(1)
|
---|
[1] | 586 | /** Bit 2 - B2 - Breakpoint 2 condition detected. */
|
---|
[5605] | 587 | #define X86_DR6_B2 RT_BIT(2)
|
---|
[1] | 588 | /** Bit 3 - B3 - Breakpoint 3 condition detected. */
|
---|
[5605] | 589 | #define X86_DR6_B3 RT_BIT(3)
|
---|
[1] | 590 | /** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
|
---|
[5605] | 591 | #define X86_DR6_BD RT_BIT(13)
|
---|
[1] | 592 | /** Bit 14 - BS - Single step */
|
---|
[5605] | 593 | #define X86_DR6_BS RT_BIT(14)
|
---|
[1] | 594 | /** Bit 15 - BT - Task switch. (TSS T bit.) */
|
---|
[5605] | 595 | #define X86_DR6_BT RT_BIT(15)
|
---|
[1] | 596 | /** @} */
|
---|
| 597 |
|
---|
| 598 |
|
---|
| 599 | /** @name DR7
|
---|
| 600 | * @{ */
|
---|
| 601 | /** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
|
---|
[5605] | 602 | #define X86_DR7_L0 RT_BIT(0)
|
---|
[1] | 603 | /** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[5605] | 604 | #define X86_DR7_G0 RT_BIT(1)
|
---|
[1] | 605 | /** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
|
---|
[5605] | 606 | #define X86_DR7_L1 RT_BIT(2)
|
---|
[1] | 607 | /** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[5605] | 608 | #define X86_DR7_G1 RT_BIT(3)
|
---|
[1] | 609 | /** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
|
---|
[5605] | 610 | #define X86_DR7_L2 RT_BIT(4)
|
---|
[1] | 611 | /** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[5605] | 612 | #define X86_DR7_G2 RT_BIT(5)
|
---|
[1] | 613 | /** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
|
---|
[5605] | 614 | #define X86_DR7_L3 RT_BIT(6)
|
---|
[1] | 615 | /** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[5605] | 616 | #define X86_DR7_G3 RT_BIT(7)
|
---|
[1] | 617 | /** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
|
---|
[5605] | 618 | #define X86_DR7_LE RT_BIT(8)
|
---|
[1] | 619 | /** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
|
---|
[5605] | 620 | #define X86_DR7_GE RT_BIT(9)
|
---|
[1] | 621 |
|
---|
| 622 | /** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
|
---|
| 623 | * any DR register is accessed. */
|
---|
[5605] | 624 | #define X86_DR7_GD RT_BIT(13)
|
---|
[1] | 625 | /** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 626 | #define X86_DR7_RW0_MASK (3 << 16)
|
---|
| 627 | /** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 628 | #define X86_DR7_LEN0_MASK (3 << 18)
|
---|
| 629 | /** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 630 | #define X86_DR7_RW1_MASK (3 << 20)
|
---|
| 631 | /** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 632 | #define X86_DR7_LEN1_MASK (3 << 22)
|
---|
| 633 | /** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 634 | #define X86_DR7_RW2_MASK (3 << 24)
|
---|
| 635 | /** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 636 | #define X86_DR7_LEN2_MASK (3 << 26)
|
---|
| 637 | /** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 638 | #define X86_DR7_RW3_MASK (3 << 28)
|
---|
| 639 | /** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 640 | #define X86_DR7_LEN3_MASK (3 << 30)
|
---|
| 641 |
|
---|
| 642 | /** Bits which must be 1s. */
|
---|
[5605] | 643 | #define X86_DR7_MB1_MASK (RT_BIT(10))
|
---|
[1] | 644 |
|
---|
| 645 | /** Calcs the L bit of Nth breakpoint.
|
---|
| 646 | * @param iBp The breakpoint number [0..3].
|
---|
| 647 | */
|
---|
| 648 | #define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
|
---|
| 649 |
|
---|
| 650 | /** Calcs the G bit of Nth breakpoint.
|
---|
| 651 | * @param iBp The breakpoint number [0..3].
|
---|
| 652 | */
|
---|
| 653 | #define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
|
---|
| 654 |
|
---|
| 655 | /** @name Read/Write values.
|
---|
| 656 | * @{ */
|
---|
| 657 | /** Break on instruction fetch only. */
|
---|
| 658 | #define X86_DR7_RW_EO 0
|
---|
| 659 | /** Break on write only. */
|
---|
| 660 | #define X86_DR7_RW_WO 1
|
---|
| 661 | /** Break on I/O read/write. This is only defined if CR4.DE is set. */
|
---|
| 662 | #define X86_DR7_RW_IO 2
|
---|
| 663 | /** Break on read or write (but not instruction fetches). */
|
---|
| 664 | #define X86_DR7_RW_RW 3
|
---|
| 665 | /** @} */
|
---|
| 666 |
|
---|
| 667 | /** Shifts a X86_DR7_RW_* value to its right place.
|
---|
| 668 | * @param iBp The breakpoint number [0..3].
|
---|
| 669 | * @param fRw One of the X86_DR7_RW_* value.
|
---|
| 670 | */
|
---|
| 671 | #define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
|
---|
| 672 |
|
---|
| 673 | /** @name Length values.
|
---|
| 674 | * @{ */
|
---|
| 675 | #define X86_DR7_LEN_BYTE 0
|
---|
| 676 | #define X86_DR7_LEN_WORD 1
|
---|
| 677 | #define X86_DR7_LEN_QWORD 2 /**< AMD64 long mode only. */
|
---|
| 678 | #define X86_DR7_LEN_DWORD 3
|
---|
| 679 | /** @} */
|
---|
| 680 |
|
---|
| 681 | /** Shifts a X86_DR7_LEN_* value to its right place.
|
---|
| 682 | * @param iBp The breakpoint number [0..3].
|
---|
| 683 | * @param cb One of the X86_DR7_LEN_* values.
|
---|
| 684 | */
|
---|
| 685 | #define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
|
---|
| 686 |
|
---|
| 687 | /** Mask used to check if any breakpoints are enabled. */
|
---|
[5605] | 688 | #define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
|
---|
[1] | 689 |
|
---|
| 690 | /** @} */
|
---|
| 691 |
|
---|
| 692 |
|
---|
| 693 | /** @name Machine Specific Registers
|
---|
| 694 | * @{
|
---|
| 695 | */
|
---|
| 696 | /** CPU Feature control. */
|
---|
| 697 | #define MSR_IA32_FEATURE_CONTROL 0x3A
|
---|
[5605] | 698 | #define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
|
---|
| 699 | #define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
|
---|
[1] | 700 |
|
---|
| 701 |
|
---|
| 702 | #ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
|
---|
| 703 | /** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
|
---|
| 704 | * R0 SS == CS + 8
|
---|
| 705 | * R3 CS == CS + 16
|
---|
| 706 | * R3 SS == CS + 24
|
---|
| 707 | */
|
---|
| 708 | #define MSR_IA32_SYSENTER_CS 0x174
|
---|
| 709 | /** SYSENTER_ESP - the R0 ESP. */
|
---|
| 710 | #define MSR_IA32_SYSENTER_ESP 0x175
|
---|
| 711 | /** SYSENTER_EIP - the R0 EIP. */
|
---|
| 712 | #define MSR_IA32_SYSENTER_EIP 0x176
|
---|
| 713 | #endif
|
---|
| 714 |
|
---|
[7695] | 715 | /* Page Attribute Table. */
|
---|
| 716 | #define IA32_CR_PAT 0x277
|
---|
| 717 |
|
---|
[1] | 718 | /** Basic VMX information. */
|
---|
| 719 | #define MSR_IA32_VMX_BASIC_INFO 0x480
|
---|
| 720 | /** Allowed settings for pin-based VM execution controls */
|
---|
| 721 | #define MSR_IA32_VMX_PINBASED_CTLS 0x481
|
---|
| 722 | /** Allowed settings for proc-based VM execution controls */
|
---|
| 723 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
|
---|
| 724 | /** Allowed settings for the VMX exit controls. */
|
---|
| 725 | #define MSR_IA32_VMX_EXIT_CTLS 0x483
|
---|
| 726 | /** Allowed settings for the VMX entry controls. */
|
---|
| 727 | #define MSR_IA32_VMX_ENTRY_CTLS 0x484
|
---|
| 728 | /** Misc VMX info. */
|
---|
| 729 | #define MSR_IA32_VMX_MISC 0x485
|
---|
| 730 | /** Fixed cleared bits in CR0. */
|
---|
| 731 | #define MSR_IA32_VMX_CR0_FIXED0 0x486
|
---|
| 732 | /** Fixed set bits in CR0. */
|
---|
| 733 | #define MSR_IA32_VMX_CR0_FIXED1 0x487
|
---|
| 734 | /** Fixed cleared bits in CR4. */
|
---|
| 735 | #define MSR_IA32_VMX_CR4_FIXED0 0x488
|
---|
| 736 | /** Fixed set bits in CR4. */
|
---|
| 737 | #define MSR_IA32_VMX_CR4_FIXED1 0x489
|
---|
| 738 | /** Information for enumerating fields in the VMCS. */
|
---|
| 739 | #define MSR_IA32_VMX_VMCS_ENUM 0x48A
|
---|
| 740 |
|
---|
| 741 |
|
---|
| 742 | /** K6 EFER - Extended Feature Enable Register. */
|
---|
| 743 | #define MSR_K6_EFER 0xc0000080
|
---|
| 744 | /** @todo document EFER */
|
---|
| 745 | /** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
|
---|
[5605] | 746 | #define MSR_K6_EFER_SCE RT_BIT(0)
|
---|
[1] | 747 | /** Bit 8 - LME - Long mode enabled. (R/W) */
|
---|
[5605] | 748 | #define MSR_K6_EFER_LME RT_BIT(8)
|
---|
[1] | 749 | /** Bit 10 - LMA - Long mode active. (R) */
|
---|
[5605] | 750 | #define MSR_K6_EFER_LMA RT_BIT(10)
|
---|
[1] | 751 | /** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
|
---|
[5605] | 752 | #define MSR_K6_EFER_NXE RT_BIT(11)
|
---|
[1] | 753 | /** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
|
---|
[5605] | 754 | #define MSR_K6_EFER_SVME RT_BIT(12)
|
---|
[1] | 755 | /** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
|
---|
[5605] | 756 | #define MSR_K6_EFER_LMSLE RT_BIT(13)
|
---|
[1] | 757 | /** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
|
---|
[5605] | 758 | #define MSR_K6_EFER_FFXSR RT_BIT(14)
|
---|
[1] | 759 | /** K6 STAR - SYSCALL/RET targets. */
|
---|
| 760 | #define MSR_K6_STAR 0xc0000081
|
---|
| 761 | /** Shift value for getting the SYSRET CS and SS value. */
|
---|
| 762 | #define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
|
---|
| 763 | /** Shift value for getting the SYSCALL CS and SS value. */
|
---|
| 764 | #define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
|
---|
| 765 | /** Selector mask for use after shifting. */
|
---|
| 766 | #define MSR_K6_STAR_SEL_MASK 0xffff
|
---|
| 767 | /** The mask which give the SYSCALL EIP. */
|
---|
| 768 | #define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
|
---|
| 769 | /** K6 WHCR - Write Handling Control Register. */
|
---|
| 770 | #define MSR_K6_WHCR 0xc0000082
|
---|
| 771 | /** K6 UWCCR - UC/WC Cacheability Control Register. */
|
---|
| 772 | #define MSR_K6_UWCCR 0xc0000085
|
---|
| 773 | /** K6 PSOR - Processor State Observability Register. */
|
---|
| 774 | #define MSR_K6_PSOR 0xc0000087
|
---|
| 775 | /** K6 PFIR - Page Flush/Invalidate Register. */
|
---|
| 776 | #define MSR_K6_PFIR 0xc0000088
|
---|
| 777 |
|
---|
| 778 | #define MSR_K7_EVNTSEL0 0xc0010000
|
---|
| 779 | #define MSR_K7_EVNTSEL1 0xc0010001
|
---|
| 780 | #define MSR_K7_EVNTSEL2 0xc0010002
|
---|
| 781 | #define MSR_K7_EVNTSEL3 0xc0010003
|
---|
| 782 | #define MSR_K7_PERFCTR0 0xc0010004
|
---|
| 783 | #define MSR_K7_PERFCTR1 0xc0010005
|
---|
| 784 | #define MSR_K7_PERFCTR2 0xc0010006
|
---|
| 785 | #define MSR_K7_PERFCTR3 0xc0010007
|
---|
| 786 |
|
---|
| 787 | /** K8 LSTAR - Long mode SYSCALL target (RIP). */
|
---|
| 788 | #define MSR_K8_LSTAR 0xc0000082
|
---|
| 789 | /** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
|
---|
| 790 | #define MSR_K8_CSTAR 0xc0000083
|
---|
| 791 | /** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
|
---|
| 792 | #define MSR_K8_SF_MASK 0xc0000084
|
---|
| 793 | /** K8 FS.base - The 64-bit base FS register. */
|
---|
| 794 | #define MSR_K8_FS_BASE 0xc0000100
|
---|
| 795 | /** K8 GS.base - The 64-bit base GS register. */
|
---|
| 796 | #define MSR_K8_GS_BASE 0xc0000101
|
---|
| 797 | /** K8 KernelGSbase - Used with SWAPGS. */
|
---|
| 798 | #define MSR_K8_KERNEL_GS_BASE 0xc0000102
|
---|
| 799 | #define MSR_K8_TSC_AUX 0xc0000103
|
---|
| 800 | #define MSR_K8_SYSCFG 0xc0010010
|
---|
| 801 | #define MSR_K8_HWCR 0xc0010015
|
---|
| 802 | #define MSR_K8_IORRBASE0 0xc0010016
|
---|
| 803 | #define MSR_K8_IORRMASK0 0xc0010017
|
---|
| 804 | #define MSR_K8_IORRBASE1 0xc0010018
|
---|
| 805 | #define MSR_K8_IORRMASK1 0xc0010019
|
---|
| 806 | #define MSR_K8_TOP_MEM1 0xc001001a
|
---|
| 807 | #define MSR_K8_TOP_MEM2 0xc001001d
|
---|
| 808 | #define MSR_K8_VM_CR 0xc0010114
|
---|
[5605] | 809 | #define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
|
---|
[3748] | 810 |
|
---|
[1] | 811 | #define MSR_K8_IGNNE 0xc0010115
|
---|
| 812 | #define MSR_K8_SMM_CTL 0xc0010116
|
---|
| 813 | /** SVM - VM_HSAVE_PA - Physical address for saving and restoring
|
---|
| 814 | * host state during world switch.
|
---|
| 815 | */
|
---|
| 816 | #define MSR_K8_VM_HSAVE_PA 0xc0010117
|
---|
| 817 |
|
---|
| 818 | /** @} */
|
---|
| 819 |
|
---|
| 820 |
|
---|
| 821 | /** @name Page Table / Directory / Directory Pointers / L4.
|
---|
| 822 | * @{
|
---|
| 823 | */
|
---|
| 824 |
|
---|
| 825 | /** Page table/directory entry as an unsigned integer. */
|
---|
| 826 | typedef uint32_t X86PGUINT;
|
---|
| 827 | /** Pointer to a page table/directory table entry as an unsigned integer. */
|
---|
| 828 | typedef X86PGUINT *PX86PGUINT;
|
---|
| 829 |
|
---|
| 830 | /** Number of entries in a 32-bit PT/PD. */
|
---|
| 831 | #define X86_PG_ENTRIES 1024
|
---|
| 832 |
|
---|
| 833 |
|
---|
[7705] | 834 | /** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
|
---|
[1] | 835 | typedef uint64_t X86PGPAEUINT;
|
---|
[7705] | 836 | /** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
|
---|
[1] | 837 | typedef X86PGPAEUINT *PX86PGPAEUINT;
|
---|
| 838 |
|
---|
[7705] | 839 | /** Number of entries in a PAE PT/PD. */
|
---|
[1] | 840 | #define X86_PG_PAE_ENTRIES 512
|
---|
[7705] | 841 | /** Number of entries in a PAE PDPT. */
|
---|
[7677] | 842 | #define X86_PG_PAE_PDPE_ENTRIES 4
|
---|
[1] | 843 |
|
---|
[7705] | 844 | /** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
|
---|
[7676] | 845 | #define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
|
---|
[7705] | 846 | /** Number of entries in an AMD64 PDPT.
|
---|
| 847 | * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
|
---|
| 848 | #define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
|
---|
[1] | 849 |
|
---|
| 850 | /** The size of a 4KB page. */
|
---|
| 851 | #define X86_PAGE_4K_SIZE _4K
|
---|
| 852 | /** The page shift of a 4KB page. */
|
---|
| 853 | #define X86_PAGE_4K_SHIFT 12
|
---|
| 854 | /** The 4KB page offset mask. */
|
---|
| 855 | #define X86_PAGE_4K_OFFSET_MASK 0xfff
|
---|
| 856 | /** The 4KB page base mask for virtual addresses. */
|
---|
| 857 | #define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
|
---|
| 858 | /** The 4KB page base mask for virtual addresses - 32bit version. */
|
---|
| 859 | #define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
|
---|
| 860 |
|
---|
| 861 | /** The size of a 2MB page. */
|
---|
| 862 | #define X86_PAGE_2M_SIZE _2M
|
---|
| 863 | /** The page shift of a 2MB page. */
|
---|
| 864 | #define X86_PAGE_2M_SHIFT 21
|
---|
| 865 | /** The 2MB page offset mask. */
|
---|
| 866 | #define X86_PAGE_2M_OFFSET_MASK 0x001fffff
|
---|
| 867 | /** The 2MB page base mask for virtual addresses. */
|
---|
| 868 | #define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
|
---|
| 869 | /** The 2MB page base mask for virtual addresses - 32bit version. */
|
---|
| 870 | #define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
|
---|
| 871 |
|
---|
| 872 | /** The size of a 4MB page. */
|
---|
| 873 | #define X86_PAGE_4M_SIZE _4M
|
---|
| 874 | /** The page shift of a 4MB page. */
|
---|
| 875 | #define X86_PAGE_4M_SHIFT 22
|
---|
| 876 | /** The 4MB page offset mask. */
|
---|
| 877 | #define X86_PAGE_4M_OFFSET_MASK 0x003fffff
|
---|
| 878 | /** The 4MB page base mask for virtual addresses. */
|
---|
| 879 | #define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
|
---|
| 880 | /** The 4MB page base mask for virtual addresses - 32bit version. */
|
---|
| 881 | #define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
|
---|
| 882 |
|
---|
| 883 |
|
---|
| 884 |
|
---|
| 885 | /** @name Page Table Entry
|
---|
| 886 | * @{
|
---|
| 887 | */
|
---|
| 888 | /** Bit 0 - P - Present bit. */
|
---|
[5605] | 889 | #define X86_PTE_P RT_BIT(0)
|
---|
[1] | 890 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[5605] | 891 | #define X86_PTE_RW RT_BIT(1)
|
---|
[1] | 892 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[5605] | 893 | #define X86_PTE_US RT_BIT(2)
|
---|
[1] | 894 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[5605] | 895 | #define X86_PTE_PWT RT_BIT(3)
|
---|
[1] | 896 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[5605] | 897 | #define X86_PTE_PCD RT_BIT(4)
|
---|
[1] | 898 | /** Bit 5 - A - Access bit. */
|
---|
[5605] | 899 | #define X86_PTE_A RT_BIT(5)
|
---|
[1] | 900 | /** Bit 6 - D - Dirty bit. */
|
---|
[5605] | 901 | #define X86_PTE_D RT_BIT(6)
|
---|
[1] | 902 | /** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
|
---|
[5605] | 903 | #define X86_PTE_PAT RT_BIT(7)
|
---|
[1] | 904 | /** Bit 8 - G - Global flag. */
|
---|
[5605] | 905 | #define X86_PTE_G RT_BIT(8)
|
---|
[1] | 906 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[5605] | 907 | #define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
|
---|
[1] | 908 | /** Bits 12-31 - - Physical Page number of the next level. */
|
---|
| 909 | #define X86_PTE_PG_MASK ( 0xfffff000 )
|
---|
| 910 |
|
---|
[7705] | 911 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
[1] | 912 | #if 1 /* we're using this internally and have to mask of the top 16-bit. */
|
---|
| 913 | #define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
|
---|
| 914 | #else
|
---|
| 915 | #define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
|
---|
| 916 | #endif
|
---|
| 917 | /** Bits 63 - NX - PAE - No execution flag. */
|
---|
[5605] | 918 | #define X86_PTE_PAE_NX RT_BIT_64(63)
|
---|
[1] | 919 |
|
---|
| 920 | /**
|
---|
| 921 | * Page table entry.
|
---|
| 922 | */
|
---|
| 923 | typedef struct X86PTEBITS
|
---|
| 924 | {
|
---|
| 925 | /** Flags whether(=1) or not the page is present. */
|
---|
| 926 | unsigned u1Present : 1;
|
---|
| 927 | /** Read(=0) / Write(=1) flag. */
|
---|
| 928 | unsigned u1Write : 1;
|
---|
| 929 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 930 | unsigned u1User : 1;
|
---|
| 931 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 932 | unsigned u1WriteThru : 1;
|
---|
| 933 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 934 | unsigned u1CacheDisable : 1;
|
---|
| 935 | /** Accessed flag.
|
---|
| 936 | * Indicates that the page have been read or written to. */
|
---|
| 937 | unsigned u1Accessed : 1;
|
---|
| 938 | /** Dirty flag.
|
---|
| 939 | * Indicates that the page have been written to. */
|
---|
| 940 | unsigned u1Dirty : 1;
|
---|
| 941 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 942 | unsigned u1PAT : 1;
|
---|
| 943 | /** Global flag. (Ignored in all but final level.) */
|
---|
| 944 | unsigned u1Global : 1;
|
---|
| 945 | /** Available for use to system software. */
|
---|
| 946 | unsigned u3Available : 3;
|
---|
| 947 | /** Physical Page number of the next level. */
|
---|
| 948 | unsigned u20PageNo : 20;
|
---|
| 949 | } X86PTEBITS;
|
---|
| 950 | /** Pointer to a page table entry. */
|
---|
| 951 | typedef X86PTEBITS *PX86PTEBITS;
|
---|
| 952 | /** Pointer to a const page table entry. */
|
---|
| 953 | typedef const X86PTEBITS *PCX86PTEBITS;
|
---|
| 954 |
|
---|
| 955 | /**
|
---|
| 956 | * Page table entry.
|
---|
| 957 | */
|
---|
| 958 | typedef union X86PTE
|
---|
| 959 | {
|
---|
| 960 | /** Bit field view. */
|
---|
| 961 | X86PTEBITS n;
|
---|
| 962 | /** Unsigned integer view */
|
---|
| 963 | X86PGUINT u;
|
---|
| 964 | /** 32-bit view. */
|
---|
| 965 | uint32_t au32[1];
|
---|
| 966 | /** 16-bit view. */
|
---|
| 967 | uint16_t au16[2];
|
---|
| 968 | /** 8-bit view. */
|
---|
| 969 | uint8_t au8[4];
|
---|
| 970 | } X86PTE;
|
---|
| 971 | /** Pointer to a page table entry. */
|
---|
| 972 | typedef X86PTE *PX86PTE;
|
---|
| 973 | /** Pointer to a const page table entry. */
|
---|
| 974 | typedef const X86PTE *PCX86PTE;
|
---|
| 975 |
|
---|
| 976 |
|
---|
| 977 | /**
|
---|
| 978 | * PAE page table entry.
|
---|
| 979 | */
|
---|
| 980 | typedef struct X86PTEPAEBITS
|
---|
| 981 | {
|
---|
| 982 | /** Flags whether(=1) or not the page is present. */
|
---|
| 983 | uint32_t u1Present : 1;
|
---|
| 984 | /** Read(=0) / Write(=1) flag. */
|
---|
| 985 | uint32_t u1Write : 1;
|
---|
| 986 | /** User(=1) / Supervisor(=0) flag. */
|
---|
| 987 | uint32_t u1User : 1;
|
---|
| 988 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 989 | uint32_t u1WriteThru : 1;
|
---|
| 990 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 991 | uint32_t u1CacheDisable : 1;
|
---|
| 992 | /** Accessed flag.
|
---|
| 993 | * Indicates that the page have been read or written to. */
|
---|
| 994 | uint32_t u1Accessed : 1;
|
---|
| 995 | /** Dirty flag.
|
---|
| 996 | * Indicates that the page have been written to. */
|
---|
| 997 | uint32_t u1Dirty : 1;
|
---|
| 998 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 999 | uint32_t u1PAT : 1;
|
---|
| 1000 | /** Global flag. (Ignored in all but final level.) */
|
---|
| 1001 | uint32_t u1Global : 1;
|
---|
| 1002 | /** Available for use to system software. */
|
---|
| 1003 | uint32_t u3Available : 3;
|
---|
| 1004 | /** Physical Page number of the next level - Low Part. Don't use this. */
|
---|
| 1005 | uint32_t u20PageNoLow : 20;
|
---|
| 1006 | /** Physical Page number of the next level - High Part. Don't use this. */
|
---|
| 1007 | uint32_t u20PageNoHigh : 20;
|
---|
| 1008 | /** MBZ bits */
|
---|
| 1009 | uint32_t u11Reserved : 11;
|
---|
| 1010 | /** No Execute flag. */
|
---|
| 1011 | uint32_t u1NoExecute : 1;
|
---|
| 1012 | } X86PTEPAEBITS;
|
---|
| 1013 | /** Pointer to a page table entry. */
|
---|
| 1014 | typedef X86PTEPAEBITS *PX86PTEPAEBITS;
|
---|
| 1015 | /** Pointer to a page table entry. */
|
---|
| 1016 | typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
|
---|
| 1017 |
|
---|
| 1018 | /**
|
---|
| 1019 | * PAE Page table entry.
|
---|
| 1020 | */
|
---|
| 1021 | typedef union X86PTEPAE
|
---|
| 1022 | {
|
---|
| 1023 | /** Bit field view. */
|
---|
| 1024 | X86PTEPAEBITS n;
|
---|
| 1025 | /** Unsigned integer view */
|
---|
| 1026 | X86PGPAEUINT u;
|
---|
| 1027 | /** 32-bit view. */
|
---|
| 1028 | uint32_t au32[2];
|
---|
| 1029 | /** 16-bit view. */
|
---|
| 1030 | uint16_t au16[4];
|
---|
| 1031 | /** 8-bit view. */
|
---|
| 1032 | uint8_t au8[8];
|
---|
| 1033 | } X86PTEPAE;
|
---|
| 1034 | /** Pointer to a PAE page table entry. */
|
---|
| 1035 | typedef X86PTEPAE *PX86PTEPAE;
|
---|
| 1036 | /** Pointer to a const PAE page table entry. */
|
---|
| 1037 | typedef const X86PTEPAE *PCX86PTEPAE;
|
---|
| 1038 | /** @} */
|
---|
| 1039 |
|
---|
| 1040 | /**
|
---|
| 1041 | * Page table.
|
---|
| 1042 | */
|
---|
| 1043 | typedef struct X86PT
|
---|
| 1044 | {
|
---|
| 1045 | /** PTE Array. */
|
---|
| 1046 | X86PTE a[X86_PG_ENTRIES];
|
---|
| 1047 | } X86PT;
|
---|
| 1048 | /** Pointer to a page table. */
|
---|
| 1049 | typedef X86PT *PX86PT;
|
---|
| 1050 | /** Pointer to a const page table. */
|
---|
| 1051 | typedef const X86PT *PCX86PT;
|
---|
| 1052 |
|
---|
| 1053 | /** The page shift to get the PT index. */
|
---|
| 1054 | #define X86_PT_SHIFT 12
|
---|
| 1055 | /** The PT index mask (apply to a shifted page address). */
|
---|
| 1056 | #define X86_PT_MASK 0x3ff
|
---|
| 1057 |
|
---|
| 1058 |
|
---|
| 1059 | /**
|
---|
| 1060 | * Page directory.
|
---|
| 1061 | */
|
---|
| 1062 | typedef struct X86PTPAE
|
---|
| 1063 | {
|
---|
| 1064 | /** PTE Array. */
|
---|
| 1065 | X86PTEPAE a[X86_PG_PAE_ENTRIES];
|
---|
| 1066 | } X86PTPAE;
|
---|
| 1067 | /** Pointer to a page table. */
|
---|
| 1068 | typedef X86PTPAE *PX86PTPAE;
|
---|
| 1069 | /** Pointer to a const page table. */
|
---|
| 1070 | typedef const X86PTPAE *PCX86PTPAE;
|
---|
| 1071 |
|
---|
| 1072 | /** The page shift to get the PA PTE index. */
|
---|
| 1073 | #define X86_PT_PAE_SHIFT 12
|
---|
| 1074 | /** The PAE PT index mask (apply to a shifted page address). */
|
---|
| 1075 | #define X86_PT_PAE_MASK 0x1ff
|
---|
| 1076 |
|
---|
| 1077 |
|
---|
| 1078 | /** @name 4KB Page Directory Entry
|
---|
| 1079 | * @{
|
---|
| 1080 | */
|
---|
| 1081 | /** Bit 0 - P - Present bit. */
|
---|
[5605] | 1082 | #define X86_PDE_P RT_BIT(0)
|
---|
[1] | 1083 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[5605] | 1084 | #define X86_PDE_RW RT_BIT(1)
|
---|
[1] | 1085 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[5605] | 1086 | #define X86_PDE_US RT_BIT(2)
|
---|
[1] | 1087 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[5605] | 1088 | #define X86_PDE_PWT RT_BIT(3)
|
---|
[1] | 1089 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[5605] | 1090 | #define X86_PDE_PCD RT_BIT(4)
|
---|
[1] | 1091 | /** Bit 5 - A - Access bit. */
|
---|
[5605] | 1092 | #define X86_PDE_A RT_BIT(5)
|
---|
[1] | 1093 | /** Bit 7 - PS - Page size attribute.
|
---|
| 1094 | * Clear mean 4KB pages, set means large pages (2/4MB). */
|
---|
[5605] | 1095 | #define X86_PDE_PS RT_BIT(7)
|
---|
[1] | 1096 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[5605] | 1097 | #define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
|
---|
[1] | 1098 | /** Bits 12-31 - - Physical Page number of the next level. */
|
---|
| 1099 | #define X86_PDE_PG_MASK ( 0xfffff000 )
|
---|
| 1100 |
|
---|
| 1101 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
| 1102 | #if 1 /* we're using this internally and have to mask of the top 16-bit. */
|
---|
| 1103 | #define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
|
---|
| 1104 | #else
|
---|
| 1105 | #define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
|
---|
| 1106 | #endif
|
---|
| 1107 | /** Bits 63 - NX - PAE - No execution flag. */
|
---|
[5605] | 1108 | #define X86_PDE_PAE_NX RT_BIT_64(63)
|
---|
[1] | 1109 |
|
---|
| 1110 | /**
|
---|
| 1111 | * Page directory entry.
|
---|
| 1112 | */
|
---|
| 1113 | typedef struct X86PDEBITS
|
---|
| 1114 | {
|
---|
| 1115 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1116 | unsigned u1Present : 1;
|
---|
| 1117 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1118 | unsigned u1Write : 1;
|
---|
| 1119 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 1120 | unsigned u1User : 1;
|
---|
| 1121 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1122 | unsigned u1WriteThru : 1;
|
---|
| 1123 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1124 | unsigned u1CacheDisable : 1;
|
---|
| 1125 | /** Accessed flag.
|
---|
| 1126 | * Indicates that the page have been read or written to. */
|
---|
| 1127 | unsigned u1Accessed : 1;
|
---|
| 1128 | /** Reserved / Ignored (dirty bit). */
|
---|
| 1129 | unsigned u1Reserved0 : 1;
|
---|
| 1130 | /** Size bit if PSE is enabled - in any event it's 0. */
|
---|
| 1131 | unsigned u1Size : 1;
|
---|
| 1132 | /** Reserved / Ignored (global bit). */
|
---|
| 1133 | unsigned u1Reserved1 : 1;
|
---|
| 1134 | /** Available for use to system software. */
|
---|
| 1135 | unsigned u3Available : 3;
|
---|
| 1136 | /** Physical Page number of the next level. */
|
---|
| 1137 | unsigned u20PageNo : 20;
|
---|
| 1138 | } X86PDEBITS;
|
---|
| 1139 | /** Pointer to a page directory entry. */
|
---|
| 1140 | typedef X86PDEBITS *PX86PDEBITS;
|
---|
| 1141 | /** Pointer to a const page directory entry. */
|
---|
| 1142 | typedef const X86PDEBITS *PCX86PDEBITS;
|
---|
| 1143 |
|
---|
| 1144 |
|
---|
| 1145 | /**
|
---|
| 1146 | * PAE page directory entry.
|
---|
| 1147 | */
|
---|
| 1148 | typedef struct X86PDEPAEBITS
|
---|
| 1149 | {
|
---|
| 1150 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1151 | uint32_t u1Present : 1;
|
---|
| 1152 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1153 | uint32_t u1Write : 1;
|
---|
| 1154 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 1155 | uint32_t u1User : 1;
|
---|
| 1156 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1157 | uint32_t u1WriteThru : 1;
|
---|
| 1158 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1159 | uint32_t u1CacheDisable : 1;
|
---|
| 1160 | /** Accessed flag.
|
---|
| 1161 | * Indicates that the page have been read or written to. */
|
---|
| 1162 | uint32_t u1Accessed : 1;
|
---|
| 1163 | /** Reserved / Ignored (dirty bit). */
|
---|
| 1164 | uint32_t u1Reserved0 : 1;
|
---|
| 1165 | /** Size bit if PSE is enabled - in any event it's 0. */
|
---|
| 1166 | uint32_t u1Size : 1;
|
---|
| 1167 | /** Reserved / Ignored (global bit). / */
|
---|
| 1168 | uint32_t u1Reserved1 : 1;
|
---|
| 1169 | /** Available for use to system software. */
|
---|
| 1170 | uint32_t u3Available : 3;
|
---|
| 1171 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 1172 | uint32_t u20PageNoLow : 20;
|
---|
| 1173 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 1174 | uint32_t u20PageNoHigh : 20;
|
---|
| 1175 | /** MBZ bits */
|
---|
| 1176 | uint32_t u11Reserved : 11;
|
---|
| 1177 | /** No Execute flag. */
|
---|
| 1178 | uint32_t u1NoExecute : 1;
|
---|
| 1179 | } X86PDEPAEBITS;
|
---|
| 1180 | /** Pointer to a page directory entry. */
|
---|
| 1181 | typedef X86PDEPAEBITS *PX86PDEPAEBITS;
|
---|
| 1182 | /** Pointer to a const page directory entry. */
|
---|
| 1183 | typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
|
---|
| 1184 |
|
---|
| 1185 | /** @} */
|
---|
| 1186 |
|
---|
| 1187 |
|
---|
| 1188 | /** @name 2/4MB Page Directory Entry
|
---|
| 1189 | * @{
|
---|
| 1190 | */
|
---|
| 1191 | /** Bit 0 - P - Present bit. */
|
---|
[5605] | 1192 | #define X86_PDE4M_P RT_BIT(0)
|
---|
[1] | 1193 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[5605] | 1194 | #define X86_PDE4M_RW RT_BIT(1)
|
---|
[1] | 1195 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[5605] | 1196 | #define X86_PDE4M_US RT_BIT(2)
|
---|
[1] | 1197 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[5605] | 1198 | #define X86_PDE4M_PWT RT_BIT(3)
|
---|
[1] | 1199 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[5605] | 1200 | #define X86_PDE4M_PCD RT_BIT(4)
|
---|
[1] | 1201 | /** Bit 5 - A - Access bit. */
|
---|
[5605] | 1202 | #define X86_PDE4M_A RT_BIT(5)
|
---|
[1] | 1203 | /** Bit 6 - D - Dirty bit. */
|
---|
[5605] | 1204 | #define X86_PDE4M_D RT_BIT(6)
|
---|
[1] | 1205 | /** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
|
---|
[5605] | 1206 | #define X86_PDE4M_PS RT_BIT(7)
|
---|
[1] | 1207 | /** Bit 8 - G - Global flag. */
|
---|
[5605] | 1208 | #define X86_PDE4M_G RT_BIT(8)
|
---|
[1] | 1209 | /** Bits 9-11 - AVL - Available for use to system software. */
|
---|
[5605] | 1210 | #define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
|
---|
[1] | 1211 | /** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
|
---|
[5605] | 1212 | #define X86_PDE4M_PAT RT_BIT(12)
|
---|
[1] | 1213 | /** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
|
---|
| 1214 | #define X86_PDE4M_PAT_SHIFT (12 - 7)
|
---|
| 1215 | /** Bits 22-31 - - Physical Page number. */
|
---|
| 1216 | #define X86_PDE4M_PG_MASK ( 0xffc00000 )
|
---|
| 1217 | /** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
|
---|
| 1218 | #define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
|
---|
| 1219 | /** The number of bits to the high part of the page number. */
|
---|
| 1220 | #define X86_PDE4M_PG_HIGH_SHIFT 19
|
---|
| 1221 |
|
---|
[7705] | 1222 | /** Bits 21-51 - - PAE & AMD64 - Physical Page number.
|
---|
| 1223 | * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
|
---|
[7666] | 1224 | #define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
|
---|
| 1225 | /** Bits 63 - NX - PAE & AMD64 - No execution flag. */
|
---|
| 1226 | #define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
|
---|
[1] | 1227 |
|
---|
| 1228 | /**
|
---|
| 1229 | * 4MB page directory entry.
|
---|
| 1230 | */
|
---|
| 1231 | typedef struct X86PDE4MBITS
|
---|
| 1232 | {
|
---|
| 1233 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1234 | unsigned u1Present : 1;
|
---|
| 1235 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1236 | unsigned u1Write : 1;
|
---|
| 1237 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 1238 | unsigned u1User : 1;
|
---|
| 1239 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1240 | unsigned u1WriteThru : 1;
|
---|
| 1241 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1242 | unsigned u1CacheDisable : 1;
|
---|
| 1243 | /** Accessed flag.
|
---|
| 1244 | * Indicates that the page have been read or written to. */
|
---|
| 1245 | unsigned u1Accessed : 1;
|
---|
| 1246 | /** Dirty flag.
|
---|
| 1247 | * Indicates that the page have been written to. */
|
---|
| 1248 | unsigned u1Dirty : 1;
|
---|
| 1249 | /** Page size flag - always 1 for 4MB entries. */
|
---|
| 1250 | unsigned u1Size : 1;
|
---|
| 1251 | /** Global flag. */
|
---|
| 1252 | unsigned u1Global : 1;
|
---|
| 1253 | /** Available for use to system software. */
|
---|
| 1254 | unsigned u3Available : 3;
|
---|
| 1255 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 1256 | unsigned u1PAT : 1;
|
---|
| 1257 | /** Bits 32-39 of the page number on AMD64.
|
---|
| 1258 | * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
|
---|
| 1259 | unsigned u8PageNoHigh : 8;
|
---|
| 1260 | /** Reserved. */
|
---|
| 1261 | unsigned u1Reserved : 1;
|
---|
| 1262 | /** Physical Page number of the page. */
|
---|
| 1263 | unsigned u10PageNo : 10;
|
---|
| 1264 | } X86PDE4MBITS;
|
---|
| 1265 | /** Pointer to a page table entry. */
|
---|
| 1266 | typedef X86PDE4MBITS *PX86PDE4MBITS;
|
---|
| 1267 | /** Pointer to a const page table entry. */
|
---|
| 1268 | typedef const X86PDE4MBITS *PCX86PDE4MBITS;
|
---|
| 1269 |
|
---|
| 1270 |
|
---|
| 1271 | /**
|
---|
| 1272 | * 2MB PAE page directory entry.
|
---|
| 1273 | */
|
---|
| 1274 | typedef struct X86PDE2MPAEBITS
|
---|
| 1275 | {
|
---|
| 1276 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1277 | uint32_t u1Present : 1;
|
---|
| 1278 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1279 | uint32_t u1Write : 1;
|
---|
| 1280 | /** User(=1) / Supervisor(=0) flag. */
|
---|
| 1281 | uint32_t u1User : 1;
|
---|
| 1282 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1283 | uint32_t u1WriteThru : 1;
|
---|
| 1284 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1285 | uint32_t u1CacheDisable : 1;
|
---|
| 1286 | /** Accessed flag.
|
---|
| 1287 | * Indicates that the page have been read or written to. */
|
---|
| 1288 | uint32_t u1Accessed : 1;
|
---|
| 1289 | /** Dirty flag.
|
---|
| 1290 | * Indicates that the page have been written to. */
|
---|
| 1291 | uint32_t u1Dirty : 1;
|
---|
| 1292 | /** Page size flag - always 1 for 2MB entries. */
|
---|
| 1293 | uint32_t u1Size : 1;
|
---|
| 1294 | /** Global flag. */
|
---|
| 1295 | uint32_t u1Global : 1;
|
---|
| 1296 | /** Available for use to system software. */
|
---|
| 1297 | uint32_t u3Available : 3;
|
---|
| 1298 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 1299 | uint32_t u1PAT : 1;
|
---|
| 1300 | /** Reserved. */
|
---|
| 1301 | uint32_t u9Reserved : 9;
|
---|
| 1302 | /** Physical Page number of the next level - Low part. Don't use! */
|
---|
| 1303 | uint32_t u10PageNoLow : 10;
|
---|
| 1304 | /** Physical Page number of the next level - High part. Don't use! */
|
---|
| 1305 | uint32_t u20PageNoHigh : 20;
|
---|
| 1306 | /** MBZ bits */
|
---|
| 1307 | uint32_t u11Reserved : 11;
|
---|
| 1308 | /** No Execute flag. */
|
---|
| 1309 | uint32_t u1NoExecute : 1;
|
---|
| 1310 | } X86PDE2MPAEBITS;
|
---|
| 1311 | /** Pointer to a 4MB PAE page table entry. */
|
---|
| 1312 | typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
|
---|
| 1313 | /** Pointer to a 4MB PAE page table entry. */
|
---|
| 1314 | typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
|
---|
| 1315 |
|
---|
| 1316 | /** @} */
|
---|
| 1317 |
|
---|
| 1318 | /**
|
---|
| 1319 | * Page directory entry.
|
---|
| 1320 | */
|
---|
| 1321 | typedef union X86PDE
|
---|
| 1322 | {
|
---|
| 1323 | /** Normal view. */
|
---|
| 1324 | X86PDEBITS n;
|
---|
| 1325 | /** 4MB view (big). */
|
---|
| 1326 | X86PDE4MBITS b;
|
---|
| 1327 | /** Unsigned integer view. */
|
---|
| 1328 | X86PGUINT u;
|
---|
| 1329 | /** 8 bit unsigned integer view. */
|
---|
| 1330 | uint8_t au8[4];
|
---|
| 1331 | /** 16 bit unsigned integer view. */
|
---|
| 1332 | uint16_t au16[2];
|
---|
| 1333 | /** 32 bit unsigned integer view. */
|
---|
| 1334 | uint32_t au32[1];
|
---|
| 1335 | } X86PDE;
|
---|
| 1336 | /** Pointer to a page directory entry. */
|
---|
| 1337 | typedef X86PDE *PX86PDE;
|
---|
| 1338 | /** Pointer to a const page directory entry. */
|
---|
| 1339 | typedef const X86PDE *PCX86PDE;
|
---|
| 1340 |
|
---|
| 1341 | /**
|
---|
| 1342 | * PAE page directory entry.
|
---|
| 1343 | */
|
---|
| 1344 | typedef union X86PDEPAE
|
---|
| 1345 | {
|
---|
| 1346 | /** Normal view. */
|
---|
| 1347 | X86PDEPAEBITS n;
|
---|
| 1348 | /** 2MB page view (big). */
|
---|
| 1349 | X86PDE2MPAEBITS b;
|
---|
| 1350 | /** Unsigned integer view. */
|
---|
| 1351 | X86PGPAEUINT u;
|
---|
| 1352 | /** 8 bit unsigned integer view. */
|
---|
| 1353 | uint8_t au8[8];
|
---|
| 1354 | /** 16 bit unsigned integer view. */
|
---|
| 1355 | uint16_t au16[4];
|
---|
| 1356 | /** 32 bit unsigned integer view. */
|
---|
| 1357 | uint32_t au32[2];
|
---|
| 1358 | } X86PDEPAE;
|
---|
| 1359 | /** Pointer to a page directory entry. */
|
---|
| 1360 | typedef X86PDEPAE *PX86PDEPAE;
|
---|
| 1361 | /** Pointer to a const page directory entry. */
|
---|
| 1362 | typedef const X86PDEPAE *PCX86PDEPAE;
|
---|
| 1363 |
|
---|
| 1364 | /**
|
---|
| 1365 | * Page directory.
|
---|
| 1366 | */
|
---|
| 1367 | typedef struct X86PD
|
---|
| 1368 | {
|
---|
| 1369 | /** PDE Array. */
|
---|
| 1370 | X86PDE a[X86_PG_ENTRIES];
|
---|
| 1371 | } X86PD;
|
---|
| 1372 | /** Pointer to a page directory. */
|
---|
| 1373 | typedef X86PD *PX86PD;
|
---|
| 1374 | /** Pointer to a const page directory. */
|
---|
| 1375 | typedef const X86PD *PCX86PD;
|
---|
| 1376 |
|
---|
| 1377 | /** The page shift to get the PD index. */
|
---|
| 1378 | #define X86_PD_SHIFT 22
|
---|
| 1379 | /** The PD index mask (apply to a shifted page address). */
|
---|
| 1380 | #define X86_PD_MASK 0x3ff
|
---|
| 1381 |
|
---|
| 1382 |
|
---|
| 1383 | /**
|
---|
| 1384 | * PAE page directory.
|
---|
| 1385 | */
|
---|
| 1386 | typedef struct X86PDPAE
|
---|
| 1387 | {
|
---|
| 1388 | /** PDE Array. */
|
---|
| 1389 | X86PDEPAE a[X86_PG_PAE_ENTRIES];
|
---|
| 1390 | } X86PDPAE;
|
---|
| 1391 | /** Pointer to a PAE page directory. */
|
---|
| 1392 | typedef X86PDPAE *PX86PDPAE;
|
---|
| 1393 | /** Pointer to a const PAE page directory. */
|
---|
| 1394 | typedef const X86PDPAE *PCX86PDPAE;
|
---|
| 1395 |
|
---|
| 1396 | /** The page shift to get the PAE PD index. */
|
---|
| 1397 | #define X86_PD_PAE_SHIFT 21
|
---|
| 1398 | /** The PAE PD index mask (apply to a shifted page address). */
|
---|
| 1399 | #define X86_PD_PAE_MASK 0x1ff
|
---|
| 1400 |
|
---|
| 1401 |
|
---|
| 1402 | /** @name Page Directory Pointer Table Entry (PAE)
|
---|
| 1403 | * @{
|
---|
| 1404 | */
|
---|
| 1405 | /** Bit 0 - P - Present bit. */
|
---|
[5605] | 1406 | #define X86_PDPE_P RT_BIT(0)
|
---|
[1] | 1407 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
|
---|
[5605] | 1408 | #define X86_PDPE_RW RT_BIT(1)
|
---|
[1] | 1409 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
|
---|
[5605] | 1410 | #define X86_PDPE_US RT_BIT(2)
|
---|
[1] | 1411 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[5605] | 1412 | #define X86_PDPE_PWT RT_BIT(3)
|
---|
[1] | 1413 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[5605] | 1414 | #define X86_PDPE_PCD RT_BIT(4)
|
---|
[1] | 1415 | /** Bit 5 - A - Access bit. Long Mode only. */
|
---|
[5605] | 1416 | #define X86_PDPE_A RT_BIT(5)
|
---|
[1] | 1417 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[5605] | 1418 | #define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
|
---|
[1] | 1419 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
| 1420 | #if 1 /* we're using this internally and have to mask of the top 16-bit. */
|
---|
| 1421 | #define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
|
---|
| 1422 | #else
|
---|
| 1423 | #define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
|
---|
| 1424 | #endif
|
---|
[7730] | 1425 | /** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
|
---|
[5605] | 1426 | #define X86_PDPE_NX RT_BIT_64(63)
|
---|
[1] | 1427 |
|
---|
| 1428 | /**
|
---|
| 1429 | * Page directory pointer table entry.
|
---|
| 1430 | */
|
---|
| 1431 | typedef struct X86PDPEBITS
|
---|
| 1432 | {
|
---|
| 1433 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1434 | uint32_t u1Present : 1;
|
---|
| 1435 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1436 | uint32_t u1Write : 1;
|
---|
| 1437 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 1438 | uint32_t u1User : 1;
|
---|
| 1439 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1440 | uint32_t u1WriteThru : 1;
|
---|
| 1441 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1442 | uint32_t u1CacheDisable : 1;
|
---|
| 1443 | /** Accessed flag.
|
---|
| 1444 | * Indicates that the page have been read or written to. */
|
---|
| 1445 | uint32_t u1Accessed : 1;
|
---|
| 1446 | /** Chunk of reserved bits. */
|
---|
| 1447 | uint32_t u3Reserved : 3;
|
---|
| 1448 | /** Available for use to system software. */
|
---|
| 1449 | uint32_t u3Available : 3;
|
---|
| 1450 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 1451 | uint32_t u20PageNoLow : 20;
|
---|
| 1452 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 1453 | uint32_t u20PageNoHigh : 20;
|
---|
| 1454 | /** MBZ bits */
|
---|
| 1455 | uint32_t u11Reserved : 11;
|
---|
| 1456 | /** No Execute flag. */
|
---|
| 1457 | uint32_t u1NoExecute : 1;
|
---|
| 1458 | } X86PDPEBITS;
|
---|
| 1459 | /** Pointer to a page directory pointer table entry. */
|
---|
| 1460 | typedef X86PDPEBITS *PX86PTPEBITS;
|
---|
| 1461 | /** Pointer to a const page directory pointer table entry. */
|
---|
| 1462 | typedef const X86PDPEBITS *PCX86PTPEBITS;
|
---|
| 1463 |
|
---|
| 1464 | /**
|
---|
| 1465 | * Page directory pointer table entry.
|
---|
| 1466 | */
|
---|
| 1467 | typedef union X86PDPE
|
---|
| 1468 | {
|
---|
| 1469 | /** Normal view. */
|
---|
| 1470 | X86PDPEBITS n;
|
---|
| 1471 | /** Unsigned integer view. */
|
---|
| 1472 | X86PGPAEUINT u;
|
---|
| 1473 | /** 8 bit unsigned integer view. */
|
---|
| 1474 | uint8_t au8[8];
|
---|
| 1475 | /** 16 bit unsigned integer view. */
|
---|
| 1476 | uint16_t au16[4];
|
---|
| 1477 | /** 32 bit unsigned integer view. */
|
---|
| 1478 | uint32_t au32[2];
|
---|
| 1479 | } X86PDPE;
|
---|
| 1480 | /** Pointer to a page directory pointer table entry. */
|
---|
| 1481 | typedef X86PDPE *PX86PDPE;
|
---|
| 1482 | /** Pointer to a const page directory pointer table entry. */
|
---|
| 1483 | typedef const X86PDPE *PCX86PDPE;
|
---|
| 1484 |
|
---|
| 1485 |
|
---|
| 1486 | /**
|
---|
| 1487 | * Page directory pointer table.
|
---|
| 1488 | */
|
---|
[7715] | 1489 | typedef struct X86PDPT
|
---|
[1] | 1490 | {
|
---|
| 1491 | /** PDE Array. */
|
---|
[7677] | 1492 | X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
|
---|
[7715] | 1493 | } X86PDPT;
|
---|
[1] | 1494 | /** Pointer to a page directory pointer table. */
|
---|
[7715] | 1495 | typedef X86PDPT *PX86PDPT;
|
---|
[1] | 1496 | /** Pointer to a const page directory pointer table. */
|
---|
[7715] | 1497 | typedef const X86PDPT *PCX86PDPT;
|
---|
[1] | 1498 |
|
---|
[7715] | 1499 | /** The page shift to get the PDPT index. */
|
---|
| 1500 | #define X86_PDPT_SHIFT 30
|
---|
| 1501 | /** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
|
---|
[7728] | 1502 | #define X86_PDPT_MASK_PAE 0x3
|
---|
[7715] | 1503 | /** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
|
---|
[7728] | 1504 | #define X86_PDPT_MASK_AMD64 0x1ff
|
---|
[1] | 1505 |
|
---|
| 1506 | /** @} */
|
---|
| 1507 |
|
---|
| 1508 |
|
---|
| 1509 | /** @name Page Map Level-4 Entry (Long Mode PAE)
|
---|
| 1510 | * @{
|
---|
| 1511 | */
|
---|
| 1512 | /** Bit 0 - P - Present bit. */
|
---|
[5605] | 1513 | #define X86_PML4E_P RT_BIT(0)
|
---|
[1] | 1514 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[5605] | 1515 | #define X86_PML4E_RW RT_BIT(1)
|
---|
[1] | 1516 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[5605] | 1517 | #define X86_PML4E_US RT_BIT(2)
|
---|
[1] | 1518 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[5605] | 1519 | #define X86_PML4E_PWT RT_BIT(3)
|
---|
[1] | 1520 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[5605] | 1521 | #define X86_PML4E_PCD RT_BIT(4)
|
---|
[1] | 1522 | /** Bit 5 - A - Access bit. */
|
---|
[5605] | 1523 | #define X86_PML4E_A RT_BIT(5)
|
---|
[1] | 1524 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[5605] | 1525 | #define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
|
---|
[1] | 1526 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
| 1527 | #if 1 /* we're using this internally and have to mask of the top 16-bit. */
|
---|
| 1528 | #define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
|
---|
| 1529 | #else
|
---|
| 1530 | #define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
|
---|
| 1531 | #endif
|
---|
| 1532 | /** Bits 63 - NX - PAE - No execution flag. */
|
---|
[5605] | 1533 | #define X86_PML4E_NX RT_BIT_64(63)
|
---|
[1] | 1534 |
|
---|
| 1535 | /**
|
---|
| 1536 | * Page Map Level-4 Entry
|
---|
| 1537 | */
|
---|
| 1538 | typedef struct X86PML4EBITS
|
---|
| 1539 | {
|
---|
| 1540 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1541 | uint32_t u1Present : 1;
|
---|
| 1542 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1543 | uint32_t u1Write : 1;
|
---|
| 1544 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 1545 | uint32_t u1User : 1;
|
---|
| 1546 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1547 | uint32_t u1WriteThru : 1;
|
---|
| 1548 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1549 | uint32_t u1CacheDisable : 1;
|
---|
| 1550 | /** Accessed flag.
|
---|
| 1551 | * Indicates that the page have been read or written to. */
|
---|
| 1552 | uint32_t u1Accessed : 1;
|
---|
| 1553 | /** Chunk of reserved bits. */
|
---|
| 1554 | uint32_t u3Reserved : 3;
|
---|
| 1555 | /** Available for use to system software. */
|
---|
| 1556 | uint32_t u3Available : 3;
|
---|
| 1557 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 1558 | uint32_t u20PageNoLow : 20;
|
---|
| 1559 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 1560 | uint32_t u20PageNoHigh : 20;
|
---|
| 1561 | /** MBZ bits */
|
---|
| 1562 | uint32_t u11Reserved : 11;
|
---|
| 1563 | /** No Execute flag. */
|
---|
| 1564 | uint32_t u1NoExecute : 1;
|
---|
| 1565 | } X86PML4EBITS;
|
---|
| 1566 | /** Pointer to a page map level-4 entry. */
|
---|
| 1567 | typedef X86PML4EBITS *PX86PML4EBITS;
|
---|
| 1568 | /** Pointer to a const page map level-4 entry. */
|
---|
| 1569 | typedef const X86PML4EBITS *PCX86PML4EBITS;
|
---|
| 1570 |
|
---|
| 1571 | /**
|
---|
| 1572 | * Page Map Level-4 Entry.
|
---|
| 1573 | */
|
---|
| 1574 | typedef union X86PML4E
|
---|
| 1575 | {
|
---|
| 1576 | /** Normal view. */
|
---|
| 1577 | X86PML4EBITS n;
|
---|
| 1578 | /** Unsigned integer view. */
|
---|
| 1579 | X86PGPAEUINT u;
|
---|
| 1580 | /** 8 bit unsigned integer view. */
|
---|
| 1581 | uint8_t au8[8];
|
---|
| 1582 | /** 16 bit unsigned integer view. */
|
---|
| 1583 | uint16_t au16[4];
|
---|
| 1584 | /** 32 bit unsigned integer view. */
|
---|
| 1585 | uint32_t au32[2];
|
---|
| 1586 | } X86PML4E;
|
---|
| 1587 | /** Pointer to a page map level-4 entry. */
|
---|
| 1588 | typedef X86PML4E *PX86PML4E;
|
---|
| 1589 | /** Pointer to a const page map level-4 entry. */
|
---|
| 1590 | typedef const X86PML4E *PCX86PML4E;
|
---|
| 1591 |
|
---|
| 1592 |
|
---|
| 1593 | /**
|
---|
| 1594 | * Page Map Level-4.
|
---|
| 1595 | */
|
---|
| 1596 | typedef struct X86PML4
|
---|
| 1597 | {
|
---|
| 1598 | /** PDE Array. */
|
---|
| 1599 | X86PML4E a[X86_PG_PAE_ENTRIES];
|
---|
| 1600 | } X86PML4;
|
---|
| 1601 | /** Pointer to a page map level-4. */
|
---|
| 1602 | typedef X86PML4 *PX86PML4;
|
---|
| 1603 | /** Pointer to a const page map level-4. */
|
---|
| 1604 | typedef const X86PML4 *PCX86PML4;
|
---|
| 1605 |
|
---|
| 1606 | /** The page shift to get the PML4 index. */
|
---|
| 1607 | #define X86_PML4_SHIFT 39
|
---|
| 1608 | /** The PML4 index mask (apply to a shifted page address). */
|
---|
| 1609 | #define X86_PML4_MASK 0x1ff
|
---|
| 1610 |
|
---|
| 1611 | /** @} */
|
---|
| 1612 |
|
---|
| 1613 | /** @} */
|
---|
| 1614 |
|
---|
| 1615 |
|
---|
| 1616 | /**
|
---|
| 1617 | * 80-bit MMX/FPU register type.
|
---|
| 1618 | */
|
---|
| 1619 | typedef struct X86FPUMMX
|
---|
| 1620 | {
|
---|
| 1621 | uint8_t reg[10];
|
---|
| 1622 | } X86FPUMMX;
|
---|
| 1623 | /** Pointer to a 80-bit MMX/FPU register type. */
|
---|
| 1624 | typedef X86FPUMMX *PX86FPUMMX;
|
---|
| 1625 | /** Pointer to a const 80-bit MMX/FPU register type. */
|
---|
| 1626 | typedef const X86FPUMMX *PCX86FPUMMX;
|
---|
| 1627 |
|
---|
| 1628 | /**
|
---|
| 1629 | * FPU state (aka FSAVE/FRSTOR Memory Region).
|
---|
| 1630 | */
|
---|
| 1631 | #pragma pack(1)
|
---|
| 1632 | typedef struct X86FPUSTATE
|
---|
| 1633 | {
|
---|
| 1634 | /** Control word. */
|
---|
| 1635 | uint16_t FCW;
|
---|
| 1636 | /** Alignment word */
|
---|
| 1637 | uint16_t Dummy1;
|
---|
| 1638 | /** Status word. */
|
---|
| 1639 | uint16_t FSW;
|
---|
| 1640 | /** Alignment word */
|
---|
| 1641 | uint16_t Dummy2;
|
---|
| 1642 | /** Tag word */
|
---|
| 1643 | uint16_t FTW;
|
---|
| 1644 | /** Alignment word */
|
---|
| 1645 | uint16_t Dummy3;
|
---|
| 1646 |
|
---|
| 1647 | /** Instruction pointer. */
|
---|
| 1648 | uint32_t FPUIP;
|
---|
| 1649 | /** Code selector. */
|
---|
| 1650 | uint16_t CS;
|
---|
| 1651 | /** Opcode. */
|
---|
| 1652 | uint16_t FOP;
|
---|
| 1653 | /** FOO. */
|
---|
| 1654 | uint32_t FPUOO;
|
---|
| 1655 | /** FOS. */
|
---|
| 1656 | uint32_t FPUOS;
|
---|
| 1657 | /** FPU view - todo. */
|
---|
| 1658 | X86FPUMMX regs[8];
|
---|
| 1659 | } X86FPUSTATE;
|
---|
| 1660 | #pragma pack()
|
---|
| 1661 | /** Pointer to a FPU state. */
|
---|
| 1662 | typedef X86FPUSTATE *PX86FPUSTATE;
|
---|
| 1663 | /** Pointer to a const FPU state. */
|
---|
| 1664 | typedef const X86FPUSTATE *PCX86FPUSTATE;
|
---|
| 1665 |
|
---|
| 1666 | /**
|
---|
| 1667 | * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
|
---|
| 1668 | */
|
---|
| 1669 | #pragma pack(1)
|
---|
| 1670 | typedef struct X86FXSTATE
|
---|
| 1671 | {
|
---|
| 1672 | /** Control word. */
|
---|
| 1673 | uint16_t FCW;
|
---|
| 1674 | /** Status word. */
|
---|
| 1675 | uint16_t FSW;
|
---|
| 1676 | /** Tag word (it's a byte actually). */
|
---|
| 1677 | uint8_t FTW;
|
---|
| 1678 | uint8_t huh1;
|
---|
| 1679 | /** Opcode. */
|
---|
| 1680 | uint16_t FOP;
|
---|
| 1681 | /** Instruction pointer. */
|
---|
| 1682 | uint32_t FPUIP;
|
---|
| 1683 | /** Code selector. */
|
---|
| 1684 | uint16_t CS;
|
---|
| 1685 | uint16_t Rsvrd1;
|
---|
| 1686 | /* - offset 16 - */
|
---|
| 1687 | /** Data pointer. */
|
---|
| 1688 | uint32_t FPUDP;
|
---|
| 1689 | /** Data segment */
|
---|
| 1690 | uint16_t DS;
|
---|
| 1691 | uint16_t Rsrvd2;
|
---|
| 1692 | uint32_t MXCSR;
|
---|
| 1693 | uint32_t MXCSR_MASK;
|
---|
| 1694 | /* - offset 32 - */
|
---|
| 1695 | union
|
---|
| 1696 | {
|
---|
| 1697 | /** MMX view. */
|
---|
| 1698 | uint64_t mmx;
|
---|
| 1699 | /** FPU view - todo. */
|
---|
| 1700 | X86FPUMMX fpu;
|
---|
| 1701 | /** 8-bit view. */
|
---|
| 1702 | uint8_t au8[16];
|
---|
| 1703 | /** 16-bit view. */
|
---|
| 1704 | uint16_t au16[8];
|
---|
| 1705 | /** 32-bit view. */
|
---|
| 1706 | uint32_t au32[4];
|
---|
| 1707 | /** 64-bit view. */
|
---|
| 1708 | uint64_t au64[2];
|
---|
| 1709 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 1710 | uint128_t au128[1];
|
---|
| 1711 | } aRegs[8];
|
---|
| 1712 | /* - offset 160 - */
|
---|
| 1713 | union
|
---|
| 1714 | {
|
---|
| 1715 | /** XMM Register view *. */
|
---|
| 1716 | uint128_t xmm;
|
---|
| 1717 | /** 8-bit view. */
|
---|
| 1718 | uint8_t au8[16];
|
---|
| 1719 | /** 16-bit view. */
|
---|
| 1720 | uint16_t au16[8];
|
---|
| 1721 | /** 32-bit view. */
|
---|
| 1722 | uint32_t au32[4];
|
---|
| 1723 | /** 64-bit view. */
|
---|
| 1724 | uint64_t au64[2];
|
---|
| 1725 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 1726 | uint128_t au128[1];
|
---|
[7095] | 1727 | } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
|
---|
| 1728 | /* - offset 416 - */
|
---|
| 1729 | uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
|
---|
[1] | 1730 | } X86FXSTATE;
|
---|
| 1731 | #pragma pack()
|
---|
| 1732 | /** Pointer to a FPU Extended state. */
|
---|
| 1733 | typedef X86FXSTATE *PX86FXSTATE;
|
---|
| 1734 | /** Pointer to a const FPU Extended state. */
|
---|
| 1735 | typedef const X86FXSTATE *PCX86FXSTATE;
|
---|
| 1736 |
|
---|
| 1737 |
|
---|
| 1738 | /** @name Selector Descriptor
|
---|
| 1739 | * @{
|
---|
| 1740 | */
|
---|
| 1741 |
|
---|
| 1742 | /**
|
---|
| 1743 | * Generic descriptor table entry
|
---|
| 1744 | */
|
---|
| 1745 | #pragma pack(1)
|
---|
| 1746 | typedef struct X86DESCGENERIC
|
---|
| 1747 | {
|
---|
| 1748 | /** Limit - Low word. */
|
---|
| 1749 | unsigned u16LimitLow : 16;
|
---|
| 1750 | /** Base address - lowe word.
|
---|
| 1751 | * Don't try set this to 24 because MSC is doing studing things then. */
|
---|
| 1752 | unsigned u16BaseLow : 16;
|
---|
| 1753 | /** Base address - first 8 bits of high word. */
|
---|
| 1754 | unsigned u8BaseHigh1 : 8;
|
---|
| 1755 | /** Segment Type. */
|
---|
| 1756 | unsigned u4Type : 4;
|
---|
| 1757 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
| 1758 | unsigned u1DescType : 1;
|
---|
| 1759 | /** Descriptor Privelege level. */
|
---|
| 1760 | unsigned u2Dpl : 2;
|
---|
| 1761 | /** Flags selector present(=1) or not. */
|
---|
| 1762 | unsigned u1Present : 1;
|
---|
| 1763 | /** Segment limit 16-19. */
|
---|
| 1764 | unsigned u4LimitHigh : 4;
|
---|
| 1765 | /** Available for system software. */
|
---|
| 1766 | unsigned u1Available : 1;
|
---|
| 1767 | /** Reserved - 0. */
|
---|
| 1768 | unsigned u1Reserved : 1;
|
---|
| 1769 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 1770 | * of the intel manual yourself. */
|
---|
| 1771 | unsigned u1DefBig : 1;
|
---|
| 1772 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 1773 | * clear byte. */
|
---|
| 1774 | unsigned u1Granularity : 1;
|
---|
| 1775 | /** Base address - highest 8 bits. */
|
---|
| 1776 | unsigned u8BaseHigh2 : 8;
|
---|
| 1777 | } X86DESCGENERIC;
|
---|
| 1778 | #pragma pack()
|
---|
| 1779 | /** Pointer to a generic descriptor entry. */
|
---|
| 1780 | typedef X86DESCGENERIC *PX86DESCGENERIC;
|
---|
| 1781 | /** Pointer to a const generic descriptor entry. */
|
---|
| 1782 | typedef const X86DESCGENERIC *PCX86DESCGENERIC;
|
---|
| 1783 |
|
---|
| 1784 |
|
---|
| 1785 | /**
|
---|
| 1786 | * Descriptor attributes.
|
---|
| 1787 | */
|
---|
| 1788 | typedef struct X86DESCATTRBITS
|
---|
| 1789 | {
|
---|
| 1790 | /** Segment Type. */
|
---|
| 1791 | unsigned u4Type : 4;
|
---|
| 1792 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
| 1793 | unsigned u1DescType : 1;
|
---|
| 1794 | /** Descriptor Privelege level. */
|
---|
| 1795 | unsigned u2Dpl : 2;
|
---|
| 1796 | /** Flags selector present(=1) or not. */
|
---|
| 1797 | unsigned u1Present : 1;
|
---|
| 1798 | /** Segment limit 16-19. */
|
---|
| 1799 | unsigned u4LimitHigh : 4;
|
---|
| 1800 | /** Available for system software. */
|
---|
| 1801 | unsigned u1Available : 1;
|
---|
| 1802 | /** Reserved - 0. */
|
---|
| 1803 | unsigned u1Reserved : 1;
|
---|
| 1804 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 1805 | * of the intel manual yourself. */
|
---|
| 1806 | unsigned u1DefBig : 1;
|
---|
| 1807 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 1808 | * clear byte. */
|
---|
| 1809 | unsigned u1Granularity : 1;
|
---|
| 1810 | } X86DESCATTRBITS;
|
---|
| 1811 |
|
---|
| 1812 |
|
---|
| 1813 | #pragma pack(1)
|
---|
| 1814 | typedef union X86DESCATTR
|
---|
| 1815 | {
|
---|
| 1816 | /** Normal view. */
|
---|
| 1817 | X86DESCATTRBITS n;
|
---|
| 1818 | /** Unsigned integer view. */
|
---|
| 1819 | uint32_t u;
|
---|
| 1820 | } X86DESCATTR;
|
---|
| 1821 | #pragma pack()
|
---|
| 1822 |
|
---|
| 1823 | /** Pointer to descriptor attributes. */
|
---|
| 1824 | typedef X86DESCATTR *PX86DESCATTR;
|
---|
| 1825 | /** Pointer to const descriptor attributes. */
|
---|
| 1826 | typedef const X86DESCATTR *PCX86DESCATTR;
|
---|
| 1827 |
|
---|
| 1828 |
|
---|
| 1829 | /**
|
---|
| 1830 | * Descriptor table entry.
|
---|
| 1831 | */
|
---|
| 1832 | #pragma pack(1)
|
---|
| 1833 | typedef union X86DESC
|
---|
| 1834 | {
|
---|
| 1835 | /** Generic descriptor view. */
|
---|
| 1836 | X86DESCGENERIC Gen;
|
---|
| 1837 | #if 0
|
---|
| 1838 | /** IDT view. */
|
---|
| 1839 | VBOXIDTE Idt;
|
---|
| 1840 | #endif
|
---|
| 1841 |
|
---|
| 1842 | /** 8 bit unsigned interger view. */
|
---|
| 1843 | uint8_t au8[8];
|
---|
| 1844 | /** 16 bit unsigned interger view. */
|
---|
| 1845 | uint16_t au16[4];
|
---|
| 1846 | /** 32 bit unsigned interger view. */
|
---|
| 1847 | uint32_t au32[2];
|
---|
| 1848 | } X86DESC;
|
---|
| 1849 | #pragma pack()
|
---|
| 1850 | /** Pointer to descriptor table entry. */
|
---|
| 1851 | typedef X86DESC *PX86DESC;
|
---|
| 1852 | /** Pointer to const descriptor table entry. */
|
---|
| 1853 | typedef const X86DESC *PCX86DESC;
|
---|
| 1854 |
|
---|
| 1855 |
|
---|
[2806] | 1856 | /**
|
---|
[2808] | 1857 | * 64 bits generic descriptor table entry
|
---|
| 1858 | * Note: most of these bits have no meaning in long mode.
|
---|
| 1859 | */
|
---|
| 1860 | #pragma pack(1)
|
---|
| 1861 | typedef struct X86DESC64GENERIC
|
---|
| 1862 | {
|
---|
| 1863 | /** Limit - Low word - *IGNORED*. */
|
---|
| 1864 | unsigned u16LimitLow : 16;
|
---|
| 1865 | /** Base address - lowe word. - *IGNORED*
|
---|
| 1866 | * Don't try set this to 24 because MSC is doing studing things then. */
|
---|
| 1867 | unsigned u16BaseLow : 16;
|
---|
| 1868 | /** Base address - first 8 bits of high word. - *IGNORED* */
|
---|
| 1869 | unsigned u8BaseHigh1 : 8;
|
---|
| 1870 | /** Segment Type. */
|
---|
| 1871 | unsigned u4Type : 4;
|
---|
| 1872 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
| 1873 | unsigned u1DescType : 1;
|
---|
| 1874 | /** Descriptor Privelege level. */
|
---|
| 1875 | unsigned u2Dpl : 2;
|
---|
| 1876 | /** Flags selector present(=1) or not. */
|
---|
| 1877 | unsigned u1Present : 1;
|
---|
| 1878 | /** Segment limit 16-19. - *IGNORED* */
|
---|
| 1879 | unsigned u4LimitHigh : 4;
|
---|
| 1880 | /** Available for system software. - *IGNORED* */
|
---|
| 1881 | unsigned u1Available : 1;
|
---|
| 1882 | /** Long mode flag. */
|
---|
| 1883 | unsigned u1Long : 1;
|
---|
| 1884 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 1885 | * of the intel manual yourself. */
|
---|
| 1886 | unsigned u1DefBig : 1;
|
---|
| 1887 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 1888 | * clear byte. - *IGNORED* */
|
---|
| 1889 | unsigned u1Granularity : 1;
|
---|
| 1890 | /** Base address - highest 8 bits. - *IGNORED* */
|
---|
| 1891 | unsigned u8BaseHigh2 : 8;
|
---|
[2810] | 1892 | /** Base address - bits 63-32. */
|
---|
| 1893 | unsigned u32BaseHigh3 : 32;
|
---|
| 1894 | unsigned u8Reserved : 8;
|
---|
| 1895 | unsigned u5Zeros : 5;
|
---|
| 1896 | unsigned u19Reserved : 19;
|
---|
[2808] | 1897 | } X86DESC64GENERIC;
|
---|
| 1898 | #pragma pack()
|
---|
| 1899 | /** Pointer to a generic descriptor entry. */
|
---|
| 1900 | typedef X86DESC64GENERIC *PX86DESC64GENERIC;
|
---|
| 1901 | /** Pointer to a const generic descriptor entry. */
|
---|
| 1902 | typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
|
---|
| 1903 |
|
---|
| 1904 | /**
|
---|
[2806] | 1905 | * System descriptor table entry (64 bits)
|
---|
| 1906 | */
|
---|
| 1907 | #pragma pack(1)
|
---|
| 1908 | typedef struct X86DESC64SYSTEM
|
---|
| 1909 | {
|
---|
| 1910 | /** Limit - Low word. */
|
---|
| 1911 | unsigned u16LimitLow : 16;
|
---|
| 1912 | /** Base address - lowe word.
|
---|
| 1913 | * Don't try set this to 24 because MSC is doing studing things then. */
|
---|
| 1914 | unsigned u16BaseLow : 16;
|
---|
| 1915 | /** Base address - first 8 bits of high word. */
|
---|
| 1916 | unsigned u8BaseHigh1 : 8;
|
---|
| 1917 | /** Segment Type. */
|
---|
| 1918 | unsigned u4Type : 4;
|
---|
| 1919 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
| 1920 | unsigned u1DescType : 1;
|
---|
| 1921 | /** Descriptor Privelege level. */
|
---|
[2809] | 1922 | unsigned u2Dpl : 2;
|
---|
[2806] | 1923 | /** Flags selector present(=1) or not. */
|
---|
| 1924 | unsigned u1Present : 1;
|
---|
| 1925 | /** Segment limit 16-19. */
|
---|
| 1926 | unsigned u4LimitHigh : 4;
|
---|
| 1927 | /** Available for system software. */
|
---|
| 1928 | unsigned u1Available : 1;
|
---|
| 1929 | /** Reserved - 0. */
|
---|
| 1930 | unsigned u1Reserved : 1;
|
---|
| 1931 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 1932 | * of the intel manual yourself. */
|
---|
| 1933 | unsigned u1DefBig : 1;
|
---|
| 1934 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 1935 | * clear byte. */
|
---|
| 1936 | unsigned u1Granularity : 1;
|
---|
| 1937 | /** Base address - bits 31-24. */
|
---|
| 1938 | unsigned u8BaseHigh2 : 8;
|
---|
| 1939 | /** Base address - bits 63-32. */
|
---|
| 1940 | unsigned u32BaseHigh3 : 32;
|
---|
| 1941 | unsigned u8Reserved : 8;
|
---|
| 1942 | unsigned u5Zeros : 5;
|
---|
| 1943 | unsigned u19Reserved : 19;
|
---|
| 1944 | } X86DESC64SYSTEM;
|
---|
| 1945 | #pragma pack()
|
---|
| 1946 | /** Pointer to a generic descriptor entry. */
|
---|
| 1947 | typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
|
---|
| 1948 | /** Pointer to a const generic descriptor entry. */
|
---|
| 1949 | typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
|
---|
| 1950 |
|
---|
| 1951 |
|
---|
| 1952 | /**
|
---|
| 1953 | * Descriptor table entry.
|
---|
| 1954 | */
|
---|
| 1955 | #pragma pack(1)
|
---|
| 1956 | typedef union X86DESC64
|
---|
| 1957 | {
|
---|
| 1958 | /** Generic descriptor view. */
|
---|
[2808] | 1959 | X86DESC64GENERIC Gen;
|
---|
| 1960 | /** System descriptor view. */
|
---|
| 1961 | X86DESC64SYSTEM System;
|
---|
[2806] | 1962 | #if 0
|
---|
[2808] | 1963 | X86DESC64GATE Gate;
|
---|
[2806] | 1964 | #endif
|
---|
| 1965 |
|
---|
| 1966 | /** 8 bit unsigned interger view. */
|
---|
[2808] | 1967 | uint8_t au8[16];
|
---|
[2806] | 1968 | /** 16 bit unsigned interger view. */
|
---|
[2808] | 1969 | uint16_t au16[8];
|
---|
[2806] | 1970 | /** 32 bit unsigned interger view. */
|
---|
[2808] | 1971 | uint32_t au32[4];
|
---|
[2812] | 1972 | /** 64 bit unsigned interger view. */
|
---|
| 1973 | uint64_t au64[2];
|
---|
[2806] | 1974 | } X86DESC64;
|
---|
| 1975 | #pragma pack()
|
---|
| 1976 | /** Pointer to descriptor table entry. */
|
---|
| 1977 | typedef X86DESC64 *PX86DESC64;
|
---|
| 1978 | /** Pointer to const descriptor table entry. */
|
---|
| 1979 | typedef const X86DESC64 *PCX86DESC64;
|
---|
| 1980 |
|
---|
[2807] | 1981 | #if HC_ARCH_BITS == 64
|
---|
| 1982 | typedef X86DESC64 X86DESCHC;
|
---|
| 1983 | typedef X86DESC64 *PX86DESCHC;
|
---|
| 1984 | #else
|
---|
| 1985 | typedef X86DESC X86DESCHC;
|
---|
| 1986 | typedef X86DESC *PX86DESCHC;
|
---|
| 1987 | #endif
|
---|
[2806] | 1988 |
|
---|
[1] | 1989 | /** @name Selector Descriptor Types.
|
---|
| 1990 | * @{
|
---|
| 1991 | */
|
---|
| 1992 |
|
---|
| 1993 | /** @name Non-System Selector Types.
|
---|
| 1994 | * @{ */
|
---|
| 1995 | /** Code(=set)/Data(=clear) bit. */
|
---|
| 1996 | #define X86_SEL_TYPE_CODE 8
|
---|
[2104] | 1997 | /** Memory(=set)/System(=clear) bit. */
|
---|
[5605] | 1998 | #define X86_SEL_TYPE_MEMORY RT_BIT(4)
|
---|
[1] | 1999 | /** Accessed bit. */
|
---|
| 2000 | #define X86_SEL_TYPE_ACCESSED 1
|
---|
| 2001 | /** Expand down bit (for data selectors only). */
|
---|
| 2002 | #define X86_SEL_TYPE_DOWN 4
|
---|
| 2003 | /** Conforming bit (for code selectors only). */
|
---|
| 2004 | #define X86_SEL_TYPE_CONF 4
|
---|
| 2005 | /** Write bit (for data selectors only). */
|
---|
| 2006 | #define X86_SEL_TYPE_WRITE 2
|
---|
| 2007 | /** Read bit (for code selectors only). */
|
---|
| 2008 | #define X86_SEL_TYPE_READ 2
|
---|
| 2009 |
|
---|
| 2010 | /** Read only selector type. */
|
---|
| 2011 | #define X86_SEL_TYPE_RO 0
|
---|
| 2012 | /** Accessed read only selector type. */
|
---|
| 2013 | #define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
|
---|
| 2014 | /** Read write selector type. */
|
---|
| 2015 | #define X86_SEL_TYPE_RW 2
|
---|
| 2016 | /** Accessed read write selector type. */
|
---|
| 2017 | #define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
|
---|
| 2018 | /** Expand down read only selector type. */
|
---|
| 2019 | #define X86_SEL_TYPE_RO_DOWN 4
|
---|
| 2020 | /** Accessed expand down read only selector type. */
|
---|
| 2021 | #define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
|
---|
| 2022 | /** Expand down read write selector type. */
|
---|
| 2023 | #define X86_SEL_TYPE_RW_DOWN 6
|
---|
| 2024 | /** Accessed expand down read write selector type. */
|
---|
| 2025 | #define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
|
---|
| 2026 | /** Execute only selector type. */
|
---|
| 2027 | #define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
|
---|
| 2028 | /** Accessed execute only selector type. */
|
---|
| 2029 | #define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 2030 | /** Execute and read selector type. */
|
---|
| 2031 | #define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
|
---|
| 2032 | /** Accessed execute and read selector type. */
|
---|
| 2033 | #define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 2034 | /** Conforming execute only selector type. */
|
---|
| 2035 | #define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
|
---|
| 2036 | /** Accessed Conforming execute only selector type. */
|
---|
| 2037 | #define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 2038 | /** Conforming execute and write selector type. */
|
---|
| 2039 | #define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
|
---|
| 2040 | /** Accessed Conforming execute and write selector type. */
|
---|
| 2041 | #define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 2042 | /** @} */
|
---|
| 2043 |
|
---|
| 2044 |
|
---|
| 2045 | /** @name System Selector Types.
|
---|
| 2046 | * @{ */
|
---|
| 2047 | /** Undefined system selector type. */
|
---|
[2806] | 2048 | #define X86_SEL_TYPE_SYS_UNDEFINED 0
|
---|
[1] | 2049 | /** 286 TSS selector. */
|
---|
[2806] | 2050 | #define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
|
---|
[1] | 2051 | /** LDT selector. */
|
---|
[2806] | 2052 | #define X86_SEL_TYPE_SYS_LDT 2
|
---|
[1] | 2053 | /** 286 TSS selector - Busy. */
|
---|
[2806] | 2054 | #define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
|
---|
[1] | 2055 | /** 286 Callgate selector. */
|
---|
[2806] | 2056 | #define X86_SEL_TYPE_SYS_286_CALL_GATE 4
|
---|
[1] | 2057 | /** Taskgate selector. */
|
---|
[2806] | 2058 | #define X86_SEL_TYPE_SYS_TASK_GATE 5
|
---|
[1] | 2059 | /** 286 Interrupt gate selector. */
|
---|
[2806] | 2060 | #define X86_SEL_TYPE_SYS_286_INT_GATE 6
|
---|
[1] | 2061 | /** 286 Trapgate selector. */
|
---|
[2806] | 2062 | #define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
|
---|
[1] | 2063 | /** Undefined system selector. */
|
---|
[2806] | 2064 | #define X86_SEL_TYPE_SYS_UNDEFINED2 8
|
---|
[1] | 2065 | /** 386 TSS selector. */
|
---|
[2806] | 2066 | #define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
|
---|
[1] | 2067 | /** Undefined system selector. */
|
---|
[2806] | 2068 | #define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
|
---|
[1] | 2069 | /** 386 TSS selector - Busy. */
|
---|
[2806] | 2070 | #define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
|
---|
[1] | 2071 | /** 386 Callgate selector. */
|
---|
[2806] | 2072 | #define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
|
---|
[1] | 2073 | /** Undefined system selector. */
|
---|
[2806] | 2074 | #define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
|
---|
[1] | 2075 | /** 386 Interruptgate selector. */
|
---|
[2806] | 2076 | #define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
|
---|
[1] | 2077 | /** 386 Trapgate selector. */
|
---|
[2806] | 2078 | #define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
|
---|
[1] | 2079 | /** @} */
|
---|
| 2080 |
|
---|
[2806] | 2081 | /** @name AMD64 System Selector Types.
|
---|
| 2082 | * @{ */
|
---|
| 2083 | #define AMD64_SEL_TYPE_SYS_LDT 2
|
---|
| 2084 | /** 286 TSS selector - Busy. */
|
---|
| 2085 | #define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
|
---|
| 2086 | /** 386 TSS selector - Busy. */
|
---|
| 2087 | #define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
|
---|
| 2088 | /** 386 Callgate selector. */
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| 2089 | #define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
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| 2090 | /** 386 Interruptgate selector. */
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| 2091 | #define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
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| 2092 | /** 386 Trapgate selector. */
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| 2093 | #define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
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[1] | 2094 | /** @} */
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| 2095 |
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[2806] | 2096 | /** @} */
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[1] | 2097 |
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[2806] | 2098 |
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[1] | 2099 | /** @name Descriptor Table Entry Flag Masks.
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| 2100 | * These are for the 2nd 32-bit word of a descriptor.
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| 2101 | * @{ */
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| 2102 | /** Bits 8-11 - TYPE - Descriptor type mask. */
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[5605] | 2103 | #define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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[1] | 2104 | /** Bit 12 - S - System (=0) or Code/Data (=1). */
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[5605] | 2105 | #define X86_DESC_S RT_BIT(12)
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[1] | 2106 | /** Bits 13-14 - DPL - Descriptor Privilege Level. */
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[5605] | 2107 | #define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
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[1] | 2108 | /** Bit 15 - P - Present. */
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[5605] | 2109 | #define X86_DESC_P RT_BIT(15)
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[1] | 2110 | /** Bit 20 - AVL - Available for system software. */
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[5605] | 2111 | #define X86_DESC_AVL RT_BIT(20)
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[1] | 2112 | /** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
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[5605] | 2113 | #define X86_DESC_DB RT_BIT(22)
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[1] | 2114 | /** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
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| 2115 | * used, if clear byte. */
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[5605] | 2116 | #define X86_DESC_G RT_BIT(23)
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[1] | 2117 | /** @} */
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| 2118 |
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| 2119 | /** @} */
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| 2120 |
|
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| 2121 |
|
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| 2122 | /** @name Selectors.
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| 2123 | * @{
|
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| 2124 | */
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| 2125 |
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| 2126 | /**
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| 2127 | * The shift used to convert a selector from and to index an index (C).
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| 2128 | */
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[2815] | 2129 | #define X86_SEL_SHIFT 3
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[1] | 2130 |
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| 2131 | /**
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[2815] | 2132 | * The shift used to convert a selector from and to index an index (C).
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| 2133 | */
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| 2134 | #define AMD64_SEL_SHIFT 4
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| 2135 |
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| 2136 | #if HC_ARCH_BITS == 64
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| 2137 | #define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
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| 2138 | #else
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| 2139 | #define X86_SEL_SHIFT_HC X86_SEL_SHIFT
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| 2140 | #endif
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| 2141 |
|
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| 2142 | /**
|
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[1] | 2143 | * The mask used to mask off the table indicator and CPL of an selector.
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| 2144 | */
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[2815] | 2145 | #define X86_SEL_MASK 0xfff8
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[1] | 2146 |
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| 2147 | /**
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| 2148 | * The bit indicating that a selector is in the LDT and not in the GDT.
|
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| 2149 | */
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[2815] | 2150 | #define X86_SEL_LDT 0x0004
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[1] | 2151 | /**
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| 2152 | * The bit mask for getting the RPL of a selector.
|
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| 2153 | */
|
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[2815] | 2154 | #define X86_SEL_RPL 0x0003
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[1] | 2155 |
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| 2156 | /** @} */
|
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| 2157 |
|
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| 2158 |
|
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| 2159 | /**
|
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| 2160 | * x86 Exceptions/Faults/Traps.
|
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| 2161 | */
|
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| 2162 | typedef enum X86XCPT
|
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| 2163 | {
|
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| 2164 | /** \#DE - Divide error. */
|
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| 2165 | X86_XCPT_DE = 0x00,
|
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| 2166 | /** \#DB - Debug event (single step, DRx, ..) */
|
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| 2167 | X86_XCPT_DB = 0x01,
|
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| 2168 | /** NMI - Non-Maskable Interrupt */
|
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| 2169 | X86_XCPT_NMI = 0x02,
|
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| 2170 | /** \#BP - Breakpoint (INT3). */
|
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| 2171 | X86_XCPT_BP = 0x03,
|
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| 2172 | /** \#OF - Overflow (INTO). */
|
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| 2173 | X86_XCPT_OF = 0x04,
|
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| 2174 | /** \#BR - Bound range exceeded (BOUND). */
|
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| 2175 | X86_XCPT_BR = 0x05,
|
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| 2176 | /** \#UD - Undefined opcode. */
|
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| 2177 | X86_XCPT_UD = 0x06,
|
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| 2178 | /** \#NM - Device not available (math coprocessor device). */
|
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| 2179 | X86_XCPT_NM = 0x07,
|
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| 2180 | /** \#DF - Double fault. */
|
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| 2181 | X86_XCPT_DF = 0x08,
|
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| 2182 | /** ??? - Coprocessor segment overrun (obsolete). */
|
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| 2183 | X86_XCPT_CO_SEG_OVERRUN = 0x09,
|
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| 2184 | /** \#TS - Taskswitch (TSS). */
|
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| 2185 | X86_XCPT_TS = 0x0a,
|
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| 2186 | /** \#NP - Segment no present. */
|
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| 2187 | X86_XCPT_NP = 0x0b,
|
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| 2188 | /** \#SS - Stack segment fault. */
|
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| 2189 | X86_XCPT_SS = 0x0c,
|
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| 2190 | /** \#GP - General protection fault. */
|
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| 2191 | X86_XCPT_GP = 0x0d,
|
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| 2192 | /** \#PF - Page fault. */
|
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| 2193 | X86_XCPT_PF = 0x0e,
|
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| 2194 | /* 0x0f is reserved. */
|
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| 2195 | /** \#MF - Math fault (FPU). */
|
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| 2196 | X86_XCPT_MF = 0x10,
|
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| 2197 | /** \#AC - Alignment check. */
|
---|
| 2198 | X86_XCPT_AC = 0x11,
|
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| 2199 | /** \#MC - Machine check. */
|
---|
| 2200 | X86_XCPT_MC = 0x12,
|
---|
| 2201 | /** \#XF - SIMD Floating-Pointer Exception. */
|
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| 2202 | X86_XCPT_XF = 0x13
|
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| 2203 | } X86XCPT;
|
---|
| 2204 | /** Pointer to a x86 exception code. */
|
---|
| 2205 | typedef X86XCPT *PX86XCPT;
|
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| 2206 | /** Pointer to a const x86 exception code. */
|
---|
| 2207 | typedef const X86XCPT *PCX86XCPT;
|
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| 2208 |
|
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| 2209 |
|
---|
| 2210 | /** @name Trap Error Codes
|
---|
| 2211 | * @{
|
---|
| 2212 | */
|
---|
| 2213 | /** External indicator. */
|
---|
| 2214 | #define X86_TRAP_ERR_EXTERNAL 1
|
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| 2215 | /** IDT indicator. */
|
---|
| 2216 | #define X86_TRAP_ERR_IDT 2
|
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| 2217 | /** Descriptor table indicator - If set LDT, if clear GDT. */
|
---|
| 2218 | #define X86_TRAP_ERR_TI 4
|
---|
| 2219 | /** Mask for getting the selector. */
|
---|
| 2220 | #define X86_TRAP_ERR_SEL_MASK 0xfff8
|
---|
| 2221 | /** Shift for getting the selector table index (C type index). */
|
---|
| 2222 | #define X86_TRAP_ERR_SEL_SHIFT 3
|
---|
| 2223 | /** @} */
|
---|
| 2224 |
|
---|
| 2225 |
|
---|
| 2226 | /** @name \#PF Trap Error Codes
|
---|
| 2227 | * @{
|
---|
| 2228 | */
|
---|
| 2229 | /** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
|
---|
[5605] | 2230 | #define X86_TRAP_PF_P RT_BIT(0)
|
---|
[1] | 2231 | /** Bit 1 - R/W - Read (clear) or write (set) access. */
|
---|
[5605] | 2232 | #define X86_TRAP_PF_RW RT_BIT(1)
|
---|
[1] | 2233 | /** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
|
---|
[5605] | 2234 | #define X86_TRAP_PF_US RT_BIT(2)
|
---|
[1] | 2235 | /** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
|
---|
[5605] | 2236 | #define X86_TRAP_PF_RSVD RT_BIT(3)
|
---|
[1] | 2237 | /** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
|
---|
[5605] | 2238 | #define X86_TRAP_PF_ID RT_BIT(4)
|
---|
[1] | 2239 | /** @} */
|
---|
| 2240 |
|
---|
[1283] | 2241 | #pragma pack(1)
|
---|
[7121] | 2242 | /**
|
---|
[1283] | 2243 | * 32-bit IDTR/GDTR.
|
---|
| 2244 | */
|
---|
| 2245 | typedef struct X86XDTR32
|
---|
| 2246 | {
|
---|
| 2247 | /** Size of the descriptor table. */
|
---|
| 2248 | uint16_t cb;
|
---|
| 2249 | /** Address of the descriptor table. */
|
---|
| 2250 | uint32_t uAddr;
|
---|
| 2251 | } X86XDTR32, *PX86XDTR32;
|
---|
| 2252 | #pragma pack()
|
---|
[1] | 2253 |
|
---|
[1283] | 2254 | #pragma pack(1)
|
---|
[7121] | 2255 | /**
|
---|
[1283] | 2256 | * 64-bit IDTR/GDTR.
|
---|
| 2257 | */
|
---|
| 2258 | typedef struct X86XDTR64
|
---|
| 2259 | {
|
---|
| 2260 | /** Size of the descriptor table. */
|
---|
| 2261 | uint16_t cb;
|
---|
| 2262 | /** Address of the descriptor table. */
|
---|
| 2263 | uint64_t uAddr;
|
---|
| 2264 | } X86XDTR64, *PX86XDTR64;
|
---|
| 2265 | #pragma pack()
|
---|
[1] | 2266 |
|
---|
| 2267 | /** @} */
|
---|
| 2268 |
|
---|
| 2269 | #endif
|
---|
| 2270 |
|
---|