[1] | 1 | /** @file
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| 2 | * SVM Structures and Definitions.
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| 3 | */
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| 4 |
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| 5 | /*
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[2981] | 6 | * Copyright (C) 2006-2007 innotek GmbH
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[1] | 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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[1] | 24 | */
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| 25 |
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[3632] | 26 | #ifndef ___VBox_svm_h
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| 27 | #define ___VBox_svm_h
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[1] | 28 |
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| 29 | #include <VBox/types.h>
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| 30 | #include <VBox/err.h>
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| 31 | #include <iprt/assert.h>
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| 32 | #include <iprt/asm.h>
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| 33 |
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| 34 | /** @defgroup grp_svm svm Types and Definitions
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| 35 | * @ingroup grp_hwaccm
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| 36 | * @{
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| 37 | */
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| 38 |
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| 39 |
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| 40 | /** @name SVM Basic Exit Reasons.
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| 41 | * @{
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| 42 | */
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| 43 | /** Invalid guest state in VMCB. */
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| 44 | #define SVM_EXIT_INVALID -1
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| 45 | /** Read from CR0-CR15. */
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| 46 | #define SVM_EXIT_READ_CR0 0x0
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| 47 | #define SVM_EXIT_READ_CR1 0x1
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| 48 | #define SVM_EXIT_READ_CR2 0x2
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| 49 | #define SVM_EXIT_READ_CR3 0x3
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| 50 | #define SVM_EXIT_READ_CR4 0x4
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| 51 | #define SVM_EXIT_READ_CR5 0x5
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| 52 | #define SVM_EXIT_READ_CR6 0x6
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| 53 | #define SVM_EXIT_READ_CR7 0x7
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| 54 | #define SVM_EXIT_READ_CR8 0x8
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| 55 | #define SVM_EXIT_READ_CR9 0x9
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| 56 | #define SVM_EXIT_READ_CR10 0xA
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| 57 | #define SVM_EXIT_READ_CR11 0xB
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| 58 | #define SVM_EXIT_READ_CR12 0xC
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| 59 | #define SVM_EXIT_READ_CR13 0xD
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| 60 | #define SVM_EXIT_READ_CR14 0xE
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| 61 | #define SVM_EXIT_READ_CR15 0xF
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| 62 | /** Writes to CR0-CR15. */
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| 63 | #define SVM_EXIT_WRITE_CR0 0x10
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| 64 | #define SVM_EXIT_WRITE_CR1 0x11
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| 65 | #define SVM_EXIT_WRITE_CR2 0x12
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| 66 | #define SVM_EXIT_WRITE_CR3 0x13
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| 67 | #define SVM_EXIT_WRITE_CR4 0x14
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| 68 | #define SVM_EXIT_WRITE_CR5 0x15
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| 69 | #define SVM_EXIT_WRITE_CR6 0x16
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| 70 | #define SVM_EXIT_WRITE_CR7 0x17
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| 71 | #define SVM_EXIT_WRITE_CR8 0x18
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| 72 | #define SVM_EXIT_WRITE_CR9 0x19
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| 73 | #define SVM_EXIT_WRITE_CR10 0x1A
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| 74 | #define SVM_EXIT_WRITE_CR11 0x1B
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| 75 | #define SVM_EXIT_WRITE_CR12 0x1C
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| 76 | #define SVM_EXIT_WRITE_CR13 0x1D
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| 77 | #define SVM_EXIT_WRITE_CR14 0x1E
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| 78 | #define SVM_EXIT_WRITE_CR15 0x1F
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| 79 | /** Read from DR0-DR15. */
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| 80 | #define SVM_EXIT_READ_DR0 0x20
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| 81 | #define SVM_EXIT_READ_DR1 0x21
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| 82 | #define SVM_EXIT_READ_DR2 0x22
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| 83 | #define SVM_EXIT_READ_DR3 0x23
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| 84 | #define SVM_EXIT_READ_DR4 0x24
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| 85 | #define SVM_EXIT_READ_DR5 0x25
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| 86 | #define SVM_EXIT_READ_DR6 0x26
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| 87 | #define SVM_EXIT_READ_DR7 0x27
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| 88 | #define SVM_EXIT_READ_DR8 0x28
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| 89 | #define SVM_EXIT_READ_DR9 0x29
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| 90 | #define SVM_EXIT_READ_DR10 0x2A
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| 91 | #define SVM_EXIT_READ_DR11 0x2B
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| 92 | #define SVM_EXIT_READ_DR12 0x2C
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| 93 | #define SVM_EXIT_READ_DR13 0x2D
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| 94 | #define SVM_EXIT_READ_DR14 0x2E
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| 95 | #define SVM_EXIT_READ_DR15 0x2F
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| 96 | /** Writes to DR0-DR15. */
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| 97 | #define SVM_EXIT_WRITE_DR0 0x30
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| 98 | #define SVM_EXIT_WRITE_DR1 0x31
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| 99 | #define SVM_EXIT_WRITE_DR2 0x32
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| 100 | #define SVM_EXIT_WRITE_DR3 0x33
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| 101 | #define SVM_EXIT_WRITE_DR4 0x34
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| 102 | #define SVM_EXIT_WRITE_DR5 0x35
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| 103 | #define SVM_EXIT_WRITE_DR6 0x36
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| 104 | #define SVM_EXIT_WRITE_DR7 0x37
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| 105 | #define SVM_EXIT_WRITE_DR8 0x38
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| 106 | #define SVM_EXIT_WRITE_DR9 0x39
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| 107 | #define SVM_EXIT_WRITE_DR10 0x3A
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| 108 | #define SVM_EXIT_WRITE_DR11 0x3B
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| 109 | #define SVM_EXIT_WRITE_DR12 0x3C
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| 110 | #define SVM_EXIT_WRITE_DR13 0x3D
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| 111 | #define SVM_EXIT_WRITE_DR14 0x3E
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| 112 | #define SVM_EXIT_WRITE_DR15 0x3F
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| 113 | /* Exception 0-31. */
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| 114 | #define SVM_EXIT_EXCEPTION_0 0x40
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| 115 | #define SVM_EXIT_EXCEPTION_1 0x41
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| 116 | #define SVM_EXIT_EXCEPTION_2 0x42
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| 117 | #define SVM_EXIT_EXCEPTION_3 0x43
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| 118 | #define SVM_EXIT_EXCEPTION_4 0x44
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| 119 | #define SVM_EXIT_EXCEPTION_5 0x45
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| 120 | #define SVM_EXIT_EXCEPTION_6 0x46
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| 121 | #define SVM_EXIT_EXCEPTION_7 0x47
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| 122 | #define SVM_EXIT_EXCEPTION_8 0x48
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| 123 | #define SVM_EXIT_EXCEPTION_9 0x49
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| 124 | #define SVM_EXIT_EXCEPTION_A 0x4A
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| 125 | #define SVM_EXIT_EXCEPTION_B 0x4B
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| 126 | #define SVM_EXIT_EXCEPTION_C 0x4C
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| 127 | #define SVM_EXIT_EXCEPTION_D 0x4D
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| 128 | #define SVM_EXIT_EXCEPTION_E 0x4E
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| 129 | #define SVM_EXIT_EXCEPTION_F 0x4F
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| 130 | #define SVM_EXIT_EXCEPTION_10 0x50
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| 131 | #define SVM_EXIT_EXCEPTION_11 0x51
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| 132 | #define SVM_EXIT_EXCEPTION_12 0x52
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| 133 | #define SVM_EXIT_EXCEPTION_13 0x53
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| 134 | #define SVM_EXIT_EXCEPTION_14 0x54
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| 135 | #define SVM_EXIT_EXCEPTION_15 0x55
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| 136 | #define SVM_EXIT_EXCEPTION_16 0x56
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| 137 | #define SVM_EXIT_EXCEPTION_17 0x57
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| 138 | #define SVM_EXIT_EXCEPTION_18 0x58
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| 139 | #define SVM_EXIT_EXCEPTION_19 0x59
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| 140 | #define SVM_EXIT_EXCEPTION_1A 0x5A
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| 141 | #define SVM_EXIT_EXCEPTION_1B 0x5B
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| 142 | #define SVM_EXIT_EXCEPTION_1C 0x5C
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| 143 | #define SVM_EXIT_EXCEPTION_1D 0x5D
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| 144 | #define SVM_EXIT_EXCEPTION_1E 0x5E
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| 145 | #define SVM_EXIT_EXCEPTION_1F 0x5F
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| 146 | /** Physical maskable interrupt. */
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| 147 | #define SVM_EXIT_INTR 0x60
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| 148 | /** Non-maskable interrupt. */
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| 149 | #define SVM_EXIT_NMI 0x61
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| 150 | /** System Management interrupt. */
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| 151 | #define SVM_EXIT_SMI 0x62
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| 152 | /** Physical INIT signal. */
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| 153 | #define SVM_EXIT_INIT 0x63
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| 154 | /** Virtual interrupt. */
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| 155 | #define SVM_EXIT_VINTR 0x64
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| 156 | /** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
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| 157 | #define SVM_EXIT_CR0_SEL_WRITE 0x65
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| 158 | /** IDTR read. */
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| 159 | #define SVM_EXIT_IDTR_READ 0x66
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| 160 | /** GDTR read. */
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| 161 | #define SVM_EXIT_GDTR_READ 0x67
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| 162 | /** LDTR read. */
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| 163 | #define SVM_EXIT_LDTR_READ 0x68
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| 164 | /** TR read. */
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| 165 | #define SVM_EXIT_TR_READ 0x69
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| 166 | /** IDTR write. */
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| 167 | #define SVM_EXIT_IDTR_WRITE 0x6A
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| 168 | /** GDTR write. */
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| 169 | #define SVM_EXIT_GDTR_WRITE 0x6B
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| 170 | /** LDTR write. */
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| 171 | #define SVM_EXIT_LDTR_WRITE 0x6C
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| 172 | /** TR write. */
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| 173 | #define SVM_EXIT_TR_WRITE 0x6D
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| 174 | /** RDTSC instruction. */
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| 175 | #define SVM_EXIT_RDTSC 0x6E
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| 176 | /** RDPMC instruction. */
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| 177 | #define SVM_EXIT_RDPMC 0x6F
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| 178 | /** PUSHF instruction. */
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| 179 | #define SVM_EXIT_PUSHF 0x70
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| 180 | /** POPF instruction. */
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| 181 | #define SVM_EXIT_POPF 0x71
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| 182 | /** CPUID instruction. */
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| 183 | #define SVM_EXIT_CPUID 0x72
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| 184 | /** RSM instruction. */
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| 185 | #define SVM_EXIT_RSM 0x73
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| 186 | /** IRET instruction. */
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| 187 | #define SVM_EXIT_IRET 0x74
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| 188 | /** software interrupt (INTn instructions). */
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| 189 | #define SVM_EXIT_SWINT 0x75
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| 190 | /** INVD instruction. */
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| 191 | #define SVM_EXIT_INVD 0x76
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| 192 | /** PAUSE instruction. */
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| 193 | #define SVM_EXIT_PAUSE 0x77
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| 194 | /** HLT instruction. */
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| 195 | #define SVM_EXIT_HLT 0x78
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| 196 | /** INVLPG instructions. */
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| 197 | #define SVM_EXIT_INVLPG 0x79
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| 198 | /** INVLPGA instruction. */
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| 199 | #define SVM_EXIT_INVLPGA 0x7A
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| 200 | /** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
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| 201 | #define SVM_EXIT_IOIO 0x7B
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| 202 | /** RDMSR or WRMSR access to protected MSR. */
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| 203 | #define SVM_EXIT_MSR 0x7C
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| 204 | /** task switch. */
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| 205 | #define SVM_EXIT_TASK_SWITCH 0x7D
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| 206 | /** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
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| 207 | #define SVM_EXIT_FERR_FREEZE 0x7E
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| 208 | /** Shutdown. */
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| 209 | #define SVM_EXIT_SHUTDOWN 0x7F
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| 210 | /** VMRUN instruction. */
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| 211 | #define SVM_EXIT_VMRUN 0x80
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| 212 | /** VMMCALL instruction. */
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| 213 | #define SVM_EXIT_VMMCALL 0x81
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| 214 | /** VMLOAD instruction. */
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| 215 | #define SVM_EXIT_VMLOAD 0x82
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| 216 | /** VMSAVE instruction. */
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| 217 | #define SVM_EXIT_VMSAVE 0x83
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| 218 | /** STGI instruction. */
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| 219 | #define SVM_EXIT_STGI 0x84
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| 220 | /** CLGI instruction. */
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| 221 | #define SVM_EXIT_CLGI 0x85
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| 222 | /** SKINIT instruction. */
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| 223 | #define SVM_EXIT_SKINIT 0x86
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| 224 | /** RDTSCP instruction. */
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| 225 | #define SVM_EXIT_RDTSCP 0x87
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| 226 | /** ICEBP instruction. */
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| 227 | #define SVM_EXIT_ICEBP 0x88
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| 228 | /** WBINVD instruction. */
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| 229 | #define SVM_INVD 0x89
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| 230 | /** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
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| 231 | #define SVM_EXIT_NPF 0x400
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| 232 |
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| 233 | /** @} */
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| 234 |
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| 235 |
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| 236 | /** @name SVM_VMCB.ctrl.u32InterceptCtrl1
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| 237 | * @{
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| 238 | */
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| 239 | /* 0 Intercept INTR (physical maskable interrupt) */
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[5605] | 240 | #define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
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[1] | 241 | /* 1 Intercept NMI */
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[5605] | 242 | #define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
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[1] | 243 | /* 2 Intercept SMI */
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[5605] | 244 | #define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
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[1] | 245 | /* 3 Intercept INIT */
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[5605] | 246 | #define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
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[1] | 247 | /* 4 Intercept VINTR (virtual maskable interrupt) */
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[5605] | 248 | #define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
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[1] | 249 | /* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
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[5605] | 250 | #define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
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[1] | 251 | /* 6 Intercept reads of IDTR */
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[5605] | 252 | #define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
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[1] | 253 | /* 7 Intercept reads of GDTR */
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[5605] | 254 | #define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
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[1] | 255 | /* 8 Intercept reads of LDTR */
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[5605] | 256 | #define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
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[1] | 257 | /* 9 Intercept reads of TR */
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[5605] | 258 | #define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
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[1] | 259 | /* 10 Intercept writes of IDTR */
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[5605] | 260 | #define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
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[1] | 261 | /* 11 Intercept writes of GDTR */
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[5605] | 262 | #define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
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[1] | 263 | /* 12 Intercept writes of LDTR */
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[5605] | 264 | #define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
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[1] | 265 | /* 13 Intercept writes of TR */
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[5605] | 266 | #define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
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[1] | 267 | /* 14 Intercept RDTSC instruction */
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[5605] | 268 | #define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
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[1] | 269 | /* 15 Intercept RDPMC instruction */
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[5605] | 270 | #define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
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[1] | 271 | /* 16 Intercept PUSHF instruction */
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[5605] | 272 | #define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
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[1] | 273 | /* 17 Intercept POPF instruction */
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[5605] | 274 | #define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
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[1] | 275 | /* 18 Intercept CPUID instruction */
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[5605] | 276 | #define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
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[1] | 277 | /* 19 Intercept RSM instruction */
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[5605] | 278 | #define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
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[1] | 279 | /* 20 Intercept IRET instruction */
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[5605] | 280 | #define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
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[1] | 281 | /* 21 Intercept INTn instruction */
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[5605] | 282 | #define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
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[1] | 283 | /* 22 Intercept INVD instruction */
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[5605] | 284 | #define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
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[1] | 285 | /* 23 Intercept PAUSE instruction */
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[5605] | 286 | #define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
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[1] | 287 | /* 24 Intercept HLT instruction */
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[5605] | 288 | #define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
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[1] | 289 | /* 25 Intercept INVLPG instruction */
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[5605] | 290 | #define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
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[1] | 291 | /* 26 Intercept INVLPGA instruction */
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[5605] | 292 | #define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
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[1] | 293 | /* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
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[5605] | 294 | #define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
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[1] | 295 | /* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
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[5605] | 296 | #define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
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[1] | 297 | /* 29 Intercept task switches. */
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[5605] | 298 | #define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
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[1] | 299 | /* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
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[5605] | 300 | #define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
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[1] | 301 | /* 31 Intercept shutdown events. */
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[5605] | 302 | #define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
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[1] | 303 | /** @} */
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| 304 |
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| 305 |
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| 306 | /** @name SVM_VMCB.ctrl.u32InterceptCtrl2
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| 307 | * @{
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| 308 | */
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| 309 | /* 0 Intercept VMRUN instruction */
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[5605] | 310 | #define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
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[1] | 311 | /* 1 Intercept VMMCALL instruction */
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[5605] | 312 | #define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
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[1] | 313 | /* 2 Intercept VMLOAD instruction */
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[5605] | 314 | #define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
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[1] | 315 | /* 3 Intercept VMSAVE instruction */
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[5605] | 316 | #define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
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[1] | 317 | /* 4 Intercept STGI instruction */
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[5605] | 318 | #define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
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[1] | 319 | /* 5 Intercept CLGI instruction */
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[5605] | 320 | #define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
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[1] | 321 | /* 6 Intercept SKINIT instruction */
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[5605] | 322 | #define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
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[1] | 323 | /* 7 Intercept RDTSCP instruction */
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[5605] | 324 | #define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
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[1] | 325 | /* 8 Intercept ICEBP instruction */
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[5605] | 326 | #define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
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[1] | 327 | /* 9 Intercept WBINVD instruction */
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[5605] | 328 | #define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
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[1] | 329 | /** @} */
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| 330 |
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| 331 | /** @name SVM_VMCB.ctrl.u64NestedPaging
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| 332 | * @{
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| 333 | */
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[5605] | 334 | #define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
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[1] | 335 | /** @} */
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| 336 |
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| 337 | /** @name SVM_VMCB.ctrl.u64IntShadow
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| 338 | * @{
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| 339 | */
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[5605] | 340 | #define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
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[1] | 341 | /** @} */
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| 342 |
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| 343 |
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| 344 | /** @name SVM_INTCTRL.u3Type
|
---|
| 345 | * @{
|
---|
| 346 | */
|
---|
| 347 | /** External or virtual interrupt. */
|
---|
| 348 | #define SVM_EVENT_EXTERNAL_IRQ 0
|
---|
| 349 | /** Non-maskable interrupt. */
|
---|
| 350 | #define SVM_EVENT_NMI 1
|
---|
| 351 | /** Exception; fault or trap. */
|
---|
| 352 | #define SVM_EVENT_EXCEPTION 3
|
---|
| 353 | /** Software interrupt. */
|
---|
| 354 | #define SVM_EVENT_SOFTWARE_INT 4
|
---|
| 355 | /** @} */
|
---|
| 356 |
|
---|
| 357 |
|
---|
| 358 |
|
---|
| 359 |
|
---|
| 360 | /**
|
---|
| 361 | * SVM Selector type; includes hidden parts
|
---|
| 362 | */
|
---|
| 363 | #pragma pack(1)
|
---|
| 364 | typedef struct
|
---|
| 365 | {
|
---|
| 366 | uint16_t u16Sel;
|
---|
| 367 | uint16_t u16Attr;
|
---|
| 368 | uint32_t u32Limit;
|
---|
| 369 | uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
|
---|
| 370 | } SVMSEL;
|
---|
| 371 | #pragma pack()
|
---|
| 372 |
|
---|
| 373 | /**
|
---|
| 374 | * SVM GDTR/IDTR type
|
---|
| 375 | */
|
---|
| 376 | #pragma pack(1)
|
---|
| 377 | typedef struct
|
---|
| 378 | {
|
---|
| 379 | uint16_t u16Reserved1;
|
---|
| 380 | uint16_t u16Reserved2;
|
---|
| 381 | uint32_t u32Limit; /* Only lower 16 bits are implemented. */
|
---|
| 382 | uint64_t u64Base;
|
---|
| 383 | } SVMGDTR;
|
---|
| 384 | #pragma pack()
|
---|
| 385 |
|
---|
| 386 | typedef SVMGDTR SVMIDTR;
|
---|
| 387 |
|
---|
| 388 | /**
|
---|
| 389 | * SVM Event injection structure
|
---|
| 390 | */
|
---|
| 391 | #pragma pack(1)
|
---|
| 392 | typedef union
|
---|
| 393 | {
|
---|
| 394 | struct
|
---|
| 395 | {
|
---|
| 396 | uint32_t u8Vector : 8;
|
---|
| 397 | uint32_t u3Type : 3;
|
---|
| 398 | uint32_t u1ErrorCodeValid : 1;
|
---|
| 399 | uint32_t u19Reserved : 19;
|
---|
| 400 | uint32_t u1Valid : 1;
|
---|
[6243] | 401 | uint32_t u32ErrorCode : 32;
|
---|
[1] | 402 | } n;
|
---|
| 403 | uint64_t au64[1];
|
---|
| 404 | } SVM_EVENT;
|
---|
| 405 | #pragma pack()
|
---|
| 406 |
|
---|
| 407 |
|
---|
| 408 | /**
|
---|
| 409 | * SVM Interrupt control structure
|
---|
| 410 | */
|
---|
| 411 | #pragma pack(1)
|
---|
| 412 | typedef union
|
---|
| 413 | {
|
---|
| 414 | struct
|
---|
| 415 | {
|
---|
| 416 | uint32_t u8VTPR : 8;
|
---|
| 417 | uint32_t u1VIrqValid : 1;
|
---|
| 418 | uint32_t u7Reserved : 7;
|
---|
| 419 | uint32_t u4VIrqPriority : 4;
|
---|
| 420 | uint32_t u1IgnoreTPR : 1;
|
---|
| 421 | uint32_t u3Reserved : 3;
|
---|
| 422 | uint32_t u1VIrqMasking : 1;
|
---|
| 423 | uint32_t u7Reserved2 : 7;
|
---|
| 424 | uint32_t u8VIrqVector : 8;
|
---|
| 425 | uint32_t u24Reserved : 24;
|
---|
| 426 | } n;
|
---|
| 427 | uint64_t au64[1];
|
---|
| 428 | } SVM_INTCTRL;
|
---|
| 429 | #pragma pack()
|
---|
| 430 |
|
---|
| 431 |
|
---|
| 432 | /**
|
---|
| 433 | * SVM TLB control structure
|
---|
| 434 | */
|
---|
| 435 | #pragma pack(1)
|
---|
| 436 | typedef union
|
---|
| 437 | {
|
---|
| 438 | struct
|
---|
| 439 | {
|
---|
| 440 | uint32_t u32ASID : 32;
|
---|
| 441 | uint32_t u1TLBFlush : 1;
|
---|
| 442 | uint32_t u7Reserved : 7;
|
---|
| 443 | uint32_t u24Reserved : 24;
|
---|
| 444 | } n;
|
---|
| 445 | uint64_t au64[1];
|
---|
| 446 | } SVM_TLBCTRL;
|
---|
| 447 | #pragma pack()
|
---|
| 448 |
|
---|
| 449 |
|
---|
| 450 | /**
|
---|
| 451 | * SVM IOIO exit structure
|
---|
| 452 | */
|
---|
| 453 | #pragma pack(1)
|
---|
| 454 | typedef union
|
---|
| 455 | {
|
---|
| 456 | struct
|
---|
| 457 | {
|
---|
| 458 | uint32_t u1Type : 1; /* 0 = out, 1 = in */
|
---|
| 459 | uint32_t u1Reserved : 1;
|
---|
| 460 | uint32_t u1STR : 1;
|
---|
| 461 | uint32_t u1REP : 1;
|
---|
| 462 | uint32_t u1OP8 : 1;
|
---|
| 463 | uint32_t u1OP16 : 1;
|
---|
| 464 | uint32_t u1OP32 : 1;
|
---|
| 465 | uint32_t u1ADDR16 : 1;
|
---|
| 466 | uint32_t u1ADDR32 : 1;
|
---|
| 467 | uint32_t u1ADDR64 : 1;
|
---|
| 468 | uint32_t u6Reserved : 6;
|
---|
| 469 | uint32_t u16Port : 16;
|
---|
| 470 | } n;
|
---|
| 471 | uint32_t au32[1];
|
---|
| 472 | } SVM_IOIO_EXIT;
|
---|
| 473 | #pragma pack()
|
---|
| 474 |
|
---|
| 475 |
|
---|
| 476 | /**
|
---|
| 477 | * SVM VM Control Block. (VMCB)
|
---|
| 478 | */
|
---|
| 479 | #pragma pack(1)
|
---|
| 480 | typedef struct _SVM_VMCB
|
---|
| 481 | {
|
---|
| 482 | /** Control Area. */
|
---|
| 483 | struct
|
---|
| 484 | {
|
---|
| 485 | /** Offset 0x00 - Intercept reads of CR0-15. */
|
---|
| 486 | uint16_t u16InterceptRdCRx;
|
---|
| 487 | /** Offset 0x02 - Intercept writes to CR0-15. */
|
---|
| 488 | uint16_t u16InterceptWrCRx;
|
---|
| 489 | /** Offset 0x04 - Intercept reads of DR0-15. */
|
---|
| 490 | uint16_t u16InterceptRdDRx;
|
---|
| 491 | /** Offset 0x06 - Intercept writes to DR0-15. */
|
---|
| 492 | uint16_t u16InterceptWrDRx;
|
---|
| 493 | /** Offset 0x08 - Intercept exception vectors 0-31. */
|
---|
| 494 | uint32_t u32InterceptException;
|
---|
| 495 | /** Offset 0x0C - Intercept control field 1. */
|
---|
| 496 | uint32_t u32InterceptCtrl1;
|
---|
| 497 | /** Offset 0x0C - Intercept control field 2. */
|
---|
| 498 | uint32_t u32InterceptCtrl2;
|
---|
| 499 | /** Offset 0x14-0x3F - Reserved. */
|
---|
| 500 | uint8_t u8Reserved[0x40-0x14];
|
---|
| 501 | /** Offset 0x40 - Physical address of IOPM. */
|
---|
| 502 | uint64_t u64IOPMPhysAddr;
|
---|
| 503 | /** Offset 0x48 - Physical address of MSRPM. */
|
---|
| 504 | uint64_t u64MSRPMPhysAddr;
|
---|
| 505 | /** Offset 0x50 - TSC Offset. */
|
---|
| 506 | uint64_t u64TSCOffset;
|
---|
| 507 | /** Offset 0x58 - TLB control field. */
|
---|
| 508 | SVM_TLBCTRL TLBCtrl;
|
---|
| 509 | /** Offset 0x60 - Interrupt control field. */
|
---|
| 510 | SVM_INTCTRL IntCtrl;
|
---|
| 511 | /** Offset 0x68 - Interrupt shadow. */
|
---|
| 512 | uint64_t u64IntShadow;
|
---|
| 513 | /** Offset 0x70 - Exit code. */
|
---|
| 514 | uint64_t u64ExitCode;
|
---|
| 515 | /** Offset 0x78 - Exit info 1. */
|
---|
| 516 | uint64_t u64ExitInfo1;
|
---|
| 517 | /** Offset 0x80 - Exit info 2. */
|
---|
| 518 | uint64_t u64ExitInfo2;
|
---|
| 519 | /** Offset 0x88 - Exit Interrupt info. */
|
---|
| 520 | SVM_EVENT ExitIntInfo;
|
---|
| 521 | /** Offset 0x90 - Nested Paging. */
|
---|
| 522 | uint64_t u64NestedPaging;
|
---|
| 523 | /** Offset 0x98-0xA7 - Reserved. */
|
---|
| 524 | uint8_t u8Reserved2[0xA8-0x98];
|
---|
| 525 | /** Offset 0xA8 - Event injection. */
|
---|
| 526 | SVM_EVENT EventInject;
|
---|
| 527 | /** Offset 0xB0 - Host CR3 for nested paging. */
|
---|
| 528 | uint64_t u64HostCR3;
|
---|
| 529 | /** Offset 0xB8 - LBR Virtualization. */
|
---|
| 530 | uint64_t u64LBRVirt;
|
---|
| 531 | } ctrl;
|
---|
| 532 |
|
---|
| 533 | /** Offset 0xC0-0x3FF - Reserved. */
|
---|
| 534 | uint8_t u8Reserved3[0x400-0xC0];
|
---|
| 535 |
|
---|
| 536 | /* State Save Area. Starts at offset 0x400. */
|
---|
| 537 | struct
|
---|
| 538 | {
|
---|
| 539 | /** Offset 0x400 - Guest ES register + hidden parts. */
|
---|
| 540 | SVMSEL ES;
|
---|
| 541 | /** Offset 0x410 - Guest CS register + hidden parts. */
|
---|
| 542 | SVMSEL CS;
|
---|
| 543 | /** Offset 0x420 - Guest SS register + hidden parts. */
|
---|
| 544 | SVMSEL SS;
|
---|
| 545 | /** Offset 0x430 - Guest DS register + hidden parts. */
|
---|
| 546 | SVMSEL DS;
|
---|
| 547 | /** Offset 0x440 - Guest FS register + hidden parts. */
|
---|
| 548 | SVMSEL FS;
|
---|
| 549 | /** Offset 0x450 - Guest GS register + hidden parts. */
|
---|
| 550 | SVMSEL GS;
|
---|
| 551 | /** Offset 0x460 - Guest GDTR register. */
|
---|
| 552 | SVMGDTR GDTR;
|
---|
| 553 | /** Offset 0x470 - Guest LDTR register + hidden parts. */
|
---|
| 554 | SVMSEL LDTR;
|
---|
| 555 | /** Offset 0x480 - Guest IDTR register. */
|
---|
| 556 | SVMIDTR IDTR;
|
---|
| 557 | /** Offset 0x490 - Guest TR register + hidden parts. */
|
---|
| 558 | SVMSEL TR;
|
---|
| 559 | /** Offset 0x4A0-0x4CA - Reserved. */
|
---|
| 560 | uint8_t u8Reserved4[0x4CB-0x4A0];
|
---|
| 561 | /** Offset 0x4CB - CPL. */
|
---|
| 562 | uint8_t u8CPL;
|
---|
| 563 | /** Offset 0x4CC-0x4CF - Reserved. */
|
---|
| 564 | uint8_t u8Reserved5[0x4D0-0x4CC];
|
---|
| 565 | /** Offset 0x4D0 - EFER. */
|
---|
| 566 | uint64_t u64EFER;
|
---|
| 567 | /** Offset 0x4D8-0x547 - Reserved. */
|
---|
| 568 | uint8_t u8Reserved6[0x548-0x4D8];
|
---|
| 569 | /** Offset 0x548 - CR4. */
|
---|
| 570 | uint64_t u64CR4;
|
---|
| 571 | /** Offset 0x550 - CR3. */
|
---|
| 572 | uint64_t u64CR3;
|
---|
| 573 | /** Offset 0x558 - CR0. */
|
---|
| 574 | uint64_t u64CR0;
|
---|
| 575 | /** Offset 0x560 - DR7. */
|
---|
| 576 | uint64_t u64DR7;
|
---|
| 577 | /** Offset 0x568 - DR6. */
|
---|
| 578 | uint64_t u64DR6;
|
---|
| 579 | /** Offset 0x570 - RFLAGS. */
|
---|
| 580 | uint64_t u64RFlags;
|
---|
| 581 | /** Offset 0x578 - RIP. */
|
---|
| 582 | uint64_t u64RIP;
|
---|
| 583 | /** Offset 0x580-0x5D7 - Reserved. */
|
---|
| 584 | uint8_t u8Reserved7[0x5D8-0x580];
|
---|
| 585 | /** Offset 0x5D8 - RSP. */
|
---|
| 586 | uint64_t u64RSP;
|
---|
| 587 | /** Offset 0x5E0-0x5F7 - Reserved. */
|
---|
| 588 | uint8_t u8Reserved8[0x5F8-0x5E0];
|
---|
| 589 | /** Offset 0x5F8 - RAX. */
|
---|
| 590 | uint64_t u64RAX;
|
---|
| 591 | /** Offset 0x600 - STAR. */
|
---|
| 592 | uint64_t u64STAR;
|
---|
| 593 | /** Offset 0x608 - LSTAR. */
|
---|
| 594 | uint64_t u64LSTAR;
|
---|
| 595 | /** Offset 0x610 - CSTAR. */
|
---|
| 596 | uint64_t u64CSTAR;
|
---|
| 597 | /** Offset 0x618 - SFMASK. */
|
---|
| 598 | uint64_t u64SFMASK;
|
---|
| 599 | /** Offset 0x620 - KernelGSBase. */
|
---|
| 600 | uint64_t u64KernelGSBase;
|
---|
| 601 | /** Offset 0x628 - SYSENTER_CS. */
|
---|
| 602 | uint64_t u64SysEnterCS;
|
---|
| 603 | /** Offset 0x630 - SYSENTER_ESP. */
|
---|
| 604 | uint64_t u64SysEnterESP;
|
---|
| 605 | /** Offset 0x638 - SYSENTER_EIP. */
|
---|
| 606 | uint64_t u64SysEnterEIP;
|
---|
| 607 | /** Offset 0x640 - CR2. */
|
---|
| 608 | uint64_t u64CR2;
|
---|
| 609 | /** Offset 0x648-0x667 - Reserved. */
|
---|
| 610 | uint8_t u8Reserved9[0x668-0x648];
|
---|
| 611 | /** Offset 0x668 - G_PAT. */
|
---|
| 612 | uint64_t u64GPAT;
|
---|
| 613 | /** Offset 0x670 - DBGCTL. */
|
---|
| 614 | uint64_t u64DBGCTL;
|
---|
| 615 | /** Offset 0x678 - BR_FROM. */
|
---|
| 616 | uint64_t u64BR_FROM;
|
---|
| 617 | /** Offset 0x680 - BR_TO. */
|
---|
| 618 | uint64_t u64BR_TO;
|
---|
| 619 | /** Offset 0x688 - LASTEXCPFROM. */
|
---|
| 620 | uint64_t u64LASTEXCPFROM;
|
---|
| 621 | /** Offset 0x690 - LASTEXCPTO. */
|
---|
| 622 | uint64_t u64LASTEXCPTO;
|
---|
| 623 | } guest;
|
---|
| 624 |
|
---|
| 625 | /** Offset 0x698-0xFFF- Reserved. */
|
---|
| 626 | uint8_t u8Reserved10[0x1000-0x698];
|
---|
| 627 | } SVM_VMCB;
|
---|
| 628 | #pragma pack()
|
---|
| 629 |
|
---|
| 630 |
|
---|
| 631 | /**
|
---|
[6243] | 632 | * Prepares for and executes VMRUN.
|
---|
[1] | 633 | *
|
---|
[6243] | 634 | * @returns VBox status code.
|
---|
| 635 | * @param pVMCBHostPhys Physical address of host VMCB.
|
---|
| 636 | * @param pVMCBPhys Physical address of the VMCB.
|
---|
| 637 | * @param pCtx Guest context.
|
---|
[1] | 638 | */
|
---|
| 639 | DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
|
---|
| 640 |
|
---|
| 641 | /**
|
---|
[6243] | 642 | * Executes INVLPGA.
|
---|
[1] | 643 | *
|
---|
[6243] | 644 | * @param pPageGC Virtual page to invalidate.
|
---|
| 645 | * @param u32ASID Tagged TLB id.
|
---|
[1] | 646 | */
|
---|
[6243] | 647 | DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
|
---|
[1] | 648 |
|
---|
| 649 | /** @} */
|
---|
| 650 |
|
---|
| 651 | #endif
|
---|
| 652 |
|
---|