VirtualBox

source: vbox/trunk/include/VBox/hwacc_svm.h@ 8155

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1/** @file
2 * SVM Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_svm_h
31#define ___VBox_svm_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_svm svm Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43
44/** @name SVM Basic Exit Reasons.
45 * @{
46 */
47/** Invalid guest state in VMCB. */
48#define SVM_EXIT_INVALID -1
49/** Read from CR0-CR15. */
50#define SVM_EXIT_READ_CR0 0x0
51#define SVM_EXIT_READ_CR1 0x1
52#define SVM_EXIT_READ_CR2 0x2
53#define SVM_EXIT_READ_CR3 0x3
54#define SVM_EXIT_READ_CR4 0x4
55#define SVM_EXIT_READ_CR5 0x5
56#define SVM_EXIT_READ_CR6 0x6
57#define SVM_EXIT_READ_CR7 0x7
58#define SVM_EXIT_READ_CR8 0x8
59#define SVM_EXIT_READ_CR9 0x9
60#define SVM_EXIT_READ_CR10 0xA
61#define SVM_EXIT_READ_CR11 0xB
62#define SVM_EXIT_READ_CR12 0xC
63#define SVM_EXIT_READ_CR13 0xD
64#define SVM_EXIT_READ_CR14 0xE
65#define SVM_EXIT_READ_CR15 0xF
66/** Writes to CR0-CR15. */
67#define SVM_EXIT_WRITE_CR0 0x10
68#define SVM_EXIT_WRITE_CR1 0x11
69#define SVM_EXIT_WRITE_CR2 0x12
70#define SVM_EXIT_WRITE_CR3 0x13
71#define SVM_EXIT_WRITE_CR4 0x14
72#define SVM_EXIT_WRITE_CR5 0x15
73#define SVM_EXIT_WRITE_CR6 0x16
74#define SVM_EXIT_WRITE_CR7 0x17
75#define SVM_EXIT_WRITE_CR8 0x18
76#define SVM_EXIT_WRITE_CR9 0x19
77#define SVM_EXIT_WRITE_CR10 0x1A
78#define SVM_EXIT_WRITE_CR11 0x1B
79#define SVM_EXIT_WRITE_CR12 0x1C
80#define SVM_EXIT_WRITE_CR13 0x1D
81#define SVM_EXIT_WRITE_CR14 0x1E
82#define SVM_EXIT_WRITE_CR15 0x1F
83/** Read from DR0-DR15. */
84#define SVM_EXIT_READ_DR0 0x20
85#define SVM_EXIT_READ_DR1 0x21
86#define SVM_EXIT_READ_DR2 0x22
87#define SVM_EXIT_READ_DR3 0x23
88#define SVM_EXIT_READ_DR4 0x24
89#define SVM_EXIT_READ_DR5 0x25
90#define SVM_EXIT_READ_DR6 0x26
91#define SVM_EXIT_READ_DR7 0x27
92#define SVM_EXIT_READ_DR8 0x28
93#define SVM_EXIT_READ_DR9 0x29
94#define SVM_EXIT_READ_DR10 0x2A
95#define SVM_EXIT_READ_DR11 0x2B
96#define SVM_EXIT_READ_DR12 0x2C
97#define SVM_EXIT_READ_DR13 0x2D
98#define SVM_EXIT_READ_DR14 0x2E
99#define SVM_EXIT_READ_DR15 0x2F
100/** Writes to DR0-DR15. */
101#define SVM_EXIT_WRITE_DR0 0x30
102#define SVM_EXIT_WRITE_DR1 0x31
103#define SVM_EXIT_WRITE_DR2 0x32
104#define SVM_EXIT_WRITE_DR3 0x33
105#define SVM_EXIT_WRITE_DR4 0x34
106#define SVM_EXIT_WRITE_DR5 0x35
107#define SVM_EXIT_WRITE_DR6 0x36
108#define SVM_EXIT_WRITE_DR7 0x37
109#define SVM_EXIT_WRITE_DR8 0x38
110#define SVM_EXIT_WRITE_DR9 0x39
111#define SVM_EXIT_WRITE_DR10 0x3A
112#define SVM_EXIT_WRITE_DR11 0x3B
113#define SVM_EXIT_WRITE_DR12 0x3C
114#define SVM_EXIT_WRITE_DR13 0x3D
115#define SVM_EXIT_WRITE_DR14 0x3E
116#define SVM_EXIT_WRITE_DR15 0x3F
117/* Exception 0-31. */
118#define SVM_EXIT_EXCEPTION_0 0x40
119#define SVM_EXIT_EXCEPTION_1 0x41
120#define SVM_EXIT_EXCEPTION_2 0x42
121#define SVM_EXIT_EXCEPTION_3 0x43
122#define SVM_EXIT_EXCEPTION_4 0x44
123#define SVM_EXIT_EXCEPTION_5 0x45
124#define SVM_EXIT_EXCEPTION_6 0x46
125#define SVM_EXIT_EXCEPTION_7 0x47
126#define SVM_EXIT_EXCEPTION_8 0x48
127#define SVM_EXIT_EXCEPTION_9 0x49
128#define SVM_EXIT_EXCEPTION_A 0x4A
129#define SVM_EXIT_EXCEPTION_B 0x4B
130#define SVM_EXIT_EXCEPTION_C 0x4C
131#define SVM_EXIT_EXCEPTION_D 0x4D
132#define SVM_EXIT_EXCEPTION_E 0x4E
133#define SVM_EXIT_EXCEPTION_F 0x4F
134#define SVM_EXIT_EXCEPTION_10 0x50
135#define SVM_EXIT_EXCEPTION_11 0x51
136#define SVM_EXIT_EXCEPTION_12 0x52
137#define SVM_EXIT_EXCEPTION_13 0x53
138#define SVM_EXIT_EXCEPTION_14 0x54
139#define SVM_EXIT_EXCEPTION_15 0x55
140#define SVM_EXIT_EXCEPTION_16 0x56
141#define SVM_EXIT_EXCEPTION_17 0x57
142#define SVM_EXIT_EXCEPTION_18 0x58
143#define SVM_EXIT_EXCEPTION_19 0x59
144#define SVM_EXIT_EXCEPTION_1A 0x5A
145#define SVM_EXIT_EXCEPTION_1B 0x5B
146#define SVM_EXIT_EXCEPTION_1C 0x5C
147#define SVM_EXIT_EXCEPTION_1D 0x5D
148#define SVM_EXIT_EXCEPTION_1E 0x5E
149#define SVM_EXIT_EXCEPTION_1F 0x5F
150/** Physical maskable interrupt. */
151#define SVM_EXIT_INTR 0x60
152/** Non-maskable interrupt. */
153#define SVM_EXIT_NMI 0x61
154/** System Management interrupt. */
155#define SVM_EXIT_SMI 0x62
156/** Physical INIT signal. */
157#define SVM_EXIT_INIT 0x63
158/** Virtual interrupt. */
159#define SVM_EXIT_VINTR 0x64
160/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
161#define SVM_EXIT_CR0_SEL_WRITE 0x65
162/** IDTR read. */
163#define SVM_EXIT_IDTR_READ 0x66
164/** GDTR read. */
165#define SVM_EXIT_GDTR_READ 0x67
166/** LDTR read. */
167#define SVM_EXIT_LDTR_READ 0x68
168/** TR read. */
169#define SVM_EXIT_TR_READ 0x69
170/** IDTR write. */
171#define SVM_EXIT_IDTR_WRITE 0x6A
172/** GDTR write. */
173#define SVM_EXIT_GDTR_WRITE 0x6B
174/** LDTR write. */
175#define SVM_EXIT_LDTR_WRITE 0x6C
176/** TR write. */
177#define SVM_EXIT_TR_WRITE 0x6D
178/** RDTSC instruction. */
179#define SVM_EXIT_RDTSC 0x6E
180/** RDPMC instruction. */
181#define SVM_EXIT_RDPMC 0x6F
182/** PUSHF instruction. */
183#define SVM_EXIT_PUSHF 0x70
184/** POPF instruction. */
185#define SVM_EXIT_POPF 0x71
186/** CPUID instruction. */
187#define SVM_EXIT_CPUID 0x72
188/** RSM instruction. */
189#define SVM_EXIT_RSM 0x73
190/** IRET instruction. */
191#define SVM_EXIT_IRET 0x74
192/** software interrupt (INTn instructions). */
193#define SVM_EXIT_SWINT 0x75
194/** INVD instruction. */
195#define SVM_EXIT_INVD 0x76
196/** PAUSE instruction. */
197#define SVM_EXIT_PAUSE 0x77
198/** HLT instruction. */
199#define SVM_EXIT_HLT 0x78
200/** INVLPG instructions. */
201#define SVM_EXIT_INVLPG 0x79
202/** INVLPGA instruction. */
203#define SVM_EXIT_INVLPGA 0x7A
204/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
205#define SVM_EXIT_IOIO 0x7B
206/** RDMSR or WRMSR access to protected MSR. */
207#define SVM_EXIT_MSR 0x7C
208/** task switch. */
209#define SVM_EXIT_TASK_SWITCH 0x7D
210/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
211#define SVM_EXIT_FERR_FREEZE 0x7E
212/** Shutdown. */
213#define SVM_EXIT_SHUTDOWN 0x7F
214/** VMRUN instruction. */
215#define SVM_EXIT_VMRUN 0x80
216/** VMMCALL instruction. */
217#define SVM_EXIT_VMMCALL 0x81
218/** VMLOAD instruction. */
219#define SVM_EXIT_VMLOAD 0x82
220/** VMSAVE instruction. */
221#define SVM_EXIT_VMSAVE 0x83
222/** STGI instruction. */
223#define SVM_EXIT_STGI 0x84
224/** CLGI instruction. */
225#define SVM_EXIT_CLGI 0x85
226/** SKINIT instruction. */
227#define SVM_EXIT_SKINIT 0x86
228/** RDTSCP instruction. */
229#define SVM_EXIT_RDTSCP 0x87
230/** ICEBP instruction. */
231#define SVM_EXIT_ICEBP 0x88
232/** WBINVD instruction. */
233#define SVM_INVD 0x89
234/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault.). */
235#define SVM_EXIT_NPF 0x400
236
237/** @} */
238
239
240/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
241 * @{
242 */
243/* 0 Intercept INTR (physical maskable interrupt) */
244#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
245/* 1 Intercept NMI */
246#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
247/* 2 Intercept SMI */
248#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
249/* 3 Intercept INIT */
250#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
251/* 4 Intercept VINTR (virtual maskable interrupt) */
252#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
253/* 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
254#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
255/* 6 Intercept reads of IDTR */
256#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
257/* 7 Intercept reads of GDTR */
258#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
259/* 8 Intercept reads of LDTR */
260#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
261/* 9 Intercept reads of TR */
262#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
263/* 10 Intercept writes of IDTR */
264#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
265/* 11 Intercept writes of GDTR */
266#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
267/* 12 Intercept writes of LDTR */
268#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
269/* 13 Intercept writes of TR */
270#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
271/* 14 Intercept RDTSC instruction */
272#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
273/* 15 Intercept RDPMC instruction */
274#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
275/* 16 Intercept PUSHF instruction */
276#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
277/* 17 Intercept POPF instruction */
278#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
279/* 18 Intercept CPUID instruction */
280#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
281/* 19 Intercept RSM instruction */
282#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
283/* 20 Intercept IRET instruction */
284#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
285/* 21 Intercept INTn instruction */
286#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
287/* 22 Intercept INVD instruction */
288#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
289/* 23 Intercept PAUSE instruction */
290#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
291/* 24 Intercept HLT instruction */
292#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
293/* 25 Intercept INVLPG instruction */
294#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
295/* 26 Intercept INVLPGA instruction */
296#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
297/* 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
298#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
299/* 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
300#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
301/* 29 Intercept task switches. */
302#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
303/* 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
304#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
305/* 31 Intercept shutdown events. */
306#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
307/** @} */
308
309
310/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
311 * @{
312 */
313/* 0 Intercept VMRUN instruction */
314#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
315/* 1 Intercept VMMCALL instruction */
316#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
317/* 2 Intercept VMLOAD instruction */
318#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
319/* 3 Intercept VMSAVE instruction */
320#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
321/* 4 Intercept STGI instruction */
322#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
323/* 5 Intercept CLGI instruction */
324#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
325/* 6 Intercept SKINIT instruction */
326#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
327/* 7 Intercept RDTSCP instruction */
328#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
329/* 8 Intercept ICEBP instruction */
330#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
331/* 9 Intercept WBINVD instruction */
332#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
333/** @} */
334
335/** @name SVM_VMCB.ctrl.u64NestedPaging
336 * @{
337 */
338#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
339/** @} */
340
341/** @name SVM_VMCB.ctrl.u64IntShadow
342 * @{
343 */
344#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
345/** @} */
346
347
348/** @name SVM_INTCTRL.u3Type
349 * @{
350 */
351/** External or virtual interrupt. */
352#define SVM_EVENT_EXTERNAL_IRQ 0
353/** Non-maskable interrupt. */
354#define SVM_EVENT_NMI 1
355/** Exception; fault or trap. */
356#define SVM_EVENT_EXCEPTION 3
357/** Software interrupt. */
358#define SVM_EVENT_SOFTWARE_INT 4
359/** @} */
360
361
362
363
364/**
365 * SVM Selector type; includes hidden parts
366 */
367#pragma pack(1)
368typedef struct
369{
370 uint16_t u16Sel;
371 uint16_t u16Attr;
372 uint32_t u32Limit;
373 uint64_t u64Base; /* Only lower 32 bits are implemented for CS, DS, ES & SS. */
374} SVMSEL;
375#pragma pack()
376
377/**
378 * SVM GDTR/IDTR type
379 */
380#pragma pack(1)
381typedef struct
382{
383 uint16_t u16Reserved1;
384 uint16_t u16Reserved2;
385 uint32_t u32Limit; /* Only lower 16 bits are implemented. */
386 uint64_t u64Base;
387} SVMGDTR;
388#pragma pack()
389
390typedef SVMGDTR SVMIDTR;
391
392/**
393 * SVM Event injection structure
394 */
395#pragma pack(1)
396typedef union
397{
398 struct
399 {
400 uint32_t u8Vector : 8;
401 uint32_t u3Type : 3;
402 uint32_t u1ErrorCodeValid : 1;
403 uint32_t u19Reserved : 19;
404 uint32_t u1Valid : 1;
405 uint32_t u32ErrorCode : 32;
406 } n;
407 uint64_t au64[1];
408} SVM_EVENT;
409#pragma pack()
410
411
412/**
413 * SVM Interrupt control structure
414 */
415#pragma pack(1)
416typedef union
417{
418 struct
419 {
420 uint32_t u8VTPR : 8;
421 uint32_t u1VIrqValid : 1;
422 uint32_t u7Reserved : 7;
423 uint32_t u4VIrqPriority : 4;
424 uint32_t u1IgnoreTPR : 1;
425 uint32_t u3Reserved : 3;
426 uint32_t u1VIrqMasking : 1;
427 uint32_t u7Reserved2 : 7;
428 uint32_t u8VIrqVector : 8;
429 uint32_t u24Reserved : 24;
430 } n;
431 uint64_t au64[1];
432} SVM_INTCTRL;
433#pragma pack()
434
435
436/**
437 * SVM TLB control structure
438 */
439#pragma pack(1)
440typedef union
441{
442 struct
443 {
444 uint32_t u32ASID : 32;
445 uint32_t u1TLBFlush : 1;
446 uint32_t u7Reserved : 7;
447 uint32_t u24Reserved : 24;
448 } n;
449 uint64_t au64[1];
450} SVM_TLBCTRL;
451#pragma pack()
452
453
454/**
455 * SVM IOIO exit structure
456 */
457#pragma pack(1)
458typedef union
459{
460 struct
461 {
462 uint32_t u1Type : 1; /* 0 = out, 1 = in */
463 uint32_t u1Reserved : 1;
464 uint32_t u1STR : 1;
465 uint32_t u1REP : 1;
466 uint32_t u1OP8 : 1;
467 uint32_t u1OP16 : 1;
468 uint32_t u1OP32 : 1;
469 uint32_t u1ADDR16 : 1;
470 uint32_t u1ADDR32 : 1;
471 uint32_t u1ADDR64 : 1;
472 uint32_t u6Reserved : 6;
473 uint32_t u16Port : 16;
474 } n;
475 uint32_t au32[1];
476} SVM_IOIO_EXIT;
477#pragma pack()
478
479
480/**
481 * SVM VM Control Block. (VMCB)
482 */
483#pragma pack(1)
484typedef struct _SVM_VMCB
485{
486 /** Control Area. */
487 struct
488 {
489 /** Offset 0x00 - Intercept reads of CR0-15. */
490 uint16_t u16InterceptRdCRx;
491 /** Offset 0x02 - Intercept writes to CR0-15. */
492 uint16_t u16InterceptWrCRx;
493 /** Offset 0x04 - Intercept reads of DR0-15. */
494 uint16_t u16InterceptRdDRx;
495 /** Offset 0x06 - Intercept writes to DR0-15. */
496 uint16_t u16InterceptWrDRx;
497 /** Offset 0x08 - Intercept exception vectors 0-31. */
498 uint32_t u32InterceptException;
499 /** Offset 0x0C - Intercept control field 1. */
500 uint32_t u32InterceptCtrl1;
501 /** Offset 0x0C - Intercept control field 2. */
502 uint32_t u32InterceptCtrl2;
503 /** Offset 0x14-0x3F - Reserved. */
504 uint8_t u8Reserved[0x40-0x14];
505 /** Offset 0x40 - Physical address of IOPM. */
506 uint64_t u64IOPMPhysAddr;
507 /** Offset 0x48 - Physical address of MSRPM. */
508 uint64_t u64MSRPMPhysAddr;
509 /** Offset 0x50 - TSC Offset. */
510 uint64_t u64TSCOffset;
511 /** Offset 0x58 - TLB control field. */
512 SVM_TLBCTRL TLBCtrl;
513 /** Offset 0x60 - Interrupt control field. */
514 SVM_INTCTRL IntCtrl;
515 /** Offset 0x68 - Interrupt shadow. */
516 uint64_t u64IntShadow;
517 /** Offset 0x70 - Exit code. */
518 uint64_t u64ExitCode;
519 /** Offset 0x78 - Exit info 1. */
520 uint64_t u64ExitInfo1;
521 /** Offset 0x80 - Exit info 2. */
522 uint64_t u64ExitInfo2;
523 /** Offset 0x88 - Exit Interrupt info. */
524 SVM_EVENT ExitIntInfo;
525 /** Offset 0x90 - Nested Paging. */
526 uint64_t u64NestedPaging;
527 /** Offset 0x98-0xA7 - Reserved. */
528 uint8_t u8Reserved2[0xA8-0x98];
529 /** Offset 0xA8 - Event injection. */
530 SVM_EVENT EventInject;
531 /** Offset 0xB0 - Host CR3 for nested paging. */
532 uint64_t u64HostCR3;
533 /** Offset 0xB8 - LBR Virtualization. */
534 uint64_t u64LBRVirt;
535 } ctrl;
536
537 /** Offset 0xC0-0x3FF - Reserved. */
538 uint8_t u8Reserved3[0x400-0xC0];
539
540 /* State Save Area. Starts at offset 0x400. */
541 struct
542 {
543 /** Offset 0x400 - Guest ES register + hidden parts. */
544 SVMSEL ES;
545 /** Offset 0x410 - Guest CS register + hidden parts. */
546 SVMSEL CS;
547 /** Offset 0x420 - Guest SS register + hidden parts. */
548 SVMSEL SS;
549 /** Offset 0x430 - Guest DS register + hidden parts. */
550 SVMSEL DS;
551 /** Offset 0x440 - Guest FS register + hidden parts. */
552 SVMSEL FS;
553 /** Offset 0x450 - Guest GS register + hidden parts. */
554 SVMSEL GS;
555 /** Offset 0x460 - Guest GDTR register. */
556 SVMGDTR GDTR;
557 /** Offset 0x470 - Guest LDTR register + hidden parts. */
558 SVMSEL LDTR;
559 /** Offset 0x480 - Guest IDTR register. */
560 SVMIDTR IDTR;
561 /** Offset 0x490 - Guest TR register + hidden parts. */
562 SVMSEL TR;
563 /** Offset 0x4A0-0x4CA - Reserved. */
564 uint8_t u8Reserved4[0x4CB-0x4A0];
565 /** Offset 0x4CB - CPL. */
566 uint8_t u8CPL;
567 /** Offset 0x4CC-0x4CF - Reserved. */
568 uint8_t u8Reserved5[0x4D0-0x4CC];
569 /** Offset 0x4D0 - EFER. */
570 uint64_t u64EFER;
571 /** Offset 0x4D8-0x547 - Reserved. */
572 uint8_t u8Reserved6[0x548-0x4D8];
573 /** Offset 0x548 - CR4. */
574 uint64_t u64CR4;
575 /** Offset 0x550 - CR3. */
576 uint64_t u64CR3;
577 /** Offset 0x558 - CR0. */
578 uint64_t u64CR0;
579 /** Offset 0x560 - DR7. */
580 uint64_t u64DR7;
581 /** Offset 0x568 - DR6. */
582 uint64_t u64DR6;
583 /** Offset 0x570 - RFLAGS. */
584 uint64_t u64RFlags;
585 /** Offset 0x578 - RIP. */
586 uint64_t u64RIP;
587 /** Offset 0x580-0x5D7 - Reserved. */
588 uint8_t u8Reserved7[0x5D8-0x580];
589 /** Offset 0x5D8 - RSP. */
590 uint64_t u64RSP;
591 /** Offset 0x5E0-0x5F7 - Reserved. */
592 uint8_t u8Reserved8[0x5F8-0x5E0];
593 /** Offset 0x5F8 - RAX. */
594 uint64_t u64RAX;
595 /** Offset 0x600 - STAR. */
596 uint64_t u64STAR;
597 /** Offset 0x608 - LSTAR. */
598 uint64_t u64LSTAR;
599 /** Offset 0x610 - CSTAR. */
600 uint64_t u64CSTAR;
601 /** Offset 0x618 - SFMASK. */
602 uint64_t u64SFMASK;
603 /** Offset 0x620 - KernelGSBase. */
604 uint64_t u64KernelGSBase;
605 /** Offset 0x628 - SYSENTER_CS. */
606 uint64_t u64SysEnterCS;
607 /** Offset 0x630 - SYSENTER_ESP. */
608 uint64_t u64SysEnterESP;
609 /** Offset 0x638 - SYSENTER_EIP. */
610 uint64_t u64SysEnterEIP;
611 /** Offset 0x640 - CR2. */
612 uint64_t u64CR2;
613 /** Offset 0x648-0x667 - Reserved. */
614 uint8_t u8Reserved9[0x668-0x648];
615 /** Offset 0x668 - G_PAT. */
616 uint64_t u64GPAT;
617 /** Offset 0x670 - DBGCTL. */
618 uint64_t u64DBGCTL;
619 /** Offset 0x678 - BR_FROM. */
620 uint64_t u64BR_FROM;
621 /** Offset 0x680 - BR_TO. */
622 uint64_t u64BR_TO;
623 /** Offset 0x688 - LASTEXCPFROM. */
624 uint64_t u64LASTEXCPFROM;
625 /** Offset 0x690 - LASTEXCPTO. */
626 uint64_t u64LASTEXCPTO;
627 } guest;
628
629 /** Offset 0x698-0xFFF- Reserved. */
630 uint8_t u8Reserved10[0x1000-0x698];
631} SVM_VMCB;
632#pragma pack()
633
634
635/**
636 * Prepares for and executes VMRUN.
637 *
638 * @returns VBox status code.
639 * @param pVMCBHostPhys Physical address of host VMCB.
640 * @param pVMCBPhys Physical address of the VMCB.
641 * @param pCtx Guest context.
642 */
643DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
644
645/**
646 * Executes INVLPGA.
647 *
648 * @param pPageGC Virtual page to invalidate.
649 * @param u32ASID Tagged TLB id.
650 */
651DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
652
653/** @} */
654
655#endif
656
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