VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 8142

Last change on this file since 8142 was 8142, checked in by vboxsync, 16 years ago

Some updates for 64 bits disassembly
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 21.1 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disasm_h
27#define ___VBox_disasm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/disopcode.h>
32
33#if defined(__L4ENV__)
34#include <setjmp.h>
35#endif
36
37__BEGIN_DECLS
38
39
40/** CPU mode flags (DISCPUSTATE::mode).
41 * @{
42 */
43typedef enum
44{
45 CPUMODE_16BIT = 1,
46 CPUMODE_32BIT = 2,
47 CPUMODE_64BIT = 3,
48 /** hack forcing the size of the enum to 32-bits. */
49 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
50} DISCPUMODE;
51/** @} */
52
53/** Prefix byte flags
54 * @{
55 */
56#define PREFIX_NONE 0
57/** non-default address size. */
58#define PREFIX_ADDRSIZE 1
59/** non-default operand size. */
60#define PREFIX_OPSIZE 2
61/** lock prefix. */
62#define PREFIX_LOCK 4
63/** segment prefix. */
64#define PREFIX_SEG 8
65/** rep(e) prefix (not a prefix, but we'll treat is as one). */
66#define PREFIX_REP 16
67/** rep(e) prefix (not a prefix, but we'll treat is as one). */
68#define PREFIX_REPNE 32
69/** REX prefix (64 bits) */
70#define PREFIX_REX 64
71/** @} */
72
73/** 64 bits prefix byte flags
74 * @{
75 */
76#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_REX)
77#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_REX)
78#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_REX_B)
79#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_REX_X)
80#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_REX_XB)
81#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_REX_R)
82#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_REX_RB)
83#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_REX_RX)
84#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_REX_RXB)
85#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_REX_W)
86#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_REX_WB)
87#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_REX_WX)
88#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_REX_WXB)
89#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_REX_WR)
90#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_REX_WRB)
91#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_REX_WRX)
92#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_REX_WRXB)
93/** @} */
94
95/**
96 * Operand type.
97 */
98#define OPTYPE_INVALID RT_BIT(0)
99#define OPTYPE_HARMLESS RT_BIT(1)
100#define OPTYPE_CONTROLFLOW RT_BIT(2)
101#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
102#define OPTYPE_DANGEROUS RT_BIT(4)
103#define OPTYPE_PORTIO RT_BIT(5)
104#define OPTYPE_PRIVILEGED RT_BIT(6)
105#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
106#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
107#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
108#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
109#define OPTYPE_INTERRUPT RT_BIT(11)
110#define OPTYPE_ILLEGAL RT_BIT(12)
111#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
112#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
113#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
114#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
115#define OPTYPE_PORTIO_READ RT_BIT(17)
116#define OPTYPE_PORTIO_WRITE RT_BIT(18)
117#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
118#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
119#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
120#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
121#define OPTYPE_ALL (0xffffffff)
122
123/** Parameter usage flags.
124 * @{
125 */
126#define USE_BASE RT_BIT(0)
127#define USE_INDEX RT_BIT(1)
128#define USE_SCALE RT_BIT(2)
129#define USE_REG_GEN8 RT_BIT(3)
130#define USE_REG_GEN16 RT_BIT(4)
131#define USE_REG_GEN32 RT_BIT(5)
132#define USE_REG_FP RT_BIT(6)
133#define USE_REG_MMX RT_BIT(7)
134#define USE_REG_XMM RT_BIT(8)
135#define USE_REG_CR RT_BIT(9)
136#define USE_REG_DBG RT_BIT(10)
137#define USE_REG_SEG RT_BIT(11)
138#define USE_REG_TEST RT_BIT(12)
139#define USE_DISPLACEMENT8 RT_BIT(13)
140#define USE_DISPLACEMENT16 RT_BIT(14)
141#define USE_DISPLACEMENT32 RT_BIT(15)
142#define USE_IMMEDIATE8 RT_BIT(16)
143#define USE_IMMEDIATE8_REL RT_BIT(17)
144#define USE_IMMEDIATE16 RT_BIT(18)
145#define USE_IMMEDIATE16_REL RT_BIT(19)
146#define USE_IMMEDIATE32 RT_BIT(20)
147#define USE_IMMEDIATE32_REL RT_BIT(21)
148#define USE_IMMEDIATE64 RT_BIT(22)
149#define USE_IMMEDIATE_ADDR_0_32 RT_BIT(23)
150#define USE_IMMEDIATE_ADDR_16_32 RT_BIT(24)
151#define USE_IMMEDIATE_ADDR_0_16 RT_BIT(25)
152#define USE_IMMEDIATE_ADDR_16_16 RT_BIT(26)
153/** DS:ESI */
154#define USE_POINTER_DS_BASED RT_BIT(27)
155/** ES:EDI */
156#define USE_POINTER_ES_BASED RT_BIT(28)
157#define USE_IMMEDIATE16_SX8 RT_BIT(29)
158#define USE_IMMEDIATE32_SX8 RT_BIT(30)
159
160#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
161
162/** @} */
163
164/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
165 * @{
166 */
167#define USE_REG_RAX 0
168#define USE_REG_RCX 1
169#define USE_REG_RDX 2
170#define USE_REG_RBX 3
171#define USE_REG_RSP 4
172#define USE_REG_RBP 5
173#define USE_REG_RSI 6
174#define USE_REG_RDI 7
175#define USE_REG_R8 8
176#define USE_REG_R9 9
177#define USE_REG_R10 10
178#define USE_REG_R11 11
179#define USE_REG_R12 12
180#define USE_REG_R13 13
181#define USE_REG_R14 14
182#define USE_REG_R15 15
183/** @} */
184
185/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
186 * @{
187 */
188#define USE_REG_EAX 0
189#define USE_REG_ECX 1
190#define USE_REG_EDX 2
191#define USE_REG_EBX 3
192#define USE_REG_ESP 4
193#define USE_REG_EBP 5
194#define USE_REG_ESI 6
195#define USE_REG_EDI 7
196/** @} */
197/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
198 * @{
199 */
200#define USE_REG_AX 0
201#define USE_REG_CX 1
202#define USE_REG_DX 2
203#define USE_REG_BX 3
204#define USE_REG_SP 4
205#define USE_REG_BP 5
206#define USE_REG_SI 6
207#define USE_REG_DI 7
208/** @} */
209
210/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
211 * @{
212 */
213#define USE_REG_AL 0
214#define USE_REG_CL 1
215#define USE_REG_DL 2
216#define USE_REG_BL 3
217#define USE_REG_AH 4
218#define USE_REG_CH 5
219#define USE_REG_DH 6
220#define USE_REG_BH 7
221/** @} */
222
223/** index in {ES, CS, SS, DS, FS, GS}
224 * @{
225 */
226#define USE_REG_ES 0
227#define USE_REG_CS 1
228#define USE_REG_SS 2
229#define USE_REG_DS 3
230#define USE_REG_FS 4
231#define USE_REG_GS 5
232/** @} */
233
234#define USE_REG_FP0 0
235#define USE_REG_FP1 1
236#define USE_REG_FP2 2
237#define USE_REG_FP3 3
238#define USE_REG_FP4 4
239#define USE_REG_FP5 5
240#define USE_REG_FP6 6
241#define USE_REG_FP7 7
242
243#define USE_REG_CR0 0
244#define USE_REG_CR1 1
245#define USE_REG_CR2 2
246#define USE_REG_CR3 3
247#define USE_REG_CR4 4
248
249#define USE_REG_DR0 0
250#define USE_REG_DR1 1
251#define USE_REG_DR2 2
252#define USE_REG_DR3 3
253#define USE_REG_DR4 4
254#define USE_REG_DR5 5
255#define USE_REG_DR6 6
256#define USE_REG_DR7 7
257
258#define USE_REG_MMX0 0
259#define USE_REG_MMX1 1
260#define USE_REG_MMX2 2
261#define USE_REG_MMX3 3
262#define USE_REG_MMX4 4
263#define USE_REG_MMX5 5
264#define USE_REG_MMX6 6
265#define USE_REG_MMX7 7
266
267#define USE_REG_XMM0 0
268#define USE_REG_XMM1 1
269#define USE_REG_XMM2 2
270#define USE_REG_XMM3 3
271#define USE_REG_XMM4 4
272#define USE_REG_XMM5 5
273#define USE_REG_XMM6 6
274#define USE_REG_XMM7 7
275
276/** Used by DISQueryParamVal & EMIQueryParamVal
277 * @{
278 */
279#define PARAM_VAL8 RT_BIT(0)
280#define PARAM_VAL16 RT_BIT(1)
281#define PARAM_VAL32 RT_BIT(2)
282#define PARAM_VAL64 RT_BIT(3)
283#define PARAM_VALFARPTR16 RT_BIT(4)
284#define PARAM_VALFARPTR32 RT_BIT(5)
285
286#define PARMTYPE_REGISTER 1
287#define PARMTYPE_ADDRESS 2
288#define PARMTYPE_IMMEDIATE 3
289
290typedef struct
291{
292 uint32_t type;
293 uint32_t flags;
294 uint32_t size;
295
296 union
297 {
298 uint8_t val8;
299 uint16_t val16;
300 uint32_t val32;
301 uint64_t val64;
302
303 struct
304 {
305 uint16_t sel;
306 uint32_t offset;
307 } farptr;
308 } val;
309
310} OP_PARAMVAL;
311/** Pointer to opcode parameter value. */
312typedef OP_PARAMVAL *POP_PARAMVAL;
313
314typedef enum
315{
316 PARAM_DEST,
317 PARAM_SOURCE
318} PARAM_TYPE;
319
320/** @} */
321
322/**
323 * Operand Parameter.
324 */
325typedef struct _OP_PARAMETER
326{
327 int param;
328 uint64_t parval;
329 char szParam[32];
330
331 int32_t disp8, disp16, disp32;
332
333 uint32_t flags;
334
335 uint32_t size;
336
337 union
338 {
339 uint32_t reg_gen8;
340 uint32_t reg_gen16;
341 uint32_t reg_gen32;
342 /** ST(0) - ST(7) */
343 uint32_t reg_fp;
344 /** MMX0 - MMX7 */
345 uint32_t reg_mmx;
346 /** XMM0 - XMM7 */
347 uint32_t reg_xmm;
348 /** {ES, CS, SS, DS, FS, GS} */
349 uint32_t reg_seg;
350 /** TR0-TR7 (?) */
351 uint32_t reg_test;
352 /** CR0-CR4 */
353 uint32_t reg_ctrl;
354 /** DR0-DR7 */
355 uint32_t reg_dbg;
356 } base;
357 union
358 {
359 uint32_t reg_gen;
360 } index;
361
362 /** 2, 4 or 8. */
363 uint32_t scale;
364
365} OP_PARAMETER;
366/** Pointer to opcode parameter. */
367typedef OP_PARAMETER *POP_PARAMETER;
368/** Pointer to opcode parameter. */
369typedef const OP_PARAMETER *PCOP_PARAMETER;
370
371
372struct _OPCODE;
373/** Pointer to opcode. */
374typedef struct _OPCODE *POPCODE;
375/** Pointer to const opcode. */
376typedef const struct _OPCODE *PCOPCODE;
377
378typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, uint32_t size, void *pvUserdata);
379typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
380
381/* forward decl */
382struct _DISCPUSTATE;
383/** Pointer to the disassembler CPU state. */
384typedef struct _DISCPUSTATE *PDISCPUSTATE;
385
386/** Parser callback.
387 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
388typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
389typedef FNDISPARSE *PFNDISPARSE;
390
391typedef struct _DISCPUSTATE
392{
393 /* Global setting */
394 DISCPUMODE mode;
395
396 /* Per instruction prefix settings */
397 uint32_t prefix;
398 /** segment prefix value. */
399 uint32_t prefix_seg;
400 /** rex prefix value (64 bits only */
401 uint32_t prefix_rex;
402 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
403 DISCPUMODE addrmode;
404 /** operand mode (16 or 32 bits). (CPUMODE_*) */
405 DISCPUMODE opmode;
406
407 OP_PARAMETER param1;
408 OP_PARAMETER param2;
409 OP_PARAMETER param3;
410
411 /** ModRM byte. */
412 uint32_t ModRM;
413 /** scalar, index, base byte. */
414 uint32_t SIB;
415
416 int32_t disp;
417
418 /** First opcode byte of instruction. */
419 uint8_t opcode;
420 /** Last prefix byte (for SSE2 extension tables) */
421 uint8_t lastprefix;
422 RTUINTPTR opaddr;
423 uint32_t opsize;
424#ifndef DIS_CORE_ONLY
425 /** Opcode format string for current instruction. */
426 const char *pszOpcode;
427#endif
428
429 /** Internal: pointer to disassembly function table */
430 PFNDISPARSE *pfnDisasmFnTable;
431 /** Internal: instruction filter */
432 uint32_t uFilter;
433
434 /** Pointer to the current instruction. */
435 PCOPCODE pCurInstr;
436
437 void *apvUserData[3];
438
439 /** Optional read function */
440 PFN_DIS_READBYTES pfnReadBytes;
441#ifdef __L4ENV__
442 jmp_buf *pJumpBuffer;
443#endif /* __L4ENV__ */
444} DISCPUSTATE;
445
446/** Opcode. */
447#pragma pack(4)
448typedef struct _OPCODE
449{
450#ifndef DIS_CORE_ONLY
451 const char *pszOpcode;
452#endif
453 uint8_t idxParse1;
454 uint8_t idxParse2;
455 uint8_t idxParse3;
456 uint16_t opcode;
457 uint16_t param1;
458 uint16_t param2;
459 uint16_t param3;
460
461 uint32_t optype;
462} OPCODE;
463#pragma pack()
464
465
466/**
467 * Disassembles a code block.
468 *
469 * @returns VBox error code
470 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
471 * set correctly.
472 * @param pvCodeBlock Pointer to the strunction to disassemble.
473 * @param cbMax Maximum number of bytes to disassemble.
474 * @param pcbSize Where to store the size of the instruction.
475 * NULL is allowed.
476 *
477 *
478 * @todo Define output callback.
479 * @todo Using signed integers as sizes is a bit odd. There are still
480 * some GCC warnings about mixing signed and unsigend integers.
481 * @todo Need to extend this interface to include a code address so we
482 * can dissassemble GC code. Perhaps a new function is better...
483 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
484 * This means *pcbSize >= cbMax sometimes.
485 */
486DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
487
488/**
489 * Disassembles one instruction
490 *
491 * @returns VBox error code
492 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
493 * set correctly.
494 * @param pu8Instruction Pointer to the instrunction to disassemble.
495 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
496 * @param pcbSize Where to store the size of the instruction.
497 * NULL is allowed.
498 * @param pszOutput Storage for disassembled instruction
499 *
500 * @todo Define output callback.
501 */
502DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
503
504/**
505 * Disassembles one instruction
506 *
507 * @returns VBox error code
508 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
509 * set correctly.
510 * @param pu8Instruction Pointer to the strunction to disassemble.
511 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
512 * @param pcbSize Where to store the size of the instruction.
513 * NULL is allowed.
514 * @param pszOutput Storage for disassembled instruction
515 * @param uFilter Instruction type filter
516 *
517 * @todo Define output callback.
518 */
519DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
520 char *pszOutput, unsigned uFilter);
521
522/**
523 * Parses one instruction.
524 * The result is found in pCpu.
525 *
526 * @returns VBox error code
527 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
528 * @param InstructionAddr Pointer to the instruction to parse.
529 * @param pcbInstruction Where to store the size of the instruction.
530 * NULL is allowed.
531 */
532DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
533
534/**
535 * Parses one guest instruction.
536 * The result is found in pCpu and pcbInstruction.
537 *
538 * @returns VBox status code.
539 * @param InstructionAddr Address of the instruction to decode. What this means
540 * is left to the pfnReadBytes function.
541 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
542 * @param pfnReadBytes Callback for reading instruction bytes.
543 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
544 * @param pCpu Pointer to cpu structure. Will be initialized.
545 * @param pcbInstruction Where to store the size of the instruction.
546 * NULL is allowed.
547 */
548DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
549 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
550
551DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
552DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
553DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
554
555/**
556 * Returns the value of the parameter in pParam
557 *
558 * @returns VBox error code
559 * @param pCtx Exception structure pointer
560 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
561 * set correctly.
562 * @param pParam Pointer to the parameter to parse
563 * @param pParamVal Pointer to parameter value (OUT)
564 * @param parmtype Parameter type
565 *
566 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
567 *
568 */
569DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
570DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, uint32_t **ppReg, size_t *pcbSize);
571
572DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
573DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
574DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
575DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
576DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal);
577DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
578DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
579DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
580DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
581DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
582DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL val);
583DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
584DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
585DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
586DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
587
588__END_DECLS
589
590#endif
591
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