VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 8006

Last change on this file since 8006 was 7285, checked in by vboxsync, 16 years ago

added DISQueryParamRegPtr to return a pointer to a register which is modified by an interpreted instruction
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 19.8 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disasm_h
27#define ___VBox_disasm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/disopcode.h>
32
33#if defined(__L4ENV__)
34#include <setjmp.h>
35#endif
36
37__BEGIN_DECLS
38
39
40/** CPU mode flags (DISCPUSTATE::mode).
41 * @{
42 */
43typedef enum
44{
45 CPUMODE_16BIT = 1,
46 CPUMODE_32BIT = 2,
47 CPUMODE_64BIT = 3,
48 /** hack forcing the size of the enum to 32-bits. */
49 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
50} DISCPUMODE;
51/** @} */
52
53/** Prefix byte flags
54 * @{
55 */
56#define PREFIX_NONE 0
57/** non-default address size. */
58#define PREFIX_ADDRSIZE 1
59/** non-default operand size. */
60#define PREFIX_OPSIZE 2
61/** lock prefix. */
62#define PREFIX_LOCK 4
63/** segment prefix. */
64#define PREFIX_SEG 8
65/** rep(e) prefix (not a prefix, but we'll treat is as one). */
66#define PREFIX_REP 16
67/** rep(e) prefix (not a prefix, but we'll treat is as one). */
68#define PREFIX_REPNE 32
69/** REX prefix (64 bits) */
70#define PREFIX_REX 64
71/** @} */
72
73/** 64 bits prefix byte flags
74 * @{
75 */
76#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_REX)
77#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_REX)
78#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_REX_B)
79#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_REX_X)
80#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_REX_XB)
81#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_REX_R)
82#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_REX_RB)
83#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_REX_RX)
84#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_REX_RXB)
85#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_REX_W)
86#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_REX_WB)
87#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_REX_WX)
88#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_REX_WXB)
89#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_REX_WR)
90#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_REX_WRB)
91#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_REX_WRX)
92#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_REX_WRXB)
93/** @} */
94
95/**
96 * Operand type.
97 */
98#define OPTYPE_INVALID RT_BIT(0)
99#define OPTYPE_HARMLESS RT_BIT(1)
100#define OPTYPE_CONTROLFLOW RT_BIT(2)
101#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
102#define OPTYPE_DANGEROUS RT_BIT(4)
103#define OPTYPE_PORTIO RT_BIT(5)
104#define OPTYPE_PRIVILEGED RT_BIT(6)
105#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
106#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
107#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
108#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
109#define OPTYPE_INTERRUPT RT_BIT(11)
110#define OPTYPE_ILLEGAL RT_BIT(12)
111#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
112#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
113#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
114#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
115#define OPTYPE_PORTIO_READ RT_BIT(17)
116#define OPTYPE_PORTIO_WRITE RT_BIT(18)
117#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
118#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
119#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
120#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
121#define OPTYPE_ALL (0xffffffff)
122
123/** Parameter usage flags.
124 * @{
125 */
126#define USE_BASE RT_BIT(0)
127#define USE_INDEX RT_BIT(1)
128#define USE_SCALE RT_BIT(2)
129#define USE_REG_GEN8 RT_BIT(3)
130#define USE_REG_GEN16 RT_BIT(4)
131#define USE_REG_GEN32 RT_BIT(5)
132#define USE_REG_FP RT_BIT(6)
133#define USE_REG_MMX RT_BIT(7)
134#define USE_REG_XMM RT_BIT(8)
135#define USE_REG_CR RT_BIT(9)
136#define USE_REG_DBG RT_BIT(10)
137#define USE_REG_SEG RT_BIT(11)
138#define USE_REG_TEST RT_BIT(12)
139#define USE_DISPLACEMENT8 RT_BIT(13)
140#define USE_DISPLACEMENT16 RT_BIT(14)
141#define USE_DISPLACEMENT32 RT_BIT(15)
142#define USE_IMMEDIATE8 RT_BIT(16)
143#define USE_IMMEDIATE8_REL RT_BIT(17)
144#define USE_IMMEDIATE16 RT_BIT(18)
145#define USE_IMMEDIATE16_REL RT_BIT(19)
146#define USE_IMMEDIATE32 RT_BIT(20)
147#define USE_IMMEDIATE32_REL RT_BIT(21)
148#define USE_IMMEDIATE64 RT_BIT(22)
149#define USE_IMMEDIATE_ADDR_0_32 RT_BIT(23)
150#define USE_IMMEDIATE_ADDR_16_32 RT_BIT(24)
151#define USE_IMMEDIATE_ADDR_0_16 RT_BIT(25)
152#define USE_IMMEDIATE_ADDR_16_16 RT_BIT(26)
153/** DS:ESI */
154#define USE_POINTER_DS_BASED RT_BIT(27)
155/** ES:EDI */
156#define USE_POINTER_ES_BASED RT_BIT(28)
157#define USE_IMMEDIATE16_SX8 RT_BIT(29)
158#define USE_IMMEDIATE32_SX8 RT_BIT(30)
159
160#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
161
162/** @} */
163
164/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
165 * @{
166 */
167#define USE_REG_EAX 0
168#define USE_REG_ECX 1
169#define USE_REG_EDX 2
170#define USE_REG_EBX 3
171#define USE_REG_ESP 4
172#define USE_REG_EBP 5
173#define USE_REG_ESI 6
174#define USE_REG_EDI 7
175/** @} */
176/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
177 * @{
178 */
179#define USE_REG_AX 0
180#define USE_REG_CX 1
181#define USE_REG_DX 2
182#define USE_REG_BX 3
183#define USE_REG_SP 4
184#define USE_REG_BP 5
185#define USE_REG_SI 6
186#define USE_REG_DI 7
187/** @} */
188
189/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
190 * @{
191 */
192#define USE_REG_AL 0
193#define USE_REG_CL 1
194#define USE_REG_DL 2
195#define USE_REG_BL 3
196#define USE_REG_AH 4
197#define USE_REG_CH 5
198#define USE_REG_DH 6
199#define USE_REG_BH 7
200/** @} */
201
202/** index in {ES, CS, SS, DS, FS, GS}
203 * @{
204 */
205#define USE_REG_ES 0
206#define USE_REG_CS 1
207#define USE_REG_SS 2
208#define USE_REG_DS 3
209#define USE_REG_FS 4
210#define USE_REG_GS 5
211/** @} */
212
213#define USE_REG_FP0 0
214#define USE_REG_FP1 1
215#define USE_REG_FP2 2
216#define USE_REG_FP3 3
217#define USE_REG_FP4 4
218#define USE_REG_FP5 5
219#define USE_REG_FP6 6
220#define USE_REG_FP7 7
221
222#define USE_REG_CR0 0
223#define USE_REG_CR1 1
224#define USE_REG_CR2 2
225#define USE_REG_CR3 3
226#define USE_REG_CR4 4
227
228#define USE_REG_DR0 0
229#define USE_REG_DR1 1
230#define USE_REG_DR2 2
231#define USE_REG_DR3 3
232#define USE_REG_DR4 4
233#define USE_REG_DR5 5
234#define USE_REG_DR6 6
235#define USE_REG_DR7 7
236
237#define USE_REG_MMX0 0
238#define USE_REG_MMX1 1
239#define USE_REG_MMX2 2
240#define USE_REG_MMX3 3
241#define USE_REG_MMX4 4
242#define USE_REG_MMX5 5
243#define USE_REG_MMX6 6
244#define USE_REG_MMX7 7
245
246#define USE_REG_XMM0 0
247#define USE_REG_XMM1 1
248#define USE_REG_XMM2 2
249#define USE_REG_XMM3 3
250#define USE_REG_XMM4 4
251#define USE_REG_XMM5 5
252#define USE_REG_XMM6 6
253#define USE_REG_XMM7 7
254
255/** Used by DISQueryParamVal & EMIQueryParamVal
256 * @{
257 */
258#define PARAM_VAL8 RT_BIT(0)
259#define PARAM_VAL16 RT_BIT(1)
260#define PARAM_VAL32 RT_BIT(2)
261#define PARAM_VAL64 RT_BIT(3)
262#define PARAM_VALFARPTR16 RT_BIT(4)
263#define PARAM_VALFARPTR32 RT_BIT(5)
264
265#define PARMTYPE_REGISTER 1
266#define PARMTYPE_ADDRESS 2
267#define PARMTYPE_IMMEDIATE 3
268
269typedef struct
270{
271 uint32_t type;
272 uint32_t flags;
273 uint32_t size;
274
275 union
276 {
277 uint8_t val8;
278 uint16_t val16;
279 uint32_t val32;
280 uint64_t val64;
281
282 struct
283 {
284 uint16_t sel;
285 uint32_t offset;
286 } farptr;
287 } val;
288
289} OP_PARAMVAL;
290/** Pointer to opcode parameter value. */
291typedef OP_PARAMVAL *POP_PARAMVAL;
292
293typedef enum
294{
295 PARAM_DEST,
296 PARAM_SOURCE
297} PARAM_TYPE;
298
299/** @} */
300
301/**
302 * Operand Parameter.
303 */
304typedef struct _OP_PARAMETER
305{
306 int param;
307 uint64_t parval;
308 char szParam[32];
309
310 int32_t disp8, disp16, disp32;
311
312 uint32_t flags;
313
314 uint32_t size;
315
316 union
317 {
318 uint32_t reg_gen8;
319 uint32_t reg_gen16;
320 uint32_t reg_gen32;
321 /** ST(0) - ST(7) */
322 uint32_t reg_fp;
323 /** MMX0 - MMX7 */
324 uint32_t reg_mmx;
325 /** XMM0 - XMM7 */
326 uint32_t reg_xmm;
327 /** {ES, CS, SS, DS, FS, GS} */
328 uint32_t reg_seg;
329 /** TR0-TR7 (?) */
330 uint32_t reg_test;
331 /** CR0-CR4 */
332 uint32_t reg_ctrl;
333 /** DR0-DR7 */
334 uint32_t reg_dbg;
335 } base;
336 union
337 {
338 uint32_t reg_gen;
339 } index;
340
341 /** 2, 4 or 8. */
342 uint32_t scale;
343
344} OP_PARAMETER;
345/** Pointer to opcode parameter. */
346typedef OP_PARAMETER *POP_PARAMETER;
347/** Pointer to opcode parameter. */
348typedef const OP_PARAMETER *PCOP_PARAMETER;
349
350
351struct _OPCODE;
352/** Pointer to opcode. */
353typedef struct _OPCODE *POPCODE;
354/** Pointer to const opcode. */
355typedef const struct _OPCODE *PCOPCODE;
356
357typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, uint32_t size, void *pvUserdata);
358typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
359
360/* forward decl */
361struct _DISCPUSTATE;
362/** Pointer to the disassembler CPU state. */
363typedef struct _DISCPUSTATE *PDISCPUSTATE;
364
365/** Parser callback.
366 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
367typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
368typedef FNDISPARSE *PFNDISPARSE;
369
370typedef struct _DISCPUSTATE
371{
372 /* Global setting */
373 DISCPUMODE mode;
374
375 /* Per instruction prefix settings */
376 uint32_t prefix;
377 /** segment prefix value. */
378 uint32_t prefix_seg;
379 /** rex prefix value (64 bits only */
380 uint32_t prefix_rex;
381 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
382 DISCPUMODE addrmode;
383 /** operand mode (16 or 32 bits). (CPUMODE_*) */
384 DISCPUMODE opmode;
385
386 OP_PARAMETER param1;
387 OP_PARAMETER param2;
388 OP_PARAMETER param3;
389
390 /** ModRM byte. */
391 uint32_t ModRM;
392 /** scalar, index, base byte. */
393 uint32_t SIB;
394
395 int32_t disp;
396
397 /** First opcode byte of instruction. */
398 uint8_t opcode;
399 /** Last prefix byte (for SSE2 extension tables) */
400 uint8_t lastprefix;
401 RTUINTPTR opaddr;
402 uint32_t opsize;
403#ifndef DIS_CORE_ONLY
404 /** Opcode format string for current instruction. */
405 const char *pszOpcode;
406#endif
407
408 /** Internal: pointer to disassembly function table */
409 PFNDISPARSE *pfnDisasmFnTable;
410 /** Internal: instruction filter */
411 uint32_t uFilter;
412
413 /** Pointer to the current instruction. */
414 PCOPCODE pCurInstr;
415
416 void *apvUserData[3];
417
418 /** Optional read function */
419 PFN_DIS_READBYTES pfnReadBytes;
420#ifdef __L4ENV__
421 jmp_buf *pJumpBuffer;
422#endif /* __L4ENV__ */
423} DISCPUSTATE;
424
425/** Opcode. */
426#pragma pack(4)
427typedef struct _OPCODE
428{
429#ifndef DIS_CORE_ONLY
430 const char *pszOpcode;
431#endif
432 uint8_t idxParse1;
433 uint8_t idxParse2;
434 uint8_t idxParse3;
435 uint16_t opcode;
436 uint16_t param1;
437 uint16_t param2;
438 uint16_t param3;
439
440 uint32_t optype;
441} OPCODE;
442#pragma pack()
443
444
445/**
446 * Disassembles a code block.
447 *
448 * @returns VBox error code
449 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
450 * set correctly.
451 * @param pvCodeBlock Pointer to the strunction to disassemble.
452 * @param cbMax Maximum number of bytes to disassemble.
453 * @param pcbSize Where to store the size of the instruction.
454 * NULL is allowed.
455 *
456 *
457 * @todo Define output callback.
458 * @todo Using signed integers as sizes is a bit odd. There are still
459 * some GCC warnings about mixing signed and unsigend integers.
460 * @todo Need to extend this interface to include a code address so we
461 * can dissassemble GC code. Perhaps a new function is better...
462 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
463 * This means *pcbSize >= cbMax sometimes.
464 */
465DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
466
467/**
468 * Disassembles one instruction
469 *
470 * @returns VBox error code
471 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
472 * set correctly.
473 * @param pu8Instruction Pointer to the instrunction to disassemble.
474 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
475 * @param pcbSize Where to store the size of the instruction.
476 * NULL is allowed.
477 * @param pszOutput Storage for disassembled instruction
478 *
479 * @todo Define output callback.
480 */
481DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
482
483/**
484 * Disassembles one instruction
485 *
486 * @returns VBox error code
487 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
488 * set correctly.
489 * @param pu8Instruction Pointer to the strunction to disassemble.
490 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
491 * @param pcbSize Where to store the size of the instruction.
492 * NULL is allowed.
493 * @param pszOutput Storage for disassembled instruction
494 * @param uFilter Instruction type filter
495 *
496 * @todo Define output callback.
497 */
498DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
499 char *pszOutput, unsigned uFilter);
500
501/**
502 * Parses one instruction.
503 * The result is found in pCpu.
504 *
505 * @returns VBox error code
506 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
507 * @param InstructionAddr Pointer to the instruction to parse.
508 * @param pcbInstruction Where to store the size of the instruction.
509 * NULL is allowed.
510 */
511DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
512
513/**
514 * Parses one guest instruction.
515 * The result is found in pCpu and pcbInstruction.
516 *
517 * @returns VBox status code.
518 * @param InstructionAddr Address of the instruction to decode. What this means
519 * is left to the pfnReadBytes function.
520 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
521 * @param pfnReadBytes Callback for reading instruction bytes.
522 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
523 * @param pCpu Pointer to cpu structure. Will be initialized.
524 * @param pcbInstruction Where to store the size of the instruction.
525 * NULL is allowed.
526 */
527DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
528 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
529
530DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
531DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
532DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
533
534/**
535 * Returns the value of the parameter in pParam
536 *
537 * @returns VBox error code
538 * @param pCtx Exception structure pointer
539 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
540 * set correctly.
541 * @param pParam Pointer to the parameter to parse
542 * @param pParamVal Pointer to parameter value (OUT)
543 * @param parmtype Parameter type
544 *
545 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
546 *
547 */
548DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
549DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, uint32_t **ppReg, size_t *pcbSize);
550
551DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, uint32_t reg8, uint8_t *pVal);
552DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, uint32_t reg16, uint16_t *pVal);
553DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, uint32_t reg32, uint32_t *pVal);
554DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal);
555DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
556DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, uint32_t reg8, uint8_t val8);
557DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint16_t val16);
558DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint32_t val32);
559DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL val);
560
561__END_DECLS
562
563#endif
564
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