[1] | 1 | /** @file
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| 2 | * CPUM - CPU Monitor(/ Manager).
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| 3 | */
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| 4 |
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| 5 | /*
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[8155] | 6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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[1] | 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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[8155] | 24 | *
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| 25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 27 | * additional information or have any questions.
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[1] | 28 | */
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| 29 |
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[3632] | 30 | #ifndef ___VBox_cpum_h
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| 31 | #define ___VBox_cpum_h
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[1] | 32 |
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| 33 | #include <VBox/cdefs.h>
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| 34 | #include <VBox/types.h>
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| 35 | #include <VBox/x86.h>
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| 36 |
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| 37 |
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| 38 | __BEGIN_DECLS
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| 39 |
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| 40 | /** @defgroup grp_cpum The CPU Monitor(/Manager) API
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| 41 | * @{
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| 42 | */
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| 43 |
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| 44 | /**
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| 45 | * Selector hidden registers.
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| 46 | */
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[7133] | 47 | typedef struct CPUMSELREGHID
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[1] | 48 | {
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| 49 | /** Base register. */
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| 50 | uint32_t u32Base;
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| 51 | /** Limit (expanded). */
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| 52 | uint32_t u32Limit;
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| 53 | /** Flags.
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| 54 | * This is the high 32-bit word of the descriptor entry.
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| 55 | * Only the flags, dpl and type are used. */
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| 56 | X86DESCATTR Attr;
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| 57 | } CPUMSELREGHID;
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| 58 |
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| 59 |
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| 60 | /**
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| 61 | * The sysenter register set.
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| 62 | */
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| 63 | typedef struct CPUMSYSENTER
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| 64 | {
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| 65 | /** Ring 0 cs.
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| 66 | * This value + 8 is the Ring 0 ss.
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| 67 | * This value + 16 is the Ring 3 cs.
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| 68 | * This value + 24 is the Ring 3 ss.
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| 69 | */
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| 70 | uint64_t cs;
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| 71 | /** Ring 0 eip. */
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| 72 | uint64_t eip;
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| 73 | /** Ring 0 esp. */
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| 74 | uint64_t esp;
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| 75 | } CPUMSYSENTER;
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| 76 |
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| 77 |
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| 78 | /**
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| 79 | * CPU context core.
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| 80 | */
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| 81 | #pragma pack(1)
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| 82 | typedef struct CPUMCTXCORE
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| 83 | {
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[7095] | 84 | union
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| 85 | {
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| 86 | uint32_t edi;
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| 87 | uint64_t rdi;
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| 88 | };
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| 89 | union
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| 90 | {
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| 91 | uint32_t esi;
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| 92 | uint64_t rsi;
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| 93 | };
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| 94 | union
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| 95 | {
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| 96 | uint32_t ebp;
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| 97 | uint64_t rbp;
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| 98 | };
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| 99 | union
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| 100 | {
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| 101 | uint32_t eax;
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| 102 | uint64_t rax;
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| 103 | };
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| 104 | union
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| 105 | {
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| 106 | uint32_t ebx;
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| 107 | uint64_t rbx;
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| 108 | };
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| 109 | union
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| 110 | {
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| 111 | uint32_t edx;
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| 112 | uint64_t rdx;
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| 113 | };
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| 114 | union
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| 115 | {
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| 116 | uint32_t ecx;
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| 117 | uint64_t rcx;
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| 118 | };
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[7097] | 119 | /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
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| 120 | uint32_t esp;
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| 121 | RTSEL ss;
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| 122 | RTSEL ssPadding;
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| 123 | /* Note: no overlap with esp here. */
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| 124 | uint64_t rsp;
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[1] | 125 |
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| 126 | RTSEL gs;
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| 127 | RTSEL gsPadding;
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| 128 | RTSEL fs;
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| 129 | RTSEL fsPadding;
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| 130 | RTSEL es;
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| 131 | RTSEL esPadding;
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| 132 | RTSEL ds;
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| 133 | RTSEL dsPadding;
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| 134 | RTSEL cs;
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[7097] | 135 | RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
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[1] | 136 |
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[7095] | 137 | union
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| 138 | {
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| 139 | X86EFLAGS eflags;
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| 140 | X86RFLAGS rflags;
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| 141 | };
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| 142 | union
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| 143 | {
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| 144 | uint32_t eip;
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| 145 | uint64_t rip;
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| 146 | };
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[1] | 147 |
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[7095] | 148 | uint64_t r8;
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| 149 | uint64_t r9;
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| 150 | uint64_t r10;
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| 151 | uint64_t r11;
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| 152 | uint64_t r12;
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| 153 | uint64_t r13;
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| 154 | uint64_t r14;
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| 155 | uint64_t r15;
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| 156 |
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[1] | 157 | /** Hidden selector registers.
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| 158 | * @{ */
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| 159 | CPUMSELREGHID esHid;
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| 160 | CPUMSELREGHID csHid;
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| 161 | CPUMSELREGHID ssHid;
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| 162 | CPUMSELREGHID dsHid;
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| 163 | CPUMSELREGHID fsHid;
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| 164 | CPUMSELREGHID gsHid;
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| 165 | /** @} */
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| 166 |
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| 167 | } CPUMCTXCORE;
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| 168 | #pragma pack()
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| 169 |
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[7133] | 170 |
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[1] | 171 | /**
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| 172 | * CPU context.
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| 173 | */
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| 174 | #pragma pack(1)
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| 175 | typedef struct CPUMCTX
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| 176 | {
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| 177 | /** FPU state. (16-byte alignment)
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| 178 | * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
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| 179 | * actual format or convert it (waste of time). */
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| 180 | X86FXSTATE fpu;
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| 181 |
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| 182 | /** CPUMCTXCORE Part.
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| 183 | * @{ */
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[7095] | 184 | union
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| 185 | {
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| 186 | uint32_t edi;
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| 187 | uint64_t rdi;
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| 188 | };
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| 189 | union
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| 190 | {
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| 191 | uint32_t esi;
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| 192 | uint64_t rsi;
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| 193 | };
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| 194 | union
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| 195 | {
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| 196 | uint32_t ebp;
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| 197 | uint64_t rbp;
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| 198 | };
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| 199 | union
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| 200 | {
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| 201 | uint32_t eax;
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| 202 | uint64_t rax;
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| 203 | };
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| 204 | union
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| 205 | {
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| 206 | uint32_t ebx;
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| 207 | uint64_t rbx;
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| 208 | };
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| 209 | union
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| 210 | {
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| 211 | uint32_t edx;
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| 212 | uint64_t rdx;
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| 213 | };
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| 214 | union
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| 215 | {
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| 216 | uint32_t ecx;
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| 217 | uint64_t rcx;
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| 218 | };
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[7097] | 219 | /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
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| 220 | uint32_t esp;
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| 221 | RTSEL ss;
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| 222 | RTSEL ssPadding;
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| 223 | /* Note: no overlap with esp here. */
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| 224 | uint64_t rsp;
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[1] | 225 |
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| 226 | RTSEL gs;
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| 227 | RTSEL gsPadding;
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| 228 | RTSEL fs;
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| 229 | RTSEL fsPadding;
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| 230 | RTSEL es;
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| 231 | RTSEL esPadding;
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| 232 | RTSEL ds;
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| 233 | RTSEL dsPadding;
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| 234 | RTSEL cs;
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[7097] | 235 | RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
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[1] | 236 |
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[7095] | 237 | union
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| 238 | {
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| 239 | X86EFLAGS eflags;
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| 240 | X86RFLAGS rflags;
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| 241 | };
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| 242 | union
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| 243 | {
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| 244 | uint32_t eip;
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| 245 | uint64_t rip;
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| 246 | };
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[1] | 247 |
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[7095] | 248 | uint64_t r8;
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| 249 | uint64_t r9;
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| 250 | uint64_t r10;
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| 251 | uint64_t r11;
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| 252 | uint64_t r12;
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| 253 | uint64_t r13;
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| 254 | uint64_t r14;
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| 255 | uint64_t r15;
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| 256 |
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[1] | 257 | /** Hidden selector registers.
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| 258 | * @{ */
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| 259 | CPUMSELREGHID esHid;
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| 260 | CPUMSELREGHID csHid;
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| 261 | CPUMSELREGHID ssHid;
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| 262 | CPUMSELREGHID dsHid;
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| 263 | CPUMSELREGHID fsHid;
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| 264 | CPUMSELREGHID gsHid;
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| 265 | /** @} */
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| 266 |
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| 267 | /** @} */
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| 268 |
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| 269 | /** Control registers.
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| 270 | * @{ */
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[7095] | 271 | uint64_t cr0;
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| 272 | uint64_t cr2;
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| 273 | uint64_t cr3;
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| 274 | uint64_t cr4;
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| 275 | uint64_t cr8;
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[1] | 276 | /** @} */
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| 277 |
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| 278 | /** Debug registers.
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| 279 | * @{ */
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[7095] | 280 | uint64_t dr0;
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| 281 | uint64_t dr1;
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| 282 | uint64_t dr2;
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| 283 | uint64_t dr3;
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| 284 | uint64_t dr4; /**< @todo remove dr4 and dr5. */
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| 285 | uint64_t dr5;
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| 286 | uint64_t dr6;
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| 287 | uint64_t dr7;
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| 288 | /* DR8-15 are currently not supported */
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[1] | 289 | /** @} */
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| 290 |
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| 291 | /** Global Descriptor Table register. */
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| 292 | VBOXGDTR gdtr;
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| 293 | uint16_t gdtrPadding;
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| 294 | uint32_t gdtrPadding64;/** @todo fix this hack */
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| 295 | /** Interrupt Descriptor Table register. */
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| 296 | VBOXIDTR idtr;
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| 297 | uint16_t idtrPadding;
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| 298 | uint32_t idtrPadding64;/** @todo fix this hack */
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| 299 | /** The task register.
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| 300 | * Only the guest context uses all the members. */
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| 301 | RTSEL ldtr;
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| 302 | RTSEL ldtrPadding;
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| 303 | /** The task register.
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| 304 | * Only the guest context uses all the members. */
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| 305 | RTSEL tr;
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| 306 | RTSEL trPadding;
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| 307 |
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| 308 | /** The sysenter msr registers.
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| 309 | * This member is not used by the hypervisor context. */
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| 310 | CPUMSYSENTER SysEnter;
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| 311 |
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[7695] | 312 | /** System MSRs.
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| 313 | * @{ */
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| 314 | uint64_t msrEFER;
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| 315 | uint64_t msrSTAR;
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| 316 | uint64_t msrPAT;
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| 317 | uint64_t msrLSTAR;
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| 318 | uint64_t msrCSTAR;
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| 319 | uint64_t msrSFMASK;
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| 320 | uint64_t msrFSBASE;
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| 321 | uint64_t msrGSBASE;
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| 322 | uint64_t msrKERNELGSBASE;
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| 323 | /** @} */
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| 324 |
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[1] | 325 | /** Hidden selector registers.
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| 326 | * @{ */
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| 327 | CPUMSELREGHID ldtrHid;
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| 328 | CPUMSELREGHID trHid;
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| 329 | /** @} */
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| 330 |
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| 331 | /* padding to get 32byte aligned size */
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[7695] | 332 | uint32_t padding[2];
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[1] | 333 | } CPUMCTX;
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| 334 | #pragma pack()
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| 335 |
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| 336 | /**
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| 337 | * Gets the CPUMCTXCORE part of a CPUMCTX.
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| 338 | */
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| 339 | #define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
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| 340 |
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| 341 | /**
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| 342 | * The register set returned by a CPUID operation.
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| 343 | */
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| 344 | typedef struct CPUMCPUID
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| 345 | {
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| 346 | uint32_t eax;
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| 347 | uint32_t ebx;
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| 348 | uint32_t ecx;
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| 349 | uint32_t edx;
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| 350 | } CPUMCPUID;
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| 351 | /** Pointer to a CPUID leaf. */
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| 352 | typedef CPUMCPUID *PCPUMCPUID;
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| 353 | /** Pointer to a const CPUID leaf. */
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| 354 | typedef const CPUMCPUID *PCCPUMCPUID;
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| 355 |
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| 356 | /**
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| 357 | * CPUID feature to set or clear.
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| 358 | */
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| 359 | typedef enum CPUMCPUIDFEATURE
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| 360 | {
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| 361 | CPUMCPUIDFEATURE_INVALID = 0,
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| 362 | /** The APIC feature bit. (Std+Ext) */
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[770] | 363 | CPUMCPUIDFEATURE_APIC,
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| 364 | /** The sysenter/sysexit feature bit. (Std+Ext) */
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[7644] | 365 | CPUMCPUIDFEATURE_SEP,
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| 366 | /** The PAE feature bit. (Std+Ext) */
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[7645] | 367 | CPUMCPUIDFEATURE_PAE,
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| 368 | /** The LONG MODE feature bit. (Ext) */
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| 369 | CPUMCPUIDFEATURE_LONG_MODE
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[1] | 370 | } CPUMCPUIDFEATURE;
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| 371 |
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| 372 |
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| 373 | /** @name Guest Register Getters.
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| 374 | * @{ */
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| 375 | CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
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| 376 | CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
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| 377 | CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
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| 378 | CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
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| 379 | CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
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| 380 | CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
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| 381 | CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
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| 382 | CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
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| 383 | CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
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| 384 | CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
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| 385 | CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
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| 386 | CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
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| 387 | CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
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| 388 | CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
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| 389 | CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
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| 390 | CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
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| 391 | CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
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| 392 | CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
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| 393 | CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
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| 394 | CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
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| 395 | CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
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| 396 | CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
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| 397 | CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
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| 398 | CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
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| 399 | CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
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| 400 | CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
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| 401 | CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
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| 402 | CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
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| 403 | CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
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| 404 | CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
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| 405 | CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
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| 406 | CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
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| 407 | CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
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| 408 | CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
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| 409 | CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
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[5285] | 410 | CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
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[1] | 411 | CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
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| 412 | CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
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| 413 | CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
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[5285] | 414 | CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
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[1] | 415 | CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
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[7730] | 416 | CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
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[1] | 417 | /** @} */
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| 418 |
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| 419 | /** @name Guest Register Setters.
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| 420 | * @{ */
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| 421 | CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
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| 422 | CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
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| 423 | CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
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| 424 | CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
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| 425 | CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
|
---|
| 426 | CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
|
---|
| 427 | CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
|
---|
| 428 | CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
|
---|
| 429 | CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
|
---|
| 430 | CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
|
---|
| 431 | CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
|
---|
| 432 | CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
|
---|
| 433 | CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
|
---|
| 434 | CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
|
---|
| 435 | CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
|
---|
| 436 | CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
|
---|
| 437 | CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
|
---|
| 438 | CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
|
---|
| 439 | CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
|
---|
| 440 | CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
|
---|
| 441 | CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
|
---|
| 442 | CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
|
---|
| 443 | CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
|
---|
| 444 | CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
|
---|
| 445 | CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
|
---|
| 446 | CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
|
---|
| 447 | CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
|
---|
| 448 | CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
|
---|
| 449 | CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
|
---|
| 450 | CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
|
---|
| 451 | CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
|
---|
| 452 | CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
|
---|
[7730] | 453 | CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
|
---|
[1] | 454 | CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
|
---|
| 455 | CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
|
---|
[8111] | 456 | CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
|
---|
[1] | 457 | CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
|
---|
| 458 | /** @} */
|
---|
| 459 |
|
---|
| 460 | /** @name Misc Guest Predicate Functions.
|
---|
| 461 | * @{ */
|
---|
| 462 |
|
---|
| 463 | /**
|
---|
| 464 | * Tests if the guest is running in real mode or not.
|
---|
| 465 | *
|
---|
| 466 | * @returns true if in real mode, otherwise false.
|
---|
| 467 | * @param pVM The VM handle.
|
---|
| 468 | */
|
---|
| 469 | DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
|
---|
| 470 | {
|
---|
| 471 | return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
|
---|
| 472 | }
|
---|
| 473 |
|
---|
| 474 | /**
|
---|
| 475 | * Tests if the guest is running in protected or not.
|
---|
| 476 | *
|
---|
| 477 | * @returns true if in protected mode, otherwise false.
|
---|
| 478 | * @param pVM The VM handle.
|
---|
| 479 | */
|
---|
| 480 | DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
|
---|
| 481 | {
|
---|
| 482 | return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
|
---|
| 483 | }
|
---|
| 484 |
|
---|
| 485 | /**
|
---|
| 486 | * Tests if the guest is running in paged protected or not.
|
---|
| 487 | *
|
---|
| 488 | * @returns true if in paged protected mode, otherwise false.
|
---|
| 489 | * @param pVM The VM handle.
|
---|
| 490 | */
|
---|
| 491 | DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
|
---|
| 492 | {
|
---|
| 493 | return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
|
---|
| 494 | }
|
---|
| 495 |
|
---|
| 496 | /**
|
---|
| 497 | * Tests if the guest is running in paged protected or not.
|
---|
| 498 | *
|
---|
| 499 | * @returns true if in paged protected mode, otherwise false.
|
---|
| 500 | * @param pVM The VM handle.
|
---|
| 501 | */
|
---|
| 502 | CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
|
---|
| 503 |
|
---|
| 504 | /**
|
---|
| 505 | * Tests if the guest is running in paged protected or not.
|
---|
| 506 | *
|
---|
| 507 | * @returns true if in paged protected mode, otherwise false.
|
---|
| 508 | * @param pVM The VM handle.
|
---|
| 509 | */
|
---|
| 510 | CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
|
---|
| 511 |
|
---|
| 512 | /**
|
---|
| 513 | * Tests if the guest is running in paged protected or not.
|
---|
| 514 | *
|
---|
| 515 | * @returns true if in paged protected mode, otherwise false.
|
---|
| 516 | * @param pVM The VM handle.
|
---|
| 517 | */
|
---|
| 518 | CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
|
---|
| 519 |
|
---|
| 520 | /** @} */
|
---|
| 521 |
|
---|
| 522 |
|
---|
| 523 |
|
---|
| 524 | /** @name Hypervisor Register Getters.
|
---|
| 525 | * @{ */
|
---|
| 526 | CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
|
---|
| 527 | CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
|
---|
| 528 | CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
|
---|
| 529 | CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
|
---|
| 530 | CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
|
---|
| 531 | CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
|
---|
| 532 | #if 0 /* these are not correct. */
|
---|
| 533 | CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
|
---|
| 534 | CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
|
---|
| 535 | CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
|
---|
| 536 | CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
|
---|
| 537 | #endif
|
---|
| 538 | /** This register is only saved on fatal traps. */
|
---|
| 539 | CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
|
---|
| 540 | CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
|
---|
| 541 | /** This register is only saved on fatal traps. */
|
---|
| 542 | CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
|
---|
| 543 | /** This register is only saved on fatal traps. */
|
---|
| 544 | CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
|
---|
| 545 | CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
|
---|
| 546 | CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
|
---|
| 547 | CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
|
---|
| 548 | CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
|
---|
| 549 | CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
|
---|
| 550 | CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
|
---|
| 551 | CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
|
---|
| 552 | CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
|
---|
| 553 | CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
|
---|
| 554 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
|
---|
| 555 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
|
---|
| 556 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
|
---|
| 557 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
|
---|
| 558 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
|
---|
| 559 | CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
|
---|
| 560 | CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
|
---|
| 561 | /** @} */
|
---|
| 562 |
|
---|
| 563 | /** @name Hypervisor Register Setters.
|
---|
| 564 | * @{ */
|
---|
| 565 | CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
|
---|
| 566 | CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
|
---|
| 567 | CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
|
---|
| 568 | CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
|
---|
| 569 | CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
|
---|
| 570 | CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
|
---|
| 571 | CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
|
---|
| 572 | CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
|
---|
| 573 | CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
|
---|
| 574 | CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
|
---|
| 575 | CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
|
---|
| 576 | CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
|
---|
| 577 | CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
|
---|
| 578 | CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
|
---|
| 579 | CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
|
---|
| 580 | CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
|
---|
| 581 | CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
|
---|
| 582 | CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
|
---|
| 583 | CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
|
---|
| 584 | CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
|
---|
| 585 | CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
|
---|
| 586 | CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
|
---|
| 587 | /** @} */
|
---|
| 588 |
|
---|
| 589 | CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
|
---|
| 590 |
|
---|
| 591 | /**
|
---|
| 592 | * Sets or resets an alternative hypervisor context core.
|
---|
| 593 | *
|
---|
| 594 | * This is called when we get a hypervisor trap set switch the context
|
---|
| 595 | * core with the trap frame on the stack. It is called again to reset
|
---|
| 596 | * back to the default context core when resuming hypervisor execution.
|
---|
| 597 | *
|
---|
| 598 | * @param pVM The VM handle.
|
---|
| 599 | * @param pCtxCore Pointer to the alternative context core or NULL
|
---|
| 600 | * to go back to the default context core.
|
---|
| 601 | */
|
---|
| 602 | CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
|
---|
| 603 |
|
---|
| 604 |
|
---|
| 605 | /**
|
---|
| 606 | * Queries the pointer to the internal CPUMCTX structure
|
---|
| 607 | *
|
---|
| 608 | * @returns VBox status code.
|
---|
| 609 | * @param pVM Handle to the virtual machine.
|
---|
| 610 | * @param ppCtx Receives the CPUMCTX pointer when successful.
|
---|
| 611 | */
|
---|
| 612 | CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
|
---|
| 613 |
|
---|
| 614 | /**
|
---|
| 615 | * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
|
---|
| 616 | *
|
---|
| 617 | * @returns VBox status code.
|
---|
| 618 | * @param pVM Handle to the virtual machine.
|
---|
| 619 | * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
|
---|
| 620 | */
|
---|
| 621 | CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
|
---|
| 622 |
|
---|
| 623 |
|
---|
| 624 | /**
|
---|
| 625 | * Gets the pointer to the internal CPUMCTXCORE structure.
|
---|
| 626 | * This is only for reading in order to save a few calls.
|
---|
| 627 | *
|
---|
| 628 | * @param pVM Handle to the virtual machine.
|
---|
| 629 | */
|
---|
| 630 | CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
|
---|
| 631 |
|
---|
| 632 | /**
|
---|
| 633 | * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
|
---|
| 634 | * This is only for reading in order to save a few calls.
|
---|
| 635 | *
|
---|
| 636 | * @param pVM Handle to the virtual machine.
|
---|
| 637 | */
|
---|
| 638 | CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
|
---|
| 639 |
|
---|
| 640 | /**
|
---|
| 641 | * Sets the guest context core registers.
|
---|
| 642 | *
|
---|
| 643 | * @param pVM Handle to the virtual machine.
|
---|
| 644 | * @param pCtxCore The new context core values.
|
---|
| 645 | */
|
---|
| 646 | CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
|
---|
| 647 |
|
---|
| 648 |
|
---|
| 649 | /**
|
---|
| 650 | * Transforms the guest CPU state to raw-ring mode.
|
---|
| 651 | *
|
---|
| 652 | * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
|
---|
| 653 | *
|
---|
| 654 | * @returns VBox status. (recompiler failure)
|
---|
| 655 | * @param pVM VM handle.
|
---|
| 656 | * @param pCtxCore The context core (for trap usage).
|
---|
| 657 | * @see @ref pg_raw
|
---|
| 658 | */
|
---|
| 659 | CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
|
---|
| 660 |
|
---|
| 661 | /**
|
---|
| 662 | * Transforms the guest CPU state from raw-ring mode to correct values.
|
---|
| 663 | *
|
---|
| 664 | * This function will change any selector registers with DPL=1 to DPL=0.
|
---|
| 665 | *
|
---|
| 666 | * @returns Adjusted rc.
|
---|
| 667 | * @param pVM VM handle.
|
---|
| 668 | * @param rc Raw mode return code
|
---|
| 669 | * @param pCtxCore The context core (for trap usage).
|
---|
| 670 | * @see @ref pg_raw
|
---|
| 671 | */
|
---|
| 672 | CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
|
---|
| 673 |
|
---|
| 674 | /**
|
---|
| 675 | * Gets the EFLAGS while we're in raw-mode.
|
---|
| 676 | *
|
---|
| 677 | * @returns The eflags.
|
---|
| 678 | * @param pVM The VM handle.
|
---|
| 679 | * @param pCtxCore The context core.
|
---|
| 680 | */
|
---|
| 681 | CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
|
---|
| 682 |
|
---|
| 683 | /**
|
---|
| 684 | * Updates the EFLAGS while we're in raw-mode.
|
---|
| 685 | *
|
---|
| 686 | * @param pVM The VM handle.
|
---|
| 687 | * @param pCtxCore The context core.
|
---|
| 688 | * @param eflags The new EFLAGS value.
|
---|
| 689 | */
|
---|
| 690 | CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
|
---|
| 691 |
|
---|
| 692 | /**
|
---|
| 693 | * Lazily sync in the FPU/XMM state
|
---|
| 694 | *
|
---|
| 695 | * This function will change any selector registers with DPL=1 to DPL=0.
|
---|
| 696 | *
|
---|
| 697 | * @returns VBox status code.
|
---|
| 698 | * @param pVM VM handle.
|
---|
| 699 | */
|
---|
| 700 | CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
|
---|
| 701 |
|
---|
| 702 |
|
---|
| 703 | /**
|
---|
| 704 | * Restore host FPU/XMM state
|
---|
| 705 | *
|
---|
| 706 | * @returns VBox status code.
|
---|
| 707 | * @param pVM VM handle.
|
---|
| 708 | */
|
---|
| 709 | CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
|
---|
| 710 |
|
---|
| 711 | /** @name Changed flags
|
---|
| 712 | * These flags are used to keep track of which important register that
|
---|
| 713 | * have been changed since last they were reset. The only one allowed
|
---|
| 714 | * to clear them is REM!
|
---|
| 715 | * @{
|
---|
| 716 | */
|
---|
[5605] | 717 | #define CPUM_CHANGED_FPU_REM RT_BIT(0)
|
---|
| 718 | #define CPUM_CHANGED_CR0 RT_BIT(1)
|
---|
| 719 | #define CPUM_CHANGED_CR4 RT_BIT(2)
|
---|
| 720 | #define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
|
---|
| 721 | #define CPUM_CHANGED_CR3 RT_BIT(4)
|
---|
| 722 | #define CPUM_CHANGED_GDTR RT_BIT(5)
|
---|
| 723 | #define CPUM_CHANGED_IDTR RT_BIT(6)
|
---|
| 724 | #define CPUM_CHANGED_LDTR RT_BIT(7)
|
---|
| 725 | #define CPUM_CHANGED_TR RT_BIT(8)
|
---|
| 726 | #define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
|
---|
| 727 | #define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
|
---|
[8113] | 728 | #define CPUM_CHANGED_CPUID RT_BIT(11)
|
---|
[1] | 729 | /** @} */
|
---|
| 730 |
|
---|
| 731 | /**
|
---|
| 732 | * Gets and resets the changed flags (CPUM_CHANGED_*).
|
---|
| 733 | *
|
---|
| 734 | * @returns The changed flags.
|
---|
| 735 | * @param pVM VM handle.
|
---|
| 736 | */
|
---|
| 737 | CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
|
---|
| 738 |
|
---|
| 739 | /**
|
---|
| 740 | * Sets the specified changed flags (CPUM_CHANGED_*).
|
---|
| 741 | *
|
---|
| 742 | * @param pVM The VM handle.
|
---|
| 743 | */
|
---|
| 744 | CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
|
---|
| 745 |
|
---|
| 746 | /**
|
---|
| 747 | * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
|
---|
| 748 | * @returns true if supported.
|
---|
| 749 | * @returns false if not supported.
|
---|
| 750 | * @param pVM The VM handle.
|
---|
| 751 | */
|
---|
| 752 | CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
|
---|
| 753 |
|
---|
| 754 | /**
|
---|
| 755 | * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
|
---|
| 756 | * @returns true if used.
|
---|
| 757 | * @returns false if not used.
|
---|
| 758 | * @param pVM The VM handle.
|
---|
| 759 | */
|
---|
| 760 | CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
|
---|
| 761 |
|
---|
| 762 | /**
|
---|
| 763 | * Checks if the host OS uses the SYSCALL / SYSRET instructions.
|
---|
| 764 | * @returns true if used.
|
---|
| 765 | * @returns false if not used.
|
---|
| 766 | * @param pVM The VM handle.
|
---|
| 767 | */
|
---|
| 768 | CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
|
---|
| 769 |
|
---|
| 770 | /**
|
---|
| 771 | * Checks if we activated the FPU/XMM state of the guest OS
|
---|
| 772 | * @returns true if we did.
|
---|
| 773 | * @returns false if not.
|
---|
| 774 | * @param pVM The VM handle.
|
---|
| 775 | */
|
---|
| 776 | CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
|
---|
| 777 |
|
---|
| 778 | /**
|
---|
| 779 | * Deactivate the FPU/XMM state of the guest OS
|
---|
| 780 | * @param pVM The VM handle.
|
---|
| 781 | */
|
---|
| 782 | CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
|
---|
| 783 |
|
---|
| 784 |
|
---|
| 785 | /**
|
---|
| 786 | * Checks if the hidden selector registers are valid
|
---|
| 787 | * @returns true if they are.
|
---|
| 788 | * @returns false if not.
|
---|
| 789 | * @param pVM The VM handle.
|
---|
| 790 | */
|
---|
| 791 | CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
|
---|
| 792 |
|
---|
| 793 | /**
|
---|
| 794 | * Checks if the hidden selector registers are valid
|
---|
| 795 | * @param pVM The VM handle.
|
---|
| 796 | * @param fValid Valid or not
|
---|
| 797 | */
|
---|
| 798 | CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
|
---|
| 799 |
|
---|
[1826] | 800 | /**
|
---|
| 801 | * Get the current privilege level of the guest.
|
---|
| 802 | *
|
---|
| 803 | * @returns cpl
|
---|
| 804 | * @param pVM VM Handle.
|
---|
| 805 | * @param pRegFrame Trap register frame.
|
---|
| 806 | */
|
---|
[1827] | 807 | CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
|
---|
[1] | 808 |
|
---|
[4207] | 809 | /**
|
---|
| 810 | * CPU modes.
|
---|
| 811 | */
|
---|
| 812 | typedef enum CPUMMODE
|
---|
| 813 | {
|
---|
| 814 | /** The usual invalid zero entry. */
|
---|
| 815 | CPUMMODE_INVALID = 0,
|
---|
| 816 | /** Real mode. */
|
---|
| 817 | CPUMMODE_REAL,
|
---|
| 818 | /** Protected mode (32-bit). */
|
---|
| 819 | CPUMMODE_PROTECTED,
|
---|
| 820 | /** Long mode (64-bit). */
|
---|
| 821 | CPUMMODE_LONG
|
---|
| 822 | } CPUMMODE;
|
---|
[1826] | 823 |
|
---|
[4207] | 824 | /**
|
---|
| 825 | * Gets the current guest CPU mode.
|
---|
| 826 | *
|
---|
| 827 | * If paging mode is what you need, check out PGMGetGuestMode().
|
---|
| 828 | *
|
---|
| 829 | * @returns The CPU mode.
|
---|
| 830 | * @param pVM The VM handle.
|
---|
| 831 | */
|
---|
[4208] | 832 | CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
|
---|
[4207] | 833 |
|
---|
| 834 |
|
---|
[1] | 835 | #ifdef IN_RING3
|
---|
| 836 | /** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
|
---|
| 837 | * @ingroup grp_cpum
|
---|
| 838 | * @{
|
---|
| 839 | */
|
---|
| 840 |
|
---|
| 841 | /**
|
---|
| 842 | * Initializes the CPUM.
|
---|
| 843 | *
|
---|
| 844 | * @returns VBox status code.
|
---|
| 845 | * @param pVM The VM to operate on.
|
---|
| 846 | */
|
---|
| 847 | CPUMR3DECL(int) CPUMR3Init(PVM pVM);
|
---|
| 848 |
|
---|
| 849 | /**
|
---|
| 850 | * Applies relocations to data and code managed by this
|
---|
| 851 | * component. This function will be called at init and
|
---|
| 852 | * whenever the VMM need to relocate it self inside the GC.
|
---|
| 853 | *
|
---|
| 854 | * The CPUM will update the addresses used by the switcher.
|
---|
| 855 | *
|
---|
| 856 | * @param pVM The VM.
|
---|
| 857 | */
|
---|
| 858 | CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
|
---|
| 859 |
|
---|
| 860 | /**
|
---|
| 861 | * Terminates the CPUM.
|
---|
| 862 | *
|
---|
| 863 | * Termination means cleaning up and freeing all resources,
|
---|
| 864 | * the VM it self is at this point powered off or suspended.
|
---|
| 865 | *
|
---|
| 866 | * @returns VBox status code.
|
---|
| 867 | * @param pVM The VM to operate on.
|
---|
| 868 | */
|
---|
| 869 | CPUMR3DECL(int) CPUMR3Term(PVM pVM);
|
---|
| 870 |
|
---|
| 871 | /**
|
---|
| 872 | * Resets the CPU.
|
---|
| 873 | *
|
---|
| 874 | * @param pVM The VM handle.
|
---|
| 875 | */
|
---|
| 876 | CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
|
---|
| 877 |
|
---|
| 878 | /**
|
---|
| 879 | * Queries the pointer to the internal CPUMCTX structure
|
---|
| 880 | *
|
---|
| 881 | * @returns VBox status code.
|
---|
| 882 | * @param pVM Handle to the virtual machine.
|
---|
| 883 | * @param ppCtx Receives the CPUMCTX GC pointer when successful.
|
---|
| 884 | */
|
---|
| 885 | CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
|
---|
| 886 |
|
---|
| 887 |
|
---|
| 888 | #ifdef DEBUG
|
---|
| 889 | /**
|
---|
| 890 | * Debug helper - Saves guest context on raw mode entry (for fatal dump)
|
---|
| 891 | *
|
---|
| 892 | * @internal
|
---|
| 893 | */
|
---|
| 894 | CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
|
---|
| 895 | #endif
|
---|
| 896 |
|
---|
[1056] | 897 | /**
|
---|
| 898 | * API for controlling a few of the CPU features found in CR4.
|
---|
[4207] | 899 | *
|
---|
[1056] | 900 | * Currently only X86_CR4_TSD is accepted as input.
|
---|
[4207] | 901 | *
|
---|
[1056] | 902 | * @returns VBox status code.
|
---|
[4207] | 903 | *
|
---|
[1056] | 904 | * @param pVM The VM handle.
|
---|
| 905 | * @param fOr The CR4 OR mask.
|
---|
| 906 | * @param fAnd The CR4 AND mask.
|
---|
| 907 | */
|
---|
| 908 | CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
|
---|
| 909 |
|
---|
[1] | 910 | /** @} */
|
---|
| 911 | #endif
|
---|
| 912 |
|
---|
| 913 | #ifdef IN_GC
|
---|
| 914 | /** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
|
---|
| 915 | * @ingroup grp_cpum
|
---|
| 916 | * @{
|
---|
| 917 | */
|
---|
| 918 |
|
---|
| 919 | /**
|
---|
| 920 | * Calls a guest trap/interrupt handler directly
|
---|
| 921 | * Assumes a trap stack frame has already been setup on the guest's stack!
|
---|
| 922 | *
|
---|
| 923 | * @param pRegFrame Original trap/interrupt context
|
---|
| 924 | * @param selCS Code selector of handler
|
---|
| 925 | * @param pHandler GC virtual address of handler
|
---|
| 926 | * @param eflags Callee's EFLAGS
|
---|
| 927 | * @param selSS Stack selector for handler
|
---|
| 928 | * @param pEsp Stack address for handler
|
---|
| 929 | *
|
---|
| 930 | * This function does not return!
|
---|
| 931 | *
|
---|
| 932 | */
|
---|
| 933 | CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
|
---|
| 934 |
|
---|
[1133] | 935 | /**
|
---|
| 936 | * Performs an iret to V86 code
|
---|
| 937 | * Assumes a trap stack frame has already been setup on the guest's stack!
|
---|
| 938 | *
|
---|
| 939 | * @param pRegFrame Original trap/interrupt context
|
---|
| 940 | *
|
---|
| 941 | * This function does not return!
|
---|
| 942 | */
|
---|
| 943 | CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
|
---|
| 944 |
|
---|
[1] | 945 | /** @} */
|
---|
| 946 | #endif
|
---|
| 947 |
|
---|
| 948 | #ifdef IN_RING0
|
---|
| 949 | /** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
|
---|
| 950 | * @ingroup grp_cpum
|
---|
| 951 | * @{
|
---|
| 952 | */
|
---|
| 953 |
|
---|
| 954 | /**
|
---|
| 955 | * Does Ring-0 CPUM initialization.
|
---|
| 956 | *
|
---|
| 957 | * This is mainly to check that the Host CPU mode is compatible
|
---|
| 958 | * with VBox.
|
---|
| 959 | *
|
---|
| 960 | * @returns VBox status code.
|
---|
| 961 | * @param pVM The VM to operate on.
|
---|
| 962 | */
|
---|
| 963 | CPUMR0DECL(int) CPUMR0Init(PVM pVM);
|
---|
| 964 |
|
---|
| 965 | /** @} */
|
---|
| 966 | #endif
|
---|
| 967 |
|
---|
| 968 | /** @} */
|
---|
| 969 | __END_DECLS
|
---|
| 970 |
|
---|
| 971 |
|
---|
| 972 | #endif
|
---|
| 973 |
|
---|
| 974 |
|
---|
| 975 |
|
---|
| 976 |
|
---|
| 977 |
|
---|