VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 8155

Last change on this file since 8155 was 8155, checked in by vboxsync, 16 years ago

The Big Sun Rebranding Header Change
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_cpum_h
31#define ___VBox_cpum_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/x86.h>
36
37
38__BEGIN_DECLS
39
40/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREGHID
48{
49 /** Base register. */
50 uint32_t u32Base;
51 /** Limit (expanded). */
52 uint32_t u32Limit;
53 /** Flags.
54 * This is the high 32-bit word of the descriptor entry.
55 * Only the flags, dpl and type are used. */
56 X86DESCATTR Attr;
57} CPUMSELREGHID;
58
59
60/**
61 * The sysenter register set.
62 */
63typedef struct CPUMSYSENTER
64{
65 /** Ring 0 cs.
66 * This value + 8 is the Ring 0 ss.
67 * This value + 16 is the Ring 3 cs.
68 * This value + 24 is the Ring 3 ss.
69 */
70 uint64_t cs;
71 /** Ring 0 eip. */
72 uint64_t eip;
73 /** Ring 0 esp. */
74 uint64_t esp;
75} CPUMSYSENTER;
76
77
78/**
79 * CPU context core.
80 */
81#pragma pack(1)
82typedef struct CPUMCTXCORE
83{
84 union
85 {
86 uint32_t edi;
87 uint64_t rdi;
88 };
89 union
90 {
91 uint32_t esi;
92 uint64_t rsi;
93 };
94 union
95 {
96 uint32_t ebp;
97 uint64_t rbp;
98 };
99 union
100 {
101 uint32_t eax;
102 uint64_t rax;
103 };
104 union
105 {
106 uint32_t ebx;
107 uint64_t rbx;
108 };
109 union
110 {
111 uint32_t edx;
112 uint64_t rdx;
113 };
114 union
115 {
116 uint32_t ecx;
117 uint64_t rcx;
118 };
119 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
120 uint32_t esp;
121 RTSEL ss;
122 RTSEL ssPadding;
123 /* Note: no overlap with esp here. */
124 uint64_t rsp;
125
126 RTSEL gs;
127 RTSEL gsPadding;
128 RTSEL fs;
129 RTSEL fsPadding;
130 RTSEL es;
131 RTSEL esPadding;
132 RTSEL ds;
133 RTSEL dsPadding;
134 RTSEL cs;
135 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
136
137 union
138 {
139 X86EFLAGS eflags;
140 X86RFLAGS rflags;
141 };
142 union
143 {
144 uint32_t eip;
145 uint64_t rip;
146 };
147
148 uint64_t r8;
149 uint64_t r9;
150 uint64_t r10;
151 uint64_t r11;
152 uint64_t r12;
153 uint64_t r13;
154 uint64_t r14;
155 uint64_t r15;
156
157 /** Hidden selector registers.
158 * @{ */
159 CPUMSELREGHID esHid;
160 CPUMSELREGHID csHid;
161 CPUMSELREGHID ssHid;
162 CPUMSELREGHID dsHid;
163 CPUMSELREGHID fsHid;
164 CPUMSELREGHID gsHid;
165 /** @} */
166
167} CPUMCTXCORE;
168#pragma pack()
169
170
171/**
172 * CPU context.
173 */
174#pragma pack(1)
175typedef struct CPUMCTX
176{
177 /** FPU state. (16-byte alignment)
178 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
179 * actual format or convert it (waste of time). */
180 X86FXSTATE fpu;
181
182 /** CPUMCTXCORE Part.
183 * @{ */
184 union
185 {
186 uint32_t edi;
187 uint64_t rdi;
188 };
189 union
190 {
191 uint32_t esi;
192 uint64_t rsi;
193 };
194 union
195 {
196 uint32_t ebp;
197 uint64_t rbp;
198 };
199 union
200 {
201 uint32_t eax;
202 uint64_t rax;
203 };
204 union
205 {
206 uint32_t ebx;
207 uint64_t rbx;
208 };
209 union
210 {
211 uint32_t edx;
212 uint64_t rdx;
213 };
214 union
215 {
216 uint32_t ecx;
217 uint64_t rcx;
218 };
219 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
220 uint32_t esp;
221 RTSEL ss;
222 RTSEL ssPadding;
223 /* Note: no overlap with esp here. */
224 uint64_t rsp;
225
226 RTSEL gs;
227 RTSEL gsPadding;
228 RTSEL fs;
229 RTSEL fsPadding;
230 RTSEL es;
231 RTSEL esPadding;
232 RTSEL ds;
233 RTSEL dsPadding;
234 RTSEL cs;
235 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
236
237 union
238 {
239 X86EFLAGS eflags;
240 X86RFLAGS rflags;
241 };
242 union
243 {
244 uint32_t eip;
245 uint64_t rip;
246 };
247
248 uint64_t r8;
249 uint64_t r9;
250 uint64_t r10;
251 uint64_t r11;
252 uint64_t r12;
253 uint64_t r13;
254 uint64_t r14;
255 uint64_t r15;
256
257 /** Hidden selector registers.
258 * @{ */
259 CPUMSELREGHID esHid;
260 CPUMSELREGHID csHid;
261 CPUMSELREGHID ssHid;
262 CPUMSELREGHID dsHid;
263 CPUMSELREGHID fsHid;
264 CPUMSELREGHID gsHid;
265 /** @} */
266
267 /** @} */
268
269 /** Control registers.
270 * @{ */
271 uint64_t cr0;
272 uint64_t cr2;
273 uint64_t cr3;
274 uint64_t cr4;
275 uint64_t cr8;
276 /** @} */
277
278 /** Debug registers.
279 * @{ */
280 uint64_t dr0;
281 uint64_t dr1;
282 uint64_t dr2;
283 uint64_t dr3;
284 uint64_t dr4; /**< @todo remove dr4 and dr5. */
285 uint64_t dr5;
286 uint64_t dr6;
287 uint64_t dr7;
288 /* DR8-15 are currently not supported */
289 /** @} */
290
291 /** Global Descriptor Table register. */
292 VBOXGDTR gdtr;
293 uint16_t gdtrPadding;
294 uint32_t gdtrPadding64;/** @todo fix this hack */
295 /** Interrupt Descriptor Table register. */
296 VBOXIDTR idtr;
297 uint16_t idtrPadding;
298 uint32_t idtrPadding64;/** @todo fix this hack */
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL ldtr;
302 RTSEL ldtrPadding;
303 /** The task register.
304 * Only the guest context uses all the members. */
305 RTSEL tr;
306 RTSEL trPadding;
307
308 /** The sysenter msr registers.
309 * This member is not used by the hypervisor context. */
310 CPUMSYSENTER SysEnter;
311
312 /** System MSRs.
313 * @{ */
314 uint64_t msrEFER;
315 uint64_t msrSTAR;
316 uint64_t msrPAT;
317 uint64_t msrLSTAR;
318 uint64_t msrCSTAR;
319 uint64_t msrSFMASK;
320 uint64_t msrFSBASE;
321 uint64_t msrGSBASE;
322 uint64_t msrKERNELGSBASE;
323 /** @} */
324
325 /** Hidden selector registers.
326 * @{ */
327 CPUMSELREGHID ldtrHid;
328 CPUMSELREGHID trHid;
329 /** @} */
330
331 /* padding to get 32byte aligned size */
332 uint32_t padding[2];
333} CPUMCTX;
334#pragma pack()
335
336/**
337 * Gets the CPUMCTXCORE part of a CPUMCTX.
338 */
339#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
340
341/**
342 * The register set returned by a CPUID operation.
343 */
344typedef struct CPUMCPUID
345{
346 uint32_t eax;
347 uint32_t ebx;
348 uint32_t ecx;
349 uint32_t edx;
350} CPUMCPUID;
351/** Pointer to a CPUID leaf. */
352typedef CPUMCPUID *PCPUMCPUID;
353/** Pointer to a const CPUID leaf. */
354typedef const CPUMCPUID *PCCPUMCPUID;
355
356/**
357 * CPUID feature to set or clear.
358 */
359typedef enum CPUMCPUIDFEATURE
360{
361 CPUMCPUIDFEATURE_INVALID = 0,
362 /** The APIC feature bit. (Std+Ext) */
363 CPUMCPUIDFEATURE_APIC,
364 /** The sysenter/sysexit feature bit. (Std+Ext) */
365 CPUMCPUIDFEATURE_SEP,
366 /** The PAE feature bit. (Std+Ext) */
367 CPUMCPUIDFEATURE_PAE,
368 /** The LONG MODE feature bit. (Ext) */
369 CPUMCPUIDFEATURE_LONG_MODE
370} CPUMCPUIDFEATURE;
371
372
373/** @name Guest Register Getters.
374 * @{ */
375CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
376CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
377CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
378CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
379CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
380CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
381CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
382CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
383CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
384CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
385CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
386CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
387CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
388CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
389CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
390CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
391CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
392CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
393CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
394CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
395CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
396CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
397CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
398CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
399CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
400CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
401CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
402CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
403CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
404CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
405CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
406CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
407CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
408CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
409CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
410CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
411CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
412CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
413CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
414CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
415CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
416CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
417/** @} */
418
419/** @name Guest Register Setters.
420 * @{ */
421CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
422CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
423CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
424CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
425CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
426CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
427CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
428CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
429CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
430CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
431CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
432CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
433CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
434CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
435CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
436CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
437CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
438CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
439CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
440CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
441CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
442CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
443CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
444CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
445CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
446CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
447CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
448CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
449CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
450CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
451CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
452CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
453CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
454CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
455CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
456CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
457CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
458/** @} */
459
460/** @name Misc Guest Predicate Functions.
461 * @{ */
462
463/**
464 * Tests if the guest is running in real mode or not.
465 *
466 * @returns true if in real mode, otherwise false.
467 * @param pVM The VM handle.
468 */
469DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
470{
471 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
472}
473
474/**
475 * Tests if the guest is running in protected or not.
476 *
477 * @returns true if in protected mode, otherwise false.
478 * @param pVM The VM handle.
479 */
480DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
481{
482 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
483}
484
485/**
486 * Tests if the guest is running in paged protected or not.
487 *
488 * @returns true if in paged protected mode, otherwise false.
489 * @param pVM The VM handle.
490 */
491DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
492{
493 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
494}
495
496/**
497 * Tests if the guest is running in paged protected or not.
498 *
499 * @returns true if in paged protected mode, otherwise false.
500 * @param pVM The VM handle.
501 */
502CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
503
504/**
505 * Tests if the guest is running in paged protected or not.
506 *
507 * @returns true if in paged protected mode, otherwise false.
508 * @param pVM The VM handle.
509 */
510CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
511
512/**
513 * Tests if the guest is running in paged protected or not.
514 *
515 * @returns true if in paged protected mode, otherwise false.
516 * @param pVM The VM handle.
517 */
518CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
519
520/** @} */
521
522
523
524/** @name Hypervisor Register Getters.
525 * @{ */
526CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
527CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
528CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
529CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
530CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
531CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
532#if 0 /* these are not correct. */
533CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
534CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
535CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
536CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
537#endif
538/** This register is only saved on fatal traps. */
539CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
540CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
541/** This register is only saved on fatal traps. */
542CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
543/** This register is only saved on fatal traps. */
544CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
545CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
546CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
547CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
548CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
549CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
550CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
551CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
552CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
553CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
554CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
555CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
556CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
557CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
558CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
559CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
560CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
561/** @} */
562
563/** @name Hypervisor Register Setters.
564 * @{ */
565CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
566CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
567CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
568CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
569CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
570CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
571CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
572CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
573CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
574CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
575CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
576CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
577CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
578CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
579CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
580CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
581CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
582CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
583CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
584CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
585CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
586CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
587/** @} */
588
589CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
590
591/**
592 * Sets or resets an alternative hypervisor context core.
593 *
594 * This is called when we get a hypervisor trap set switch the context
595 * core with the trap frame on the stack. It is called again to reset
596 * back to the default context core when resuming hypervisor execution.
597 *
598 * @param pVM The VM handle.
599 * @param pCtxCore Pointer to the alternative context core or NULL
600 * to go back to the default context core.
601 */
602CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
603
604
605/**
606 * Queries the pointer to the internal CPUMCTX structure
607 *
608 * @returns VBox status code.
609 * @param pVM Handle to the virtual machine.
610 * @param ppCtx Receives the CPUMCTX pointer when successful.
611 */
612CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
613
614/**
615 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
616 *
617 * @returns VBox status code.
618 * @param pVM Handle to the virtual machine.
619 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
620 */
621CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
622
623
624/**
625 * Gets the pointer to the internal CPUMCTXCORE structure.
626 * This is only for reading in order to save a few calls.
627 *
628 * @param pVM Handle to the virtual machine.
629 */
630CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
631
632/**
633 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
634 * This is only for reading in order to save a few calls.
635 *
636 * @param pVM Handle to the virtual machine.
637 */
638CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
639
640/**
641 * Sets the guest context core registers.
642 *
643 * @param pVM Handle to the virtual machine.
644 * @param pCtxCore The new context core values.
645 */
646CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
647
648
649/**
650 * Transforms the guest CPU state to raw-ring mode.
651 *
652 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
653 *
654 * @returns VBox status. (recompiler failure)
655 * @param pVM VM handle.
656 * @param pCtxCore The context core (for trap usage).
657 * @see @ref pg_raw
658 */
659CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
660
661/**
662 * Transforms the guest CPU state from raw-ring mode to correct values.
663 *
664 * This function will change any selector registers with DPL=1 to DPL=0.
665 *
666 * @returns Adjusted rc.
667 * @param pVM VM handle.
668 * @param rc Raw mode return code
669 * @param pCtxCore The context core (for trap usage).
670 * @see @ref pg_raw
671 */
672CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
673
674/**
675 * Gets the EFLAGS while we're in raw-mode.
676 *
677 * @returns The eflags.
678 * @param pVM The VM handle.
679 * @param pCtxCore The context core.
680 */
681CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
682
683/**
684 * Updates the EFLAGS while we're in raw-mode.
685 *
686 * @param pVM The VM handle.
687 * @param pCtxCore The context core.
688 * @param eflags The new EFLAGS value.
689 */
690CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
691
692/**
693 * Lazily sync in the FPU/XMM state
694 *
695 * This function will change any selector registers with DPL=1 to DPL=0.
696 *
697 * @returns VBox status code.
698 * @param pVM VM handle.
699 */
700CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
701
702
703/**
704 * Restore host FPU/XMM state
705 *
706 * @returns VBox status code.
707 * @param pVM VM handle.
708 */
709CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
710
711/** @name Changed flags
712 * These flags are used to keep track of which important register that
713 * have been changed since last they were reset. The only one allowed
714 * to clear them is REM!
715 * @{
716 */
717#define CPUM_CHANGED_FPU_REM RT_BIT(0)
718#define CPUM_CHANGED_CR0 RT_BIT(1)
719#define CPUM_CHANGED_CR4 RT_BIT(2)
720#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
721#define CPUM_CHANGED_CR3 RT_BIT(4)
722#define CPUM_CHANGED_GDTR RT_BIT(5)
723#define CPUM_CHANGED_IDTR RT_BIT(6)
724#define CPUM_CHANGED_LDTR RT_BIT(7)
725#define CPUM_CHANGED_TR RT_BIT(8)
726#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
727#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
728#define CPUM_CHANGED_CPUID RT_BIT(11)
729/** @} */
730
731/**
732 * Gets and resets the changed flags (CPUM_CHANGED_*).
733 *
734 * @returns The changed flags.
735 * @param pVM VM handle.
736 */
737CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
738
739/**
740 * Sets the specified changed flags (CPUM_CHANGED_*).
741 *
742 * @param pVM The VM handle.
743 */
744CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
745
746/**
747 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
748 * @returns true if supported.
749 * @returns false if not supported.
750 * @param pVM The VM handle.
751 */
752CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
753
754/**
755 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
756 * @returns true if used.
757 * @returns false if not used.
758 * @param pVM The VM handle.
759 */
760CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
761
762/**
763 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
764 * @returns true if used.
765 * @returns false if not used.
766 * @param pVM The VM handle.
767 */
768CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
769
770/**
771 * Checks if we activated the FPU/XMM state of the guest OS
772 * @returns true if we did.
773 * @returns false if not.
774 * @param pVM The VM handle.
775 */
776CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
777
778/**
779 * Deactivate the FPU/XMM state of the guest OS
780 * @param pVM The VM handle.
781 */
782CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
783
784
785/**
786 * Checks if the hidden selector registers are valid
787 * @returns true if they are.
788 * @returns false if not.
789 * @param pVM The VM handle.
790 */
791CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
792
793/**
794 * Checks if the hidden selector registers are valid
795 * @param pVM The VM handle.
796 * @param fValid Valid or not
797 */
798CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
799
800/**
801 * Get the current privilege level of the guest.
802 *
803 * @returns cpl
804 * @param pVM VM Handle.
805 * @param pRegFrame Trap register frame.
806 */
807CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
808
809/**
810 * CPU modes.
811 */
812typedef enum CPUMMODE
813{
814 /** The usual invalid zero entry. */
815 CPUMMODE_INVALID = 0,
816 /** Real mode. */
817 CPUMMODE_REAL,
818 /** Protected mode (32-bit). */
819 CPUMMODE_PROTECTED,
820 /** Long mode (64-bit). */
821 CPUMMODE_LONG
822} CPUMMODE;
823
824/**
825 * Gets the current guest CPU mode.
826 *
827 * If paging mode is what you need, check out PGMGetGuestMode().
828 *
829 * @returns The CPU mode.
830 * @param pVM The VM handle.
831 */
832CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
833
834
835#ifdef IN_RING3
836/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
837 * @ingroup grp_cpum
838 * @{
839 */
840
841/**
842 * Initializes the CPUM.
843 *
844 * @returns VBox status code.
845 * @param pVM The VM to operate on.
846 */
847CPUMR3DECL(int) CPUMR3Init(PVM pVM);
848
849/**
850 * Applies relocations to data and code managed by this
851 * component. This function will be called at init and
852 * whenever the VMM need to relocate it self inside the GC.
853 *
854 * The CPUM will update the addresses used by the switcher.
855 *
856 * @param pVM The VM.
857 */
858CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
859
860/**
861 * Terminates the CPUM.
862 *
863 * Termination means cleaning up and freeing all resources,
864 * the VM it self is at this point powered off or suspended.
865 *
866 * @returns VBox status code.
867 * @param pVM The VM to operate on.
868 */
869CPUMR3DECL(int) CPUMR3Term(PVM pVM);
870
871/**
872 * Resets the CPU.
873 *
874 * @param pVM The VM handle.
875 */
876CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
877
878/**
879 * Queries the pointer to the internal CPUMCTX structure
880 *
881 * @returns VBox status code.
882 * @param pVM Handle to the virtual machine.
883 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
884 */
885CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
886
887
888#ifdef DEBUG
889/**
890 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
891 *
892 * @internal
893 */
894CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
895#endif
896
897/**
898 * API for controlling a few of the CPU features found in CR4.
899 *
900 * Currently only X86_CR4_TSD is accepted as input.
901 *
902 * @returns VBox status code.
903 *
904 * @param pVM The VM handle.
905 * @param fOr The CR4 OR mask.
906 * @param fAnd The CR4 AND mask.
907 */
908CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
909
910/** @} */
911#endif
912
913#ifdef IN_GC
914/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
915 * @ingroup grp_cpum
916 * @{
917 */
918
919/**
920 * Calls a guest trap/interrupt handler directly
921 * Assumes a trap stack frame has already been setup on the guest's stack!
922 *
923 * @param pRegFrame Original trap/interrupt context
924 * @param selCS Code selector of handler
925 * @param pHandler GC virtual address of handler
926 * @param eflags Callee's EFLAGS
927 * @param selSS Stack selector for handler
928 * @param pEsp Stack address for handler
929 *
930 * This function does not return!
931 *
932 */
933CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
934
935/**
936 * Performs an iret to V86 code
937 * Assumes a trap stack frame has already been setup on the guest's stack!
938 *
939 * @param pRegFrame Original trap/interrupt context
940 *
941 * This function does not return!
942 */
943CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
944
945/** @} */
946#endif
947
948#ifdef IN_RING0
949/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
950 * @ingroup grp_cpum
951 * @{
952 */
953
954/**
955 * Does Ring-0 CPUM initialization.
956 *
957 * This is mainly to check that the Host CPU mode is compatible
958 * with VBox.
959 *
960 * @returns VBox status code.
961 * @param pVM The VM to operate on.
962 */
963CPUMR0DECL(int) CPUMR0Init(PVM pVM);
964
965/** @} */
966#endif
967
968/** @} */
969__END_DECLS
970
971
972#endif
973
974
975
976
977
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