[38848] | 1 | /* $Id: ahci.c 104068 2024-03-26 16:38:31Z vboxsync $ */
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| 2 | /** @file
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| 3 | * AHCI host adapter driver to boot from SATA disks.
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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[38848] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[38848] | 26 | */
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| 27 |
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| 28 | #include <stdint.h>
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| 29 | #include <string.h>
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| 30 | #include "biosint.h"
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| 31 | #include "ebda.h"
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| 32 | #include "inlines.h"
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[38897] | 33 | #include "pciutil.h"
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[38899] | 34 | #include "vds.h"
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[38848] | 35 |
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[39583] | 36 | #if DEBUG_AHCI
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| 37 | # define DBG_AHCI(...) BX_INFO(__VA_ARGS__)
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[38848] | 38 | #else
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[39583] | 39 | # define DBG_AHCI(...)
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[38848] | 40 | #endif
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| 41 |
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[38899] | 42 | /* Number of S/G table entries in EDDS. */
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[104068] | 43 | #define NUM_EDDS_SG 17
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[38899] | 44 |
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| 45 |
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[38848] | 46 | /**
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[38899] | 47 | * AHCI PRDT structure.
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| 48 | */
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| 49 | typedef struct
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| 50 | {
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| 51 | uint32_t phys_addr;
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| 52 | uint32_t something;
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| 53 | uint32_t reserved;
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| 54 | uint32_t len;
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| 55 | } ahci_prdt;
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| 56 |
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| 57 | /**
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[55206] | 58 | * SATA D2H FIS (Device to Host Frame Information Structure).
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| 59 | */
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| 60 | typedef struct {
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| 61 | uint8_t fis_type; /* 34h */
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| 62 | uint8_t intr; /* Bit 6 indicates interrupt status. */
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| 63 | uint8_t status; /* Status register. */
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| 64 | uint8_t error; /* Error register. */
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| 65 | uint8_t sec_no; /* Sector number register. */
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| 66 | uint8_t cyl_lo; /* Cylinder low register. */
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| 67 | uint8_t cyl_hi; /* Cylinder high register. */
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| 68 | uint8_t dev_hd; /* Device/head register. */
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| 69 | uint8_t sec_no_exp; /* Expanded sector number register. */
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| 70 | uint8_t cyl_lo_exp; /* Expanded cylinder low register. */
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| 71 | uint8_t cyl_hi_exp; /* Expanded cylinder high register. */
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| 72 | uint8_t resvd0;
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| 73 | uint8_t sec_cn; /* Sector count register. */
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| 74 | uint8_t sec_cn_exp; /* Expanded sector count register. */
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| 75 | uint16_t resvd1;
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| 76 | uint32_t resvd2;
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| 77 | } fis_d2h;
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| 78 |
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| 79 | ct_assert(sizeof(fis_d2h) == 20);
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| 80 |
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| 81 | /**
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[38848] | 82 | * AHCI controller data.
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| 83 | */
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| 84 | typedef struct
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| 85 | {
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| 86 | /** The AHCI command list as defined by chapter 4.2.2 of the Intel AHCI spec.
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| 87 | * Because the BIOS doesn't support NCQ only the first command header is defined
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| 88 | * to save memory. - Must be aligned on a 1K boundary.
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| 89 | */
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[38897] | 90 | uint32_t aCmdHdr[0x8];
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[38848] | 91 | /** Align the next structure on a 128 byte boundary. */
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| 92 | uint8_t abAlignment1[0x60];
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| 93 | /** The command table of one request as defined by chapter 4.2.3 of the Intel AHCI spec.
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| 94 | * Must be aligned on 128 byte boundary.
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| 95 | */
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[39560] | 96 | uint8_t abCmd[0x40];
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| 97 | /** The ATAPI command region.
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| 98 | * Located 40h bytes after the beginning of the CFIS (Command FIS).
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| 99 | */
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| 100 | uint8_t abAcmd[0x20];
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| 101 | /** Align the PRDT structure on a 128 byte boundary. */
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| 102 | uint8_t abAlignment2[0x20];
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[38899] | 103 | /** Physical Region Descriptor Table (PRDT) array. In other
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| 104 | * words, a scatter/gather descriptor list.
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| 105 | */
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| 106 | ahci_prdt aPrdt[16];
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[38848] | 107 | /** Memory for the received command FIS area as specified by chapter 4.2.1
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| 108 | * of the Intel AHCI spec. This area is normally 256 bytes big but to save memory
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| 109 | * only the first 96 bytes are used because it is assumed that the controller
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| 110 | * never writes to the UFIS or reserved area. - Must be aligned on a 256byte boundary.
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| 111 | */
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| 112 | uint8_t abFisRecv[0x60];
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| 113 | /** Base I/O port for the index/data register pair. */
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| 114 | uint16_t iobase;
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| 115 | /** Current port which uses the memory to communicate with the controller. */
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[39372] | 116 | uint8_t cur_port;
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[39597] | 117 | /** Current PRD index (for pre/post skip). */
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| 118 | uint8_t cur_prd;
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[39610] | 119 | /** Saved high bits of EAX. */
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| 120 | uint16_t saved_eax_hi;
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[38899] | 121 | /** VDS EDDS DMA buffer descriptor structure. */
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| 122 | vds_edds edds;
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| 123 | vds_sg edds_more_sg[NUM_EDDS_SG - 1];
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[38848] | 124 | } ahci_t;
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| 125 |
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[39596] | 126 | /* The AHCI specific data must fit into 1KB (statically allocated). */
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| 127 | ct_assert(sizeof(ahci_t) <= 1024);
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[38848] | 128 |
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| 129 | /** PCI configuration fields. */
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| 130 | #define PCI_CONFIG_CAP 0x34
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| 131 |
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| 132 | #define PCI_CAP_ID_SATACR 0x12
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| 133 | #define VBOX_AHCI_NO_DEVICE 0xffff
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| 134 |
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| 135 | #define RT_BIT_32(bit) ((uint32_t)(1L << (bit)))
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| 136 |
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| 137 | /** Global register set. */
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| 138 | #define AHCI_HBA_SIZE 0x100
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| 139 |
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[63562] | 140 | /// @todo what are the casts good for?
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[38848] | 141 | #define AHCI_REG_CAP ((uint32_t)0x00)
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| 142 | #define AHCI_REG_GHC ((uint32_t)0x04)
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| 143 | # define AHCI_GHC_AE RT_BIT_32(31)
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| 144 | # define AHCI_GHC_IR RT_BIT_32(1)
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| 145 | # define AHCI_GHC_HR RT_BIT_32(0)
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| 146 | #define AHCI_REG_IS ((uint32_t)0x08)
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| 147 | #define AHCI_REG_PI ((uint32_t)0x0c)
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| 148 | #define AHCI_REG_VS ((uint32_t)0x10)
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| 149 |
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| 150 | /** Per port register set. */
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| 151 | #define AHCI_PORT_SIZE 0x80
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| 152 |
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| 153 | #define AHCI_REG_PORT_CLB 0x00
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| 154 | #define AHCI_REG_PORT_CLBU 0x04
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| 155 | #define AHCI_REG_PORT_FB 0x08
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| 156 | #define AHCI_REG_PORT_FBU 0x0c
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| 157 | #define AHCI_REG_PORT_IS 0x10
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| 158 | # define AHCI_REG_PORT_IS_DHRS RT_BIT_32(0)
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[39590] | 159 | # define AHCI_REG_PORT_IS_TFES RT_BIT_32(30)
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[38848] | 160 | #define AHCI_REG_PORT_IE 0x14
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| 161 | #define AHCI_REG_PORT_CMD 0x18
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| 162 | # define AHCI_REG_PORT_CMD_ST RT_BIT_32(0)
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| 163 | # define AHCI_REG_PORT_CMD_FRE RT_BIT_32(4)
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| 164 | # define AHCI_REG_PORT_CMD_FR RT_BIT_32(14)
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| 165 | # define AHCI_REG_PORT_CMD_CR RT_BIT_32(15)
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| 166 | #define AHCI_REG_PORT_TFD 0x20
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| 167 | #define AHCI_REG_PORT_SIG 0x24
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| 168 | #define AHCI_REG_PORT_SSTS 0x28
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| 169 | #define AHCI_REG_PORT_SCTL 0x2c
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| 170 | #define AHCI_REG_PORT_SERR 0x30
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| 171 | #define AHCI_REG_PORT_SACT 0x34
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| 172 | #define AHCI_REG_PORT_CI 0x38
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| 173 |
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| 174 | /** Returns the absolute register offset from a given port and port register. */
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[39619] | 175 | #define AHCI_PORT_REG(port, reg) (AHCI_HBA_SIZE + (port) * AHCI_PORT_SIZE + (reg))
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[38848] | 176 |
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| 177 | #define AHCI_REG_IDX 0
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| 178 | #define AHCI_REG_DATA 4
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| 179 |
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| 180 | /** Writes the given value to a AHCI register. */
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[39619] | 181 | #define AHCI_WRITE_REG(iobase, reg, val) \
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| 182 | outpd((iobase) + AHCI_REG_IDX, reg); \
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| 183 | outpd((iobase) + AHCI_REG_DATA, val)
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[38848] | 184 |
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| 185 | /** Reads from a AHCI register. */
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[39619] | 186 | #define AHCI_READ_REG(iobase, reg, val) \
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| 187 | outpd((iobase) + AHCI_REG_IDX, reg); \
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[38848] | 188 | (val) = inpd((iobase) + AHCI_REG_DATA)
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| 189 |
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| 190 | /** Writes to the given port register. */
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| 191 | #define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val) \
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| 192 | AHCI_WRITE_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
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| 193 |
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| 194 | /** Reads from the given port register. */
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| 195 | #define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val) \
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| 196 | AHCI_READ_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
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| 197 |
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| 198 | #define ATA_CMD_IDENTIFY_DEVICE 0xEC
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[39560] | 199 | #define ATA_CMD_IDENTIFY_PACKET 0xA1
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| 200 | #define ATA_CMD_PACKET 0xA0
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[38848] | 201 | #define AHCI_CMD_READ_DMA_EXT 0x25
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| 202 | #define AHCI_CMD_WRITE_DMA_EXT 0x35
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| 203 |
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| 204 |
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| 205 | /* Warning: Destroys high bits of EAX. */
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| 206 | uint32_t inpd(uint16_t port);
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| 207 | #pragma aux inpd = \
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| 208 | ".386" \
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| 209 | "in eax, dx" \
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| 210 | "mov dx, ax" \
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| 211 | "shr eax, 16" \
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| 212 | "xchg ax, dx" \
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| 213 | parm [dx] value [dx ax] modify nomemory;
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| 214 |
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[39610] | 215 | /* Warning: Destroys high bits of EAX. */
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[38848] | 216 | void outpd(uint16_t port, uint32_t val);
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| 217 | #pragma aux outpd = \
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| 218 | ".386" \
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| 219 | "xchg ax, cx" \
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| 220 | "shl eax, 16" \
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| 221 | "mov ax, cx" \
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| 222 | "out dx, eax" \
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| 223 | parm [dx] [cx ax] modify nomemory;
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| 224 |
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| 225 |
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[39610] | 226 | /* Machinery to save/restore high bits of EAX. 32-bit port I/O needs to use
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| 227 | * EAX, but saving/restoring EAX around each port access would be inefficient.
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| 228 | * Instead, each externally callable routine must save the high bits before
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| 229 | * modifying them and restore the high bits before exiting.
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| 230 | */
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| 231 |
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| 232 | /* Note: Reading high EAX bits destroys them - *must* be restored later. */
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| 233 | uint16_t eax_hi_rd(void);
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| 234 | #pragma aux eax_hi_rd = \
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| 235 | ".386" \
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| 236 | "shr eax, 16" \
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| 237 | value [ax] modify nomemory;
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| 238 |
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| 239 | void eax_hi_wr(uint16_t);
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| 240 | #pragma aux eax_hi_wr = \
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| 241 | ".386" \
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| 242 | "shl eax, 16" \
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| 243 | parm [ax] modify nomemory;
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| 244 |
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[58818] | 245 | void inline high_bits_save(ahci_t __far *ahci)
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[39610] | 246 | {
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| 247 | ahci->saved_eax_hi = eax_hi_rd();
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| 248 | }
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| 249 |
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[58818] | 250 | void inline high_bits_restore(ahci_t __far *ahci)
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[39610] | 251 | {
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| 252 | eax_hi_wr(ahci->saved_eax_hi);
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| 253 | }
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| 254 |
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[38848] | 255 | /**
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| 256 | * Sets a given set of bits in a register.
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| 257 | */
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[58818] | 258 | static void inline ahci_ctrl_set_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
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[38848] | 259 | {
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| 260 | outpd(iobase + AHCI_REG_IDX, reg);
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| 261 | outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) | mask);
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| 262 | }
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| 263 |
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| 264 | /**
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| 265 | * Clears a given set of bits in a register.
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| 266 | */
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[58818] | 267 | static void inline ahci_ctrl_clear_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
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[38848] | 268 | {
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| 269 | outpd(iobase + AHCI_REG_IDX, reg);
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| 270 | outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
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| 271 | }
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| 272 |
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| 273 | /**
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| 274 | * Returns whether at least one of the bits in the given mask is set
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| 275 | * for a register.
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| 276 | */
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[58818] | 277 | static uint8_t inline ahci_ctrl_is_bit_set(uint16_t iobase, uint16_t reg, uint32_t mask)
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[38848] | 278 | {
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| 279 | outpd(iobase + AHCI_REG_IDX, reg);
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| 280 | return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
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| 281 | }
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| 282 |
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| 283 | /**
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| 284 | * Extracts a range of bits from a register and shifts them
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| 285 | * to the right.
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| 286 | */
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| 287 | static uint16_t ahci_ctrl_extract_bits(uint32_t val, uint32_t mask, uint8_t shift)
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| 288 | {
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| 289 | return (val & mask) >> shift;
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| 290 | }
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| 291 |
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| 292 | /**
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| 293 | * Converts a segment:offset pair into a 32bit physical address.
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| 294 | */
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| 295 | static uint32_t ahci_addr_to_phys(void __far *ptr)
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| 296 | {
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| 297 | return ((uint32_t)FP_SEG(ptr) << 4) + FP_OFF(ptr);
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| 298 | }
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| 299 |
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| 300 | /**
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| 301 | * Issues a command to the SATA controller and waits for completion.
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| 302 | */
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[39597] | 303 | static void ahci_port_cmd_sync(ahci_t __far *ahci, uint8_t val)
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[38848] | 304 | {
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[39375] | 305 | uint16_t io_base;
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| 306 | uint8_t port;
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[38848] | 307 |
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[39375] | 308 | port = ahci->cur_port;
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| 309 | io_base = ahci->iobase;
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[38848] | 310 |
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[39375] | 311 | if (port != 0xff)
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[38848] | 312 | {
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| 313 | /* Prepare the command header. */
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[39597] | 314 | ahci->aCmdHdr[0] = ((uint32_t)ahci->cur_prd << 16) | RT_BIT_32(7) | val;
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| 315 | ahci->aCmdHdr[1] = 0;
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[38897] | 316 | ahci->aCmdHdr[2] = ahci_addr_to_phys(&ahci->abCmd[0]);
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[38848] | 317 |
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| 318 | /* Enable Command and FIS receive engine. */
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[39375] | 319 | ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
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[38848] | 320 | AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
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| 321 |
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| 322 | /* Queue command. */
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[39375] | 323 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CI, 0x1);
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[38848] | 324 |
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| 325 | /* Wait for a D2H FIS. */
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[39583] | 326 | DBG_AHCI("AHCI: Waiting for D2H FIS\n");
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[39375] | 327 | while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
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[39590] | 328 | AHCI_REG_PORT_IS_DHRS | AHCI_REG_PORT_IS_TFES) == 0)
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[38848] | 329 | {
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| 330 | // This is where we'd need some kind of a yield functionality...
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| 331 | }
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| 332 |
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[39375] | 333 | ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
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[38848] | 334 | AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
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| 335 |
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| 336 | /* Disable command engine. */
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[39375] | 337 | ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
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[38848] | 338 | AHCI_REG_PORT_CMD_ST);
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[55206] | 339 | /* Caller must examine status. */
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[38848] | 340 | }
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| 341 | else
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[39583] | 342 | DBG_AHCI("AHCI: Invalid port given\n");
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[38848] | 343 | }
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| 344 |
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| 345 | /**
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| 346 | * Issue command to device.
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| 347 | */
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[55206] | 348 | static uint16_t ahci_cmd_data(bio_dsk_t __far *bios_dsk, uint8_t cmd)
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[38848] | 349 | {
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[39375] | 350 | ahci_t __far *ahci = bios_dsk->ahci_seg :> 0;
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| 351 | uint16_t n_sect = bios_dsk->drqp.nsect;
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[39560] | 352 | uint16_t sectsz = bios_dsk->drqp.sect_sz;
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[55206] | 353 | fis_d2h __far *d2h;
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[104068] | 354 | int i;
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[38848] | 355 |
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| 356 | _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
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| 357 |
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| 358 | /* Prepare the FIS. */
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[39375] | 359 | ahci->abCmd[0] = 0x27; /* FIS type H2D. */
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| 360 | ahci->abCmd[1] = 1 << 7; /* Command update. */
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| 361 | ahci->abCmd[2] = cmd;
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| 362 | ahci->abCmd[3] = 0;
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[38848] | 363 |
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[39375] | 364 | ahci->abCmd[4] = bios_dsk->drqp.lba & 0xff;
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| 365 | ahci->abCmd[5] = (bios_dsk->drqp.lba >> 8) & 0xff;
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| 366 | ahci->abCmd[6] = (bios_dsk->drqp.lba >> 16) & 0xff;
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| 367 | ahci->abCmd[7] = RT_BIT_32(6); /* LBA access. */
|
---|
[38848] | 368 |
|
---|
[39375] | 369 | ahci->abCmd[8] = (bios_dsk->drqp.lba >> 24) & 0xff;
|
---|
[58724] | 370 | ahci->abCmd[9] = (bios_dsk->drqp.lba >> 32) & 0xff;
|
---|
| 371 | ahci->abCmd[10] = (bios_dsk->drqp.lba >> 40) & 0xff;
|
---|
[39375] | 372 | ahci->abCmd[11] = 0;
|
---|
[38848] | 373 |
|
---|
[39375] | 374 | ahci->abCmd[12] = (uint8_t)(n_sect & 0xff);
|
---|
| 375 | ahci->abCmd[13] = (uint8_t)((n_sect >> 8) & 0xff);
|
---|
[38848] | 376 |
|
---|
[38899] | 377 | /* Lock memory needed for DMA. */
|
---|
| 378 | ahci->edds.num_avail = NUM_EDDS_SG;
|
---|
[89364] | 379 | DBG_AHCI("AHCI: S/G list for %lu bytes\n", (uint32_t)n_sect * sectsz);
|
---|
[39560] | 380 | vds_build_sg_list(&ahci->edds, bios_dsk->drqp.buffer, (uint32_t)n_sect * sectsz);
|
---|
[38848] | 381 |
|
---|
[38899] | 382 | /* Set up the PRDT. */
|
---|
[104068] | 383 | for (i = 0; i < ahci->edds.num_used; ++i)
|
---|
| 384 | {
|
---|
| 385 | ahci->aPrdt[ahci->cur_prd].len = ahci->edds.u.sg[i].size - 1;
|
---|
| 386 | ahci->aPrdt[ahci->cur_prd].phys_addr = ahci->edds.u.sg[i].phys_addr;
|
---|
| 387 | ++ahci->cur_prd;
|
---|
| 388 | }
|
---|
[38899] | 389 |
|
---|
[58818] | 390 | #if DEBUG_AHCI
|
---|
| 391 | {
|
---|
| 392 | uint16_t prdt_idx;
|
---|
[39597] | 393 |
|
---|
[58818] | 394 | for (prdt_idx = 0; prdt_idx < ahci->cur_prd; ++prdt_idx) {
|
---|
| 395 | DBG_AHCI("S/G entry %u: %5lu bytes @ %08lX\n", prdt_idx,
|
---|
| 396 | ahci->aPrdt[prdt_idx].len + 1, ahci->aPrdt[prdt_idx].phys_addr);
|
---|
| 397 | }
|
---|
[39610] | 398 | }
|
---|
| 399 | #endif
|
---|
| 400 |
|
---|
[39597] | 401 | /* Build variable part of first command DWORD (reuses 'cmd'). */
|
---|
[39375] | 402 | if (cmd == AHCI_CMD_WRITE_DMA_EXT)
|
---|
[39596] | 403 | cmd = RT_BIT_32(6); /* Indicate a write to device. */
|
---|
[39560] | 404 | else if (cmd == ATA_CMD_PACKET) {
|
---|
| 405 | cmd |= RT_BIT_32(5); /* Indicate ATAPI command. */
|
---|
| 406 | ahci->abCmd[3] |= 1; /* DMA transfers. */
|
---|
| 407 | } else
|
---|
[39375] | 408 | cmd = 0;
|
---|
[38899] | 409 |
|
---|
[39560] | 410 | cmd |= 5; /* Five DWORDs. */
|
---|
[39375] | 411 |
|
---|
[39597] | 412 | ahci_port_cmd_sync(ahci, cmd);
|
---|
[39375] | 413 |
|
---|
[55206] | 414 | /* Examine operation status. */
|
---|
| 415 | d2h = (void __far *)&ahci->abFisRecv[0x40];
|
---|
| 416 | DBG_AHCI("AHCI: ERR=%02x, STAT=%02x, SCNT=%02x\n", d2h->error, d2h->status, d2h->sec_cn);
|
---|
| 417 |
|
---|
[38899] | 418 | /* Unlock the buffer again. */
|
---|
[39375] | 419 | vds_free_sg_list(&ahci->edds);
|
---|
[55206] | 420 | return d2h->error ? 4 : 0;
|
---|
[38848] | 421 | }
|
---|
| 422 |
|
---|
| 423 | /**
|
---|
| 424 | * Deinits the curent active port.
|
---|
| 425 | */
|
---|
[39375] | 426 | static void ahci_port_deinit_current(ahci_t __far *ahci)
|
---|
[38848] | 427 | {
|
---|
[39375] | 428 | uint16_t io_base;
|
---|
| 429 | uint8_t port;
|
---|
[38848] | 430 |
|
---|
[39375] | 431 | io_base = ahci->iobase;
|
---|
| 432 | port = ahci->cur_port;
|
---|
[38848] | 433 |
|
---|
[39375] | 434 | if (port != 0xff)
|
---|
[38848] | 435 | {
|
---|
| 436 | /* Put the port into an idle state. */
|
---|
[39375] | 437 | ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
|
---|
[38848] | 438 | AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
|
---|
| 439 |
|
---|
[39375] | 440 | while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
|
---|
[38848] | 441 | AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
|
---|
| 442 | {
|
---|
[39583] | 443 | DBG_AHCI("AHCI: Waiting for the port to idle\n");
|
---|
[38848] | 444 | }
|
---|
| 445 |
|
---|
| 446 | /*
|
---|
| 447 | * Port idles, set up memory for commands and received FIS and program the
|
---|
| 448 | * address registers.
|
---|
| 449 | */
|
---|
[63562] | 450 | /// @todo merge memsets?
|
---|
[38899] | 451 | _fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
|
---|
| 452 | _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
|
---|
| 453 | _fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
|
---|
[38848] | 454 |
|
---|
[39375] | 455 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FB, 0);
|
---|
| 456 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FBU, 0);
|
---|
[38848] | 457 |
|
---|
[39375] | 458 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLB, 0);
|
---|
| 459 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLBU, 0);
|
---|
[38848] | 460 |
|
---|
| 461 | /* Disable all interrupts. */
|
---|
[39375] | 462 | VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_IE, 0);
|
---|
[38848] | 463 |
|
---|
[39372] | 464 | ahci->cur_port = 0xff;
|
---|
[38848] | 465 | }
|
---|
| 466 | }
|
---|
| 467 |
|
---|
| 468 | /**
|
---|
| 469 | * Brings a port into a minimal state to make device detection possible
|
---|
| 470 | * or to queue requests.
|
---|
| 471 | */
|
---|
[39375] | 472 | static void ahci_port_init(ahci_t __far *ahci, uint8_t u8Port)
|
---|
[38848] | 473 | {
|
---|
| 474 | /* Deinit any other port first. */
|
---|
[39375] | 475 | ahci_port_deinit_current(ahci);
|
---|
[38848] | 476 |
|
---|
| 477 | /* Put the port into an idle state. */
|
---|
[39375] | 478 | ahci_ctrl_clear_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
|
---|
[38848] | 479 | AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
|
---|
| 480 |
|
---|
[39375] | 481 | while (ahci_ctrl_is_bit_set(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
|
---|
[38848] | 482 | AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
|
---|
| 483 | {
|
---|
[39583] | 484 | DBG_AHCI("AHCI: Waiting for the port to idle\n");
|
---|
[38848] | 485 | }
|
---|
| 486 |
|
---|
| 487 | /*
|
---|
| 488 | * Port idles, set up memory for commands and received FIS and program the
|
---|
| 489 | * address registers.
|
---|
| 490 | */
|
---|
[63562] | 491 | /// @todo just one memset?
|
---|
[38897] | 492 | _fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
|
---|
[38848] | 493 | _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
|
---|
| 494 | _fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
|
---|
| 495 |
|
---|
[39583] | 496 | DBG_AHCI("AHCI: FIS receive area %lx from %x:%x\n",
|
---|
[39596] | 497 | ahci_addr_to_phys(&ahci->abFisRecv), FP_SEG(ahci->abFisRecv), FP_OFF(ahci->abFisRecv));
|
---|
[39375] | 498 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FB, ahci_addr_to_phys(&ahci->abFisRecv));
|
---|
| 499 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FBU, 0);
|
---|
[38848] | 500 |
|
---|
[39583] | 501 | DBG_AHCI("AHCI: CMD list area %lx\n", ahci_addr_to_phys(&ahci->aCmdHdr));
|
---|
[39375] | 502 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLB, ahci_addr_to_phys(&ahci->aCmdHdr));
|
---|
| 503 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLBU, 0);
|
---|
[38848] | 504 |
|
---|
| 505 | /* Disable all interrupts. */
|
---|
[39375] | 506 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IE, 0);
|
---|
| 507 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IS, 0xffffffff);
|
---|
[38848] | 508 | /* Clear all errors. */
|
---|
[39375] | 509 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
|
---|
[38848] | 510 |
|
---|
[39372] | 511 | ahci->cur_port = u8Port;
|
---|
[39597] | 512 | ahci->cur_prd = 0;
|
---|
[38848] | 513 | }
|
---|
| 514 |
|
---|
| 515 | /**
|
---|
[39372] | 516 | * Read sectors from an attached AHCI device.
|
---|
| 517 | *
|
---|
| 518 | * @returns status code.
|
---|
[48123] | 519 | * @param bios_dsk Pointer to disk request packet (in the
|
---|
[39372] | 520 | * EBDA).
|
---|
[38848] | 521 | */
|
---|
[39372] | 522 | int ahci_read_sectors(bio_dsk_t __far *bios_dsk)
|
---|
[38848] | 523 | {
|
---|
[39372] | 524 | uint16_t device_id;
|
---|
[55206] | 525 | uint16_t rc;
|
---|
[38848] | 526 |
|
---|
[42811] | 527 | device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
|
---|
[39372] | 528 | if (device_id > BX_MAX_AHCI_DEVICES)
|
---|
[39560] | 529 | BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
|
---|
[39372] | 530 |
|
---|
[58724] | 531 | DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
|
---|
| 532 | bios_dsk->drqp.nsect, bios_dsk->drqp.lba,
|
---|
| 533 | device_id, bios_dsk->ahcidev[device_id].port);
|
---|
[39560] | 534 |
|
---|
[39610] | 535 | high_bits_save(bios_dsk->ahci_seg :> 0);
|
---|
[39375] | 536 | ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
|
---|
[55206] | 537 | rc = ahci_cmd_data(bios_dsk, AHCI_CMD_READ_DMA_EXT);
|
---|
[42968] | 538 | DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
|
---|
| 539 | bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
|
---|
[39372] | 540 | #ifdef DMA_WORKAROUND
|
---|
[39375] | 541 | rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.nsect * 512 / 2);
|
---|
[39372] | 542 | #endif
|
---|
[39610] | 543 | high_bits_restore(bios_dsk->ahci_seg :> 0);
|
---|
[55206] | 544 | return rc;
|
---|
[38848] | 545 | }
|
---|
| 546 |
|
---|
| 547 | /**
|
---|
[39372] | 548 | * Write sectors to an attached AHCI device.
|
---|
| 549 | *
|
---|
| 550 | * @returns status code.
|
---|
[48123] | 551 | * @param bios_dsk Pointer to disk request packet (in the
|
---|
[39372] | 552 | * EBDA).
|
---|
[38848] | 553 | */
|
---|
[39372] | 554 | int ahci_write_sectors(bio_dsk_t __far *bios_dsk)
|
---|
[38848] | 555 | {
|
---|
[39372] | 556 | uint16_t device_id;
|
---|
[55206] | 557 | uint16_t rc;
|
---|
[38848] | 558 |
|
---|
[42811] | 559 | device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
|
---|
[39372] | 560 | if (device_id > BX_MAX_AHCI_DEVICES)
|
---|
[39560] | 561 | BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
|
---|
[39372] | 562 |
|
---|
[58724] | 563 | DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
|
---|
[39583] | 564 | bios_dsk->drqp.nsect, bios_dsk->drqp.lba, device_id,
|
---|
| 565 | bios_dsk->ahcidev[device_id].port);
|
---|
[39560] | 566 |
|
---|
[39610] | 567 | high_bits_save(bios_dsk->ahci_seg :> 0);
|
---|
[39375] | 568 | ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
|
---|
[55206] | 569 | rc = ahci_cmd_data(bios_dsk, AHCI_CMD_WRITE_DMA_EXT);
|
---|
[42968] | 570 | DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
|
---|
| 571 | bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
|
---|
[39610] | 572 | high_bits_restore(bios_dsk->ahci_seg :> 0);
|
---|
[55206] | 573 | return rc;
|
---|
[38848] | 574 | }
|
---|
| 575 |
|
---|
[63562] | 576 | /// @todo move
|
---|
[39560] | 577 | #define ATA_DATA_NO 0x00
|
---|
| 578 | #define ATA_DATA_IN 0x01
|
---|
| 579 | #define ATA_DATA_OUT 0x02
|
---|
| 580 |
|
---|
[48123] | 581 | uint16_t ahci_cmd_packet(uint16_t device_id, uint8_t cmdlen, char __far *cmdbuf,
|
---|
[89364] | 582 | uint32_t length, uint8_t inout, char __far *buffer)
|
---|
[39560] | 583 | {
|
---|
| 584 | bio_dsk_t __far *bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
|
---|
[39610] | 585 | ahci_t __far *ahci;
|
---|
[39560] | 586 |
|
---|
| 587 | /* Data out is currently not supported. */
|
---|
| 588 | if (inout == ATA_DATA_OUT) {
|
---|
| 589 | BX_INFO("%s: DATA_OUT not supported yet\n", __func__);
|
---|
| 590 | return 1;
|
---|
| 591 | }
|
---|
| 592 |
|
---|
| 593 | /* Convert to AHCI specific device number. */
|
---|
[42811] | 594 | device_id = VBOX_GET_AHCI_DEVICE(device_id);
|
---|
[39560] | 595 |
|
---|
[89364] | 596 | DBG_AHCI("%s: reading %lu bytes, device %d, port %d\n", __func__,
|
---|
| 597 | length, device_id, bios_dsk->ahcidev[device_id].port);
|
---|
[39583] | 598 | DBG_AHCI("%s: reading %u %u-byte sectors\n", __func__,
|
---|
| 599 | bios_dsk->drqp.nsect, bios_dsk->drqp.sect_sz);
|
---|
[39560] | 600 |
|
---|
[63562] | 601 | bios_dsk->drqp.lba = length << 8; /// @todo xfer length limit
|
---|
[39560] | 602 | bios_dsk->drqp.buffer = buffer;
|
---|
[39591] | 603 | bios_dsk->drqp.nsect = length / bios_dsk->drqp.sect_sz;
|
---|
[39583] | 604 | // bios_dsk->drqp.sect_sz = 2048;
|
---|
[39560] | 605 |
|
---|
[39610] | 606 | ahci = bios_dsk->ahci_seg :> 0;
|
---|
| 607 | high_bits_save(ahci);
|
---|
| 608 |
|
---|
[39560] | 609 | ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
|
---|
| 610 |
|
---|
| 611 | /* Copy the ATAPI command where the HBA can fetch it. */
|
---|
| 612 | _fmemcpy(ahci->abAcmd, cmdbuf, cmdlen);
|
---|
| 613 |
|
---|
| 614 | /* Reset transferred counts. */
|
---|
[63562] | 615 | /// @todo clear in calling code?
|
---|
[39560] | 616 | bios_dsk->drqp.trsfsectors = 0;
|
---|
| 617 | bios_dsk->drqp.trsfbytes = 0;
|
---|
| 618 |
|
---|
| 619 | ahci_cmd_data(bios_dsk, ATA_CMD_PACKET);
|
---|
[39583] | 620 | DBG_AHCI("%s: transferred %lu bytes\n", __func__, ahci->aCmdHdr[1]);
|
---|
[39573] | 621 | bios_dsk->drqp.trsfbytes = ahci->aCmdHdr[1];
|
---|
[39560] | 622 | #ifdef DMA_WORKAROUND
|
---|
[39573] | 623 | rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.trsfbytes / 2);
|
---|
[39560] | 624 | #endif
|
---|
[39610] | 625 | high_bits_restore(ahci);
|
---|
| 626 |
|
---|
[39560] | 627 | return ahci->aCmdHdr[1] == 0 ? 4 : 0;
|
---|
| 628 | }
|
---|
| 629 |
|
---|
[43483] | 630 | void ahci_port_detect_device(ahci_t __far *ahci, uint8_t u8Port)
|
---|
[38848] | 631 | {
|
---|
[68611] | 632 | uint32_t val;
|
---|
| 633 | bio_dsk_t __far *bios_dsk;
|
---|
| 634 | volatile uint32_t __far *ticks;
|
---|
| 635 | uint32_t end_tick;
|
---|
| 636 | int device_found = 0;
|
---|
[38848] | 637 |
|
---|
[39375] | 638 | ahci_port_init(ahci, u8Port);
|
---|
[38848] | 639 |
|
---|
[39372] | 640 | bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
|
---|
| 641 |
|
---|
[38848] | 642 | /* Reset connection. */
|
---|
[39375] | 643 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0x01);
|
---|
[38848] | 644 | /*
|
---|
| 645 | * According to the spec we should wait at least 1msec until the reset
|
---|
| 646 | * is cleared but this is a virtual controller so we don't have to.
|
---|
| 647 | */
|
---|
[39375] | 648 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0);
|
---|
[38848] | 649 |
|
---|
[68611] | 650 | /*
|
---|
| 651 | * We do however have to wait for the device to initialize (the port reset
|
---|
| 652 | * to complete). That can take up to 10ms according to the SATA spec (device
|
---|
| 653 | * must send COMINIT within 10ms of COMRESET). We should be generous with
|
---|
| 654 | * the wait because in the typical case there are no ports without a device
|
---|
| 655 | * attached.
|
---|
| 656 | */
|
---|
| 657 | ticks = MK_FP( 0x40, 0x6C );
|
---|
| 658 | end_tick = *ticks + 3; /* Wait up to five BIOS ticks, something in 150ms range. */
|
---|
[51232] | 659 |
|
---|
[68611] | 660 | while( *ticks < end_tick )
|
---|
[51232] | 661 | {
|
---|
[68611] | 662 | /* If PxSSTS.DET is 3, everything went fine. */
|
---|
[51232] | 663 | VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
|
---|
[68611] | 664 | if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 3) {
|
---|
| 665 | device_found = 1;
|
---|
| 666 | break;
|
---|
| 667 | }
|
---|
| 668 | }
|
---|
[51232] | 669 |
|
---|
[68611] | 670 | /* Timed out, no device detected. */
|
---|
| 671 | if (!device_found) {
|
---|
| 672 | DBG_AHCI("AHCI: Timed out, no device detected on port %d\n", u8Port);
|
---|
| 673 | return;
|
---|
| 674 | }
|
---|
| 675 |
|
---|
[39375] | 676 | if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 0x3)
|
---|
[38848] | 677 | {
|
---|
[39560] | 678 | uint8_t abBuffer[0x0200];
|
---|
| 679 | uint8_t hdcount, devcount_ahci, hd_index;
|
---|
| 680 | uint8_t cdcount;
|
---|
| 681 | uint8_t removable;
|
---|
[38848] | 682 |
|
---|
[50294] | 683 | /* Clear all errors after the reset. */
|
---|
| 684 | VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
|
---|
| 685 |
|
---|
[39560] | 686 | devcount_ahci = bios_dsk->ahci_devcnt;
|
---|
[39372] | 687 |
|
---|
[39583] | 688 | DBG_AHCI("AHCI: Device detected on port %d\n", u8Port);
|
---|
[38848] | 689 |
|
---|
[63562] | 690 | /// @todo Merge common HD/CDROM detection code
|
---|
[39560] | 691 | if (devcount_ahci < BX_MAX_AHCI_DEVICES)
|
---|
[38848] | 692 | {
|
---|
| 693 | /* Device detected, enable FIS receive. */
|
---|
[39375] | 694 | ahci_ctrl_set_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
|
---|
[38848] | 695 | AHCI_REG_PORT_CMD_FRE);
|
---|
| 696 |
|
---|
| 697 | /* Check signature to determine device type. */
|
---|
[39375] | 698 | VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SIG, val);
|
---|
| 699 | if (val == 0x101)
|
---|
[38848] | 700 | {
|
---|
[58724] | 701 | uint64_t sectors;
|
---|
[42947] | 702 | uint16_t cylinders, heads, spt;
|
---|
[43483] | 703 | chs_t lgeo;
|
---|
[38848] | 704 | uint8_t idxCmosChsBase;
|
---|
| 705 |
|
---|
[39583] | 706 | DBG_AHCI("AHCI: Detected hard disk\n");
|
---|
[38848] | 707 |
|
---|
| 708 | /* Identify device. */
|
---|
[39560] | 709 | bios_dsk->drqp.lba = 0;
|
---|
| 710 | bios_dsk->drqp.buffer = &abBuffer;
|
---|
| 711 | bios_dsk->drqp.nsect = 1;
|
---|
| 712 | bios_dsk->drqp.sect_sz = 512;
|
---|
[39375] | 713 | ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_DEVICE);
|
---|
[38848] | 714 |
|
---|
[39560] | 715 | /* Calculate index into the generic device table. */
|
---|
| 716 | hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
|
---|
[38848] | 717 |
|
---|
[42947] | 718 | removable = *(abBuffer+0) & 0x80 ? 1 : 0;
|
---|
| 719 | cylinders = *(uint16_t *)(abBuffer+(1*2)); // word 1
|
---|
| 720 | heads = *(uint16_t *)(abBuffer+(3*2)); // word 3
|
---|
| 721 | spt = *(uint16_t *)(abBuffer+(6*2)); // word 6
|
---|
| 722 | sectors = *(uint32_t *)(abBuffer+(60*2)); // word 60 and word 61
|
---|
[38848] | 723 |
|
---|
[42947] | 724 | if (sectors == 0x0FFFFFFF) /* For disks bigger than ~128GB */
|
---|
[58724] | 725 | sectors = *(uint64_t *)(abBuffer+(100*2)); // words 100 to 103
|
---|
[38848] | 726 |
|
---|
[58724] | 727 | DBG_AHCI("AHCI: 0x%llx sectors\n", sectors);
|
---|
[38848] | 728 |
|
---|
[39560] | 729 | bios_dsk->ahcidev[devcount_ahci].port = u8Port;
|
---|
[39651] | 730 | bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
|
---|
| 731 | bios_dsk->devices[hd_index].device = DSK_DEVICE_HD;
|
---|
[39560] | 732 | bios_dsk->devices[hd_index].removable = removable;
|
---|
[39372] | 733 | bios_dsk->devices[hd_index].lock = 0;
|
---|
| 734 | bios_dsk->devices[hd_index].blksize = 512;
|
---|
[39651] | 735 | bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_LBA;
|
---|
[42947] | 736 | bios_dsk->devices[hd_index].sectors = sectors;
|
---|
[38848] | 737 |
|
---|
[42947] | 738 | bios_dsk->devices[hd_index].pchs.heads = heads;
|
---|
| 739 | bios_dsk->devices[hd_index].pchs.cylinders = cylinders;
|
---|
| 740 | bios_dsk->devices[hd_index].pchs.spt = spt;
|
---|
[39372] | 741 |
|
---|
[38848] | 742 | /* Get logical CHS geometry. */
|
---|
[43438] | 743 | switch (devcount_ahci)
|
---|
[38848] | 744 | {
|
---|
| 745 | case 0:
|
---|
| 746 | idxCmosChsBase = 0x40;
|
---|
| 747 | break;
|
---|
| 748 | case 1:
|
---|
| 749 | idxCmosChsBase = 0x48;
|
---|
| 750 | break;
|
---|
| 751 | case 2:
|
---|
| 752 | idxCmosChsBase = 0x50;
|
---|
| 753 | break;
|
---|
| 754 | case 3:
|
---|
| 755 | idxCmosChsBase = 0x58;
|
---|
| 756 | break;
|
---|
| 757 | default:
|
---|
| 758 | idxCmosChsBase = 0;
|
---|
| 759 | }
|
---|
[39651] | 760 | if (idxCmosChsBase && inb_cmos(idxCmosChsBase+7))
|
---|
[38848] | 761 | {
|
---|
[92290] | 762 | lgeo.cylinders = get_cmos_word(idxCmosChsBase /*, idxCmosChsBase+1*/);
|
---|
[43483] | 763 | lgeo.heads = inb_cmos(idxCmosChsBase + 2);
|
---|
| 764 | lgeo.spt = inb_cmos(idxCmosChsBase + 7);
|
---|
[38848] | 765 | }
|
---|
| 766 | else
|
---|
[43483] | 767 | set_geom_lba(&lgeo, sectors); /* Default EDD-style translated LBA geometry. */
|
---|
| 768 |
|
---|
[58724] | 769 | BX_INFO("AHCI %d-P#%d: PCHS=%u/%u/%u LCHS=%u/%u/%u 0x%llx sectors\n", devcount_ahci,
|
---|
| 770 | u8Port, cylinders, heads, spt, lgeo.cylinders, lgeo.heads, lgeo.spt,
|
---|
| 771 | sectors);
|
---|
[38848] | 772 |
|
---|
[43483] | 773 | bios_dsk->devices[hd_index].lchs = lgeo;
|
---|
[38848] | 774 |
|
---|
[39560] | 775 | /* Store the ID of the disk in the BIOS hdidmap. */
|
---|
[39372] | 776 | hdcount = bios_dsk->hdcount;
|
---|
[39560] | 777 | bios_dsk->hdidmap[hdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
|
---|
[39372] | 778 | hdcount++;
|
---|
| 779 | bios_dsk->hdcount = hdcount;
|
---|
| 780 |
|
---|
[38848] | 781 | /* Update hdcount in the BDA. */
|
---|
[39372] | 782 | hdcount = read_byte(0x40, 0x75);
|
---|
| 783 | hdcount++;
|
---|
[48123] | 784 | write_byte(0x40, 0x75, hdcount);
|
---|
[38848] | 785 | }
|
---|
| 786 | else if (val == 0xeb140101)
|
---|
| 787 | {
|
---|
[39583] | 788 | DBG_AHCI("AHCI: Detected ATAPI device\n");
|
---|
[39560] | 789 |
|
---|
| 790 | /* Identify packet device. */
|
---|
| 791 | bios_dsk->drqp.lba = 0;
|
---|
| 792 | bios_dsk->drqp.buffer = &abBuffer;
|
---|
| 793 | bios_dsk->drqp.nsect = 1;
|
---|
| 794 | bios_dsk->drqp.sect_sz = 512;
|
---|
| 795 | ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_PACKET);
|
---|
| 796 |
|
---|
| 797 | /* Calculate index into the generic device table. */
|
---|
| 798 | hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
|
---|
| 799 |
|
---|
| 800 | removable = *(abBuffer+0) & 0x80 ? 1 : 0;
|
---|
| 801 |
|
---|
[70333] | 802 | bios_dsk->ahcidev[devcount_ahci].port = u8Port;
|
---|
| 803 | bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
|
---|
| 804 | bios_dsk->devices[hd_index].device = DSK_DEVICE_CDROM;
|
---|
| 805 | bios_dsk->devices[hd_index].removable = removable;
|
---|
| 806 | bios_dsk->devices[hd_index].blksize = 2048;
|
---|
| 807 | bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_NONE;
|
---|
[39560] | 808 |
|
---|
| 809 | /* Store the ID of the device in the BIOS cdidmap. */
|
---|
| 810 | cdcount = bios_dsk->cdcount;
|
---|
| 811 | bios_dsk->cdidmap[cdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
|
---|
| 812 | cdcount++;
|
---|
| 813 | bios_dsk->cdcount = cdcount;
|
---|
[38848] | 814 | }
|
---|
| 815 | else
|
---|
[39583] | 816 | DBG_AHCI("AHCI: Ignoring unknown device\n");
|
---|
[38848] | 817 |
|
---|
[39560] | 818 | devcount_ahci++;
|
---|
| 819 | bios_dsk->ahci_devcnt = devcount_ahci;
|
---|
[38848] | 820 | }
|
---|
| 821 | else
|
---|
[39583] | 822 | DBG_AHCI("AHCI: Reached maximum device count, skipping\n");
|
---|
[38848] | 823 | }
|
---|
| 824 | }
|
---|
| 825 |
|
---|
| 826 | /**
|
---|
[39372] | 827 | * Allocates 1K of conventional memory.
|
---|
[38848] | 828 | */
|
---|
| 829 | static uint16_t ahci_mem_alloc(void)
|
---|
| 830 | {
|
---|
| 831 | uint16_t base_mem_kb;
|
---|
| 832 | uint16_t ahci_seg;
|
---|
| 833 |
|
---|
| 834 | base_mem_kb = read_word(0x00, 0x0413);
|
---|
| 835 |
|
---|
[39583] | 836 | DBG_AHCI("AHCI: %dK of base mem\n", base_mem_kb);
|
---|
[38848] | 837 |
|
---|
| 838 | if (base_mem_kb == 0)
|
---|
| 839 | return 0;
|
---|
| 840 |
|
---|
| 841 | base_mem_kb--; /* Allocate one block. */
|
---|
| 842 | ahci_seg = (((uint32_t)base_mem_kb * 1024) >> 4); /* Calculate start segment. */
|
---|
| 843 |
|
---|
| 844 | write_word(0x00, 0x0413, base_mem_kb);
|
---|
| 845 |
|
---|
| 846 | return ahci_seg;
|
---|
| 847 | }
|
---|
| 848 |
|
---|
| 849 | /**
|
---|
| 850 | * Initializes the AHCI HBA and detects attached devices.
|
---|
| 851 | */
|
---|
[39375] | 852 | static int ahci_hba_init(uint16_t io_base)
|
---|
[38848] | 853 | {
|
---|
[39596] | 854 | uint8_t i, cPorts;
|
---|
| 855 | uint32_t val;
|
---|
| 856 | uint16_t ebda_seg;
|
---|
| 857 | uint16_t ahci_seg;
|
---|
| 858 | bio_dsk_t __far *bios_dsk;
|
---|
| 859 | ahci_t __far *ahci;
|
---|
[38848] | 860 |
|
---|
[48123] | 861 |
|
---|
[38848] | 862 | ebda_seg = read_word(0x0040, 0x000E);
|
---|
[39596] | 863 | bios_dsk = ebda_seg :> &EbdaData->bdisk;
|
---|
[38848] | 864 |
|
---|
[39375] | 865 | AHCI_READ_REG(io_base, AHCI_REG_VS, val);
|
---|
[39583] | 866 | DBG_AHCI("AHCI: Controller version: 0x%x (major) 0x%x (minor)\n",
|
---|
| 867 | ahci_ctrl_extract_bits(val, 0xffff0000, 16),
|
---|
| 868 | ahci_ctrl_extract_bits(val, 0x0000ffff, 0));
|
---|
[38848] | 869 |
|
---|
| 870 | /* Allocate 1K of base memory. */
|
---|
| 871 | ahci_seg = ahci_mem_alloc();
|
---|
| 872 | if (ahci_seg == 0)
|
---|
| 873 | {
|
---|
[39583] | 874 | DBG_AHCI("AHCI: Could not allocate 1K of memory, can't boot from controller\n");
|
---|
[38848] | 875 | return 0;
|
---|
| 876 | }
|
---|
[48123] | 877 | DBG_AHCI("AHCI: ahci_seg=%04x, size=%04x, pointer at EBDA:%04x (EBDA size=%04x)\n",
|
---|
[39583] | 878 | ahci_seg, sizeof(ahci_t), (uint16_t)&EbdaData->bdisk.ahci_seg, sizeof(ebda_data_t));
|
---|
[38848] | 879 |
|
---|
[39596] | 880 | bios_dsk->ahci_seg = ahci_seg;
|
---|
| 881 | bios_dsk->ahci_devcnt = 0;
|
---|
[38848] | 882 |
|
---|
[39596] | 883 | ahci = ahci_seg :> 0;
|
---|
| 884 | ahci->cur_port = 0xff;
|
---|
| 885 | ahci->iobase = io_base;
|
---|
| 886 |
|
---|
[38848] | 887 | /* Reset the controller. */
|
---|
[39375] | 888 | ahci_ctrl_set_bits(io_base, AHCI_REG_GHC, AHCI_GHC_HR);
|
---|
[38848] | 889 | do
|
---|
| 890 | {
|
---|
[39375] | 891 | AHCI_READ_REG(io_base, AHCI_REG_GHC, val);
|
---|
[58044] | 892 | } while ((val & AHCI_GHC_HR) != 0);
|
---|
[38848] | 893 |
|
---|
[39375] | 894 | AHCI_READ_REG(io_base, AHCI_REG_CAP, val);
|
---|
[38848] | 895 | cPorts = ahci_ctrl_extract_bits(val, 0x1f, 0) + 1; /* Extract number of ports.*/
|
---|
| 896 |
|
---|
[39583] | 897 | DBG_AHCI("AHCI: HBA has %u ports\n", cPorts);
|
---|
[38848] | 898 |
|
---|
| 899 | /* Go through the ports. */
|
---|
| 900 | i = 0;
|
---|
| 901 | while (i < 32)
|
---|
| 902 | {
|
---|
[39375] | 903 | if (ahci_ctrl_is_bit_set(io_base, AHCI_REG_PI, RT_BIT_32(i)) != 0)
|
---|
[38848] | 904 | {
|
---|
[39583] | 905 | DBG_AHCI("AHCI: Port %u is present\n", i);
|
---|
[39375] | 906 | ahci_port_detect_device(ahci_seg :> 0, i);
|
---|
[38848] | 907 | cPorts--;
|
---|
| 908 | if (cPorts == 0)
|
---|
| 909 | break;
|
---|
| 910 | }
|
---|
| 911 | i++;
|
---|
| 912 | }
|
---|
| 913 |
|
---|
| 914 | return 0;
|
---|
| 915 | }
|
---|
| 916 |
|
---|
| 917 | /**
|
---|
| 918 | * Init the AHCI driver and detect attached disks.
|
---|
| 919 | */
|
---|
| 920 | void BIOSCALL ahci_init(void)
|
---|
| 921 | {
|
---|
| 922 | uint16_t busdevfn;
|
---|
| 923 |
|
---|
| 924 | busdevfn = pci_find_classcode(0x00010601);
|
---|
| 925 | if (busdevfn != VBOX_AHCI_NO_DEVICE)
|
---|
| 926 | {
|
---|
| 927 | uint8_t u8Bus, u8DevFn;
|
---|
| 928 | uint8_t u8PciCapOff;
|
---|
| 929 |
|
---|
| 930 | u8Bus = (busdevfn & 0xff00) >> 8;
|
---|
| 931 | u8DevFn = busdevfn & 0x00ff;
|
---|
| 932 |
|
---|
[39583] | 933 | DBG_AHCI("AHCI HBA at Bus %u DevFn 0x%x (raw 0x%x)\n", u8Bus, u8DevFn, busdevfn);
|
---|
[38848] | 934 |
|
---|
| 935 | /* Examine the capability list and search for the Serial ATA Capability Register. */
|
---|
| 936 | u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
|
---|
| 937 |
|
---|
| 938 | while (u8PciCapOff != 0)
|
---|
| 939 | {
|
---|
| 940 | uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
|
---|
| 941 |
|
---|
[39583] | 942 | DBG_AHCI("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
|
---|
[38848] | 943 |
|
---|
| 944 | if (u8PciCapId == PCI_CAP_ID_SATACR)
|
---|
| 945 | break;
|
---|
| 946 |
|
---|
| 947 | /* Go on to the next capability. */
|
---|
| 948 | u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
|
---|
| 949 | }
|
---|
| 950 |
|
---|
| 951 | if (u8PciCapOff != 0)
|
---|
| 952 | {
|
---|
| 953 | uint8_t u8Rev;
|
---|
| 954 |
|
---|
[39583] | 955 | DBG_AHCI("AHCI HBA with SATA Capability register at 0x%x\n", u8PciCapOff);
|
---|
[38848] | 956 |
|
---|
| 957 | /* Advance to the stuff behind the id and next capability pointer. */
|
---|
| 958 | u8PciCapOff += 2;
|
---|
| 959 |
|
---|
| 960 | u8Rev = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
|
---|
| 961 | if (u8Rev == 0x10)
|
---|
| 962 | {
|
---|
| 963 | /* Read the SATACR1 register and get the bar and offset of the index/data pair register. */
|
---|
| 964 | uint8_t u8Bar = 0x00;
|
---|
| 965 | uint16_t u16Off = 0x00;
|
---|
| 966 | uint16_t u16BarOff = pci_read_config_word(u8Bus, u8DevFn, u8PciCapOff + 2);
|
---|
| 967 |
|
---|
[39583] | 968 | DBG_AHCI("SATACR1: 0x%x\n", u16BarOff);
|
---|
[38848] | 969 |
|
---|
| 970 | switch (u16BarOff & 0xf)
|
---|
| 971 | {
|
---|
| 972 | case 0x04:
|
---|
| 973 | u8Bar = 0x10;
|
---|
| 974 | break;
|
---|
| 975 | case 0x05:
|
---|
| 976 | u8Bar = 0x14;
|
---|
| 977 | break;
|
---|
| 978 | case 0x06:
|
---|
| 979 | u8Bar = 0x18;
|
---|
| 980 | break;
|
---|
| 981 | case 0x07:
|
---|
| 982 | u8Bar = 0x1c;
|
---|
| 983 | break;
|
---|
| 984 | case 0x08:
|
---|
| 985 | u8Bar = 0x20;
|
---|
| 986 | break;
|
---|
| 987 | case 0x09:
|
---|
| 988 | u8Bar = 0x24;
|
---|
| 989 | break;
|
---|
| 990 | case 0x0f:
|
---|
| 991 | default:
|
---|
| 992 | /* Reserved or unsupported. */
|
---|
[39583] | 993 | DBG_AHCI("BAR 0x%x unsupported\n", u16BarOff & 0xf);
|
---|
[38848] | 994 | }
|
---|
| 995 |
|
---|
| 996 | /* Get the offset inside the BAR from bits 4:15. */
|
---|
| 997 | u16Off = (u16BarOff >> 4) * 4;
|
---|
| 998 |
|
---|
| 999 | if (u8Bar != 0x00)
|
---|
| 1000 | {
|
---|
| 1001 | uint32_t u32Bar = pci_read_config_dword(u8Bus, u8DevFn, u8Bar);
|
---|
| 1002 |
|
---|
[39583] | 1003 | DBG_AHCI("BAR at 0x%x : 0x%x\n", u8Bar, u32Bar);
|
---|
[38848] | 1004 |
|
---|
| 1005 | if ((u32Bar & 0x01) != 0)
|
---|
| 1006 | {
|
---|
| 1007 | int rc;
|
---|
| 1008 | uint16_t u16AhciIoBase = (u32Bar & 0xfff0) + u16Off;
|
---|
| 1009 |
|
---|
[67679] | 1010 | /* Enable PCI memory, I/O, bus mastering access in command register. */
|
---|
| 1011 | pci_write_config_word(u8Bus, u8DevFn, 4, 0x7);
|
---|
| 1012 |
|
---|
[39583] | 1013 | DBG_AHCI("I/O base: 0x%x\n", u16AhciIoBase);
|
---|
[38848] | 1014 | rc = ahci_hba_init(u16AhciIoBase);
|
---|
| 1015 | }
|
---|
| 1016 | else
|
---|
[39583] | 1017 | DBG_AHCI("BAR is MMIO\n");
|
---|
[38848] | 1018 | }
|
---|
| 1019 | }
|
---|
| 1020 | else
|
---|
[39583] | 1021 | DBG_AHCI("Invalid revision 0x%x\n", u8Rev);
|
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[38848] | 1022 | }
|
---|
| 1023 | else
|
---|
[39583] | 1024 | DBG_AHCI("AHCI HBA with no usable Index/Data register pair!\n");
|
---|
[38848] | 1025 | }
|
---|
| 1026 | else
|
---|
[39583] | 1027 | DBG_AHCI("No AHCI HBA!\n");
|
---|
[38848] | 1028 | }
|
---|