VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/BIOS/ahci.c@ 98103

Last change on this file since 98103 was 98103, checked in by vboxsync, 16 months ago

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1/* $Id: ahci.c 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * AHCI host adapter driver to boot from SATA disks.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#include <stdint.h>
29#include <string.h>
30#include "biosint.h"
31#include "ebda.h"
32#include "inlines.h"
33#include "pciutil.h"
34#include "vds.h"
35
36#if DEBUG_AHCI
37# define DBG_AHCI(...) BX_INFO(__VA_ARGS__)
38#else
39# define DBG_AHCI(...)
40#endif
41
42/* Number of S/G table entries in EDDS. */
43#define NUM_EDDS_SG 16
44
45
46/**
47 * AHCI PRDT structure.
48 */
49typedef struct
50{
51 uint32_t phys_addr;
52 uint32_t something;
53 uint32_t reserved;
54 uint32_t len;
55} ahci_prdt;
56
57/**
58 * SATA D2H FIS (Device to Host Frame Information Structure).
59 */
60typedef struct {
61 uint8_t fis_type; /* 34h */
62 uint8_t intr; /* Bit 6 indicates interrupt status. */
63 uint8_t status; /* Status register. */
64 uint8_t error; /* Error register. */
65 uint8_t sec_no; /* Sector number register. */
66 uint8_t cyl_lo; /* Cylinder low register. */
67 uint8_t cyl_hi; /* Cylinder high register. */
68 uint8_t dev_hd; /* Device/head register. */
69 uint8_t sec_no_exp; /* Expanded sector number register. */
70 uint8_t cyl_lo_exp; /* Expanded cylinder low register. */
71 uint8_t cyl_hi_exp; /* Expanded cylinder high register. */
72 uint8_t resvd0;
73 uint8_t sec_cn; /* Sector count register. */
74 uint8_t sec_cn_exp; /* Expanded sector count register. */
75 uint16_t resvd1;
76 uint32_t resvd2;
77} fis_d2h;
78
79ct_assert(sizeof(fis_d2h) == 20);
80
81/**
82 * AHCI controller data.
83 */
84typedef struct
85{
86 /** The AHCI command list as defined by chapter 4.2.2 of the Intel AHCI spec.
87 * Because the BIOS doesn't support NCQ only the first command header is defined
88 * to save memory. - Must be aligned on a 1K boundary.
89 */
90 uint32_t aCmdHdr[0x8];
91 /** Align the next structure on a 128 byte boundary. */
92 uint8_t abAlignment1[0x60];
93 /** The command table of one request as defined by chapter 4.2.3 of the Intel AHCI spec.
94 * Must be aligned on 128 byte boundary.
95 */
96 uint8_t abCmd[0x40];
97 /** The ATAPI command region.
98 * Located 40h bytes after the beginning of the CFIS (Command FIS).
99 */
100 uint8_t abAcmd[0x20];
101 /** Align the PRDT structure on a 128 byte boundary. */
102 uint8_t abAlignment2[0x20];
103 /** Physical Region Descriptor Table (PRDT) array. In other
104 * words, a scatter/gather descriptor list.
105 */
106 ahci_prdt aPrdt[16];
107 /** Memory for the received command FIS area as specified by chapter 4.2.1
108 * of the Intel AHCI spec. This area is normally 256 bytes big but to save memory
109 * only the first 96 bytes are used because it is assumed that the controller
110 * never writes to the UFIS or reserved area. - Must be aligned on a 256byte boundary.
111 */
112 uint8_t abFisRecv[0x60];
113 /** Base I/O port for the index/data register pair. */
114 uint16_t iobase;
115 /** Current port which uses the memory to communicate with the controller. */
116 uint8_t cur_port;
117 /** Current PRD index (for pre/post skip). */
118 uint8_t cur_prd;
119 /** Saved high bits of EAX. */
120 uint16_t saved_eax_hi;
121 /** VDS EDDS DMA buffer descriptor structure. */
122 vds_edds edds;
123 vds_sg edds_more_sg[NUM_EDDS_SG - 1];
124} ahci_t;
125
126/* The AHCI specific data must fit into 1KB (statically allocated). */
127ct_assert(sizeof(ahci_t) <= 1024);
128
129/** PCI configuration fields. */
130#define PCI_CONFIG_CAP 0x34
131
132#define PCI_CAP_ID_SATACR 0x12
133#define VBOX_AHCI_NO_DEVICE 0xffff
134
135#define RT_BIT_32(bit) ((uint32_t)(1L << (bit)))
136
137/** Global register set. */
138#define AHCI_HBA_SIZE 0x100
139
140/// @todo what are the casts good for?
141#define AHCI_REG_CAP ((uint32_t)0x00)
142#define AHCI_REG_GHC ((uint32_t)0x04)
143# define AHCI_GHC_AE RT_BIT_32(31)
144# define AHCI_GHC_IR RT_BIT_32(1)
145# define AHCI_GHC_HR RT_BIT_32(0)
146#define AHCI_REG_IS ((uint32_t)0x08)
147#define AHCI_REG_PI ((uint32_t)0x0c)
148#define AHCI_REG_VS ((uint32_t)0x10)
149
150/** Per port register set. */
151#define AHCI_PORT_SIZE 0x80
152
153#define AHCI_REG_PORT_CLB 0x00
154#define AHCI_REG_PORT_CLBU 0x04
155#define AHCI_REG_PORT_FB 0x08
156#define AHCI_REG_PORT_FBU 0x0c
157#define AHCI_REG_PORT_IS 0x10
158# define AHCI_REG_PORT_IS_DHRS RT_BIT_32(0)
159# define AHCI_REG_PORT_IS_TFES RT_BIT_32(30)
160#define AHCI_REG_PORT_IE 0x14
161#define AHCI_REG_PORT_CMD 0x18
162# define AHCI_REG_PORT_CMD_ST RT_BIT_32(0)
163# define AHCI_REG_PORT_CMD_FRE RT_BIT_32(4)
164# define AHCI_REG_PORT_CMD_FR RT_BIT_32(14)
165# define AHCI_REG_PORT_CMD_CR RT_BIT_32(15)
166#define AHCI_REG_PORT_TFD 0x20
167#define AHCI_REG_PORT_SIG 0x24
168#define AHCI_REG_PORT_SSTS 0x28
169#define AHCI_REG_PORT_SCTL 0x2c
170#define AHCI_REG_PORT_SERR 0x30
171#define AHCI_REG_PORT_SACT 0x34
172#define AHCI_REG_PORT_CI 0x38
173
174/** Returns the absolute register offset from a given port and port register. */
175#define AHCI_PORT_REG(port, reg) (AHCI_HBA_SIZE + (port) * AHCI_PORT_SIZE + (reg))
176
177#define AHCI_REG_IDX 0
178#define AHCI_REG_DATA 4
179
180/** Writes the given value to a AHCI register. */
181#define AHCI_WRITE_REG(iobase, reg, val) \
182 outpd((iobase) + AHCI_REG_IDX, reg); \
183 outpd((iobase) + AHCI_REG_DATA, val)
184
185/** Reads from a AHCI register. */
186#define AHCI_READ_REG(iobase, reg, val) \
187 outpd((iobase) + AHCI_REG_IDX, reg); \
188 (val) = inpd((iobase) + AHCI_REG_DATA)
189
190/** Writes to the given port register. */
191#define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val) \
192 AHCI_WRITE_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
193
194/** Reads from the given port register. */
195#define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val) \
196 AHCI_READ_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
197
198#define ATA_CMD_IDENTIFY_DEVICE 0xEC
199#define ATA_CMD_IDENTIFY_PACKET 0xA1
200#define ATA_CMD_PACKET 0xA0
201#define AHCI_CMD_READ_DMA_EXT 0x25
202#define AHCI_CMD_WRITE_DMA_EXT 0x35
203
204
205/* Warning: Destroys high bits of EAX. */
206uint32_t inpd(uint16_t port);
207#pragma aux inpd = \
208 ".386" \
209 "in eax, dx" \
210 "mov dx, ax" \
211 "shr eax, 16" \
212 "xchg ax, dx" \
213 parm [dx] value [dx ax] modify nomemory;
214
215/* Warning: Destroys high bits of EAX. */
216void outpd(uint16_t port, uint32_t val);
217#pragma aux outpd = \
218 ".386" \
219 "xchg ax, cx" \
220 "shl eax, 16" \
221 "mov ax, cx" \
222 "out dx, eax" \
223 parm [dx] [cx ax] modify nomemory;
224
225
226/* Machinery to save/restore high bits of EAX. 32-bit port I/O needs to use
227 * EAX, but saving/restoring EAX around each port access would be inefficient.
228 * Instead, each externally callable routine must save the high bits before
229 * modifying them and restore the high bits before exiting.
230 */
231
232/* Note: Reading high EAX bits destroys them - *must* be restored later. */
233uint16_t eax_hi_rd(void);
234#pragma aux eax_hi_rd = \
235 ".386" \
236 "shr eax, 16" \
237 value [ax] modify nomemory;
238
239void eax_hi_wr(uint16_t);
240#pragma aux eax_hi_wr = \
241 ".386" \
242 "shl eax, 16" \
243 parm [ax] modify nomemory;
244
245void inline high_bits_save(ahci_t __far *ahci)
246{
247 ahci->saved_eax_hi = eax_hi_rd();
248}
249
250void inline high_bits_restore(ahci_t __far *ahci)
251{
252 eax_hi_wr(ahci->saved_eax_hi);
253}
254
255/**
256 * Sets a given set of bits in a register.
257 */
258static void inline ahci_ctrl_set_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
259{
260 outpd(iobase + AHCI_REG_IDX, reg);
261 outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) | mask);
262}
263
264/**
265 * Clears a given set of bits in a register.
266 */
267static void inline ahci_ctrl_clear_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
268{
269 outpd(iobase + AHCI_REG_IDX, reg);
270 outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
271}
272
273/**
274 * Returns whether at least one of the bits in the given mask is set
275 * for a register.
276 */
277static uint8_t inline ahci_ctrl_is_bit_set(uint16_t iobase, uint16_t reg, uint32_t mask)
278{
279 outpd(iobase + AHCI_REG_IDX, reg);
280 return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
281}
282
283/**
284 * Extracts a range of bits from a register and shifts them
285 * to the right.
286 */
287static uint16_t ahci_ctrl_extract_bits(uint32_t val, uint32_t mask, uint8_t shift)
288{
289 return (val & mask) >> shift;
290}
291
292/**
293 * Converts a segment:offset pair into a 32bit physical address.
294 */
295static uint32_t ahci_addr_to_phys(void __far *ptr)
296{
297 return ((uint32_t)FP_SEG(ptr) << 4) + FP_OFF(ptr);
298}
299
300/**
301 * Issues a command to the SATA controller and waits for completion.
302 */
303static void ahci_port_cmd_sync(ahci_t __far *ahci, uint8_t val)
304{
305 uint16_t io_base;
306 uint8_t port;
307
308 port = ahci->cur_port;
309 io_base = ahci->iobase;
310
311 if (port != 0xff)
312 {
313 /* Prepare the command header. */
314 ahci->aCmdHdr[0] = ((uint32_t)ahci->cur_prd << 16) | RT_BIT_32(7) | val;
315 ahci->aCmdHdr[1] = 0;
316 ahci->aCmdHdr[2] = ahci_addr_to_phys(&ahci->abCmd[0]);
317
318 /* Enable Command and FIS receive engine. */
319 ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
320 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
321
322 /* Queue command. */
323 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CI, 0x1);
324
325 /* Wait for a D2H FIS. */
326 DBG_AHCI("AHCI: Waiting for D2H FIS\n");
327 while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
328 AHCI_REG_PORT_IS_DHRS | AHCI_REG_PORT_IS_TFES) == 0)
329 {
330 // This is where we'd need some kind of a yield functionality...
331 }
332
333 ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
334 AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
335
336 /* Disable command engine. */
337 ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
338 AHCI_REG_PORT_CMD_ST);
339 /* Caller must examine status. */
340 }
341 else
342 DBG_AHCI("AHCI: Invalid port given\n");
343}
344
345/**
346 * Issue command to device.
347 */
348static uint16_t ahci_cmd_data(bio_dsk_t __far *bios_dsk, uint8_t cmd)
349{
350 ahci_t __far *ahci = bios_dsk->ahci_seg :> 0;
351 uint16_t n_sect = bios_dsk->drqp.nsect;
352 uint16_t sectsz = bios_dsk->drqp.sect_sz;
353 fis_d2h __far *d2h;
354
355 _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
356
357 /* Prepare the FIS. */
358 ahci->abCmd[0] = 0x27; /* FIS type H2D. */
359 ahci->abCmd[1] = 1 << 7; /* Command update. */
360 ahci->abCmd[2] = cmd;
361 ahci->abCmd[3] = 0;
362
363 ahci->abCmd[4] = bios_dsk->drqp.lba & 0xff;
364 ahci->abCmd[5] = (bios_dsk->drqp.lba >> 8) & 0xff;
365 ahci->abCmd[6] = (bios_dsk->drqp.lba >> 16) & 0xff;
366 ahci->abCmd[7] = RT_BIT_32(6); /* LBA access. */
367
368 ahci->abCmd[8] = (bios_dsk->drqp.lba >> 24) & 0xff;
369 ahci->abCmd[9] = (bios_dsk->drqp.lba >> 32) & 0xff;
370 ahci->abCmd[10] = (bios_dsk->drqp.lba >> 40) & 0xff;
371 ahci->abCmd[11] = 0;
372
373 ahci->abCmd[12] = (uint8_t)(n_sect & 0xff);
374 ahci->abCmd[13] = (uint8_t)((n_sect >> 8) & 0xff);
375
376 /* Lock memory needed for DMA. */
377 ahci->edds.num_avail = NUM_EDDS_SG;
378 DBG_AHCI("AHCI: S/G list for %lu bytes\n", (uint32_t)n_sect * sectsz);
379 vds_build_sg_list(&ahci->edds, bios_dsk->drqp.buffer, (uint32_t)n_sect * sectsz);
380
381 /* Set up the PRDT. */
382 ahci->aPrdt[ahci->cur_prd].len = ahci->edds.u.sg[0].size - 1;
383 ahci->aPrdt[ahci->cur_prd].phys_addr = ahci->edds.u.sg[0].phys_addr;
384 ++ahci->cur_prd;
385
386#if DEBUG_AHCI
387 {
388 uint16_t prdt_idx;
389
390 for (prdt_idx = 0; prdt_idx < ahci->cur_prd; ++prdt_idx) {
391 DBG_AHCI("S/G entry %u: %5lu bytes @ %08lX\n", prdt_idx,
392 ahci->aPrdt[prdt_idx].len + 1, ahci->aPrdt[prdt_idx].phys_addr);
393 }
394 }
395#endif
396
397 /* Build variable part of first command DWORD (reuses 'cmd'). */
398 if (cmd == AHCI_CMD_WRITE_DMA_EXT)
399 cmd = RT_BIT_32(6); /* Indicate a write to device. */
400 else if (cmd == ATA_CMD_PACKET) {
401 cmd |= RT_BIT_32(5); /* Indicate ATAPI command. */
402 ahci->abCmd[3] |= 1; /* DMA transfers. */
403 } else
404 cmd = 0;
405
406 cmd |= 5; /* Five DWORDs. */
407
408 ahci_port_cmd_sync(ahci, cmd);
409
410 /* Examine operation status. */
411 d2h = (void __far *)&ahci->abFisRecv[0x40];
412 DBG_AHCI("AHCI: ERR=%02x, STAT=%02x, SCNT=%02x\n", d2h->error, d2h->status, d2h->sec_cn);
413
414 /* Unlock the buffer again. */
415 vds_free_sg_list(&ahci->edds);
416 return d2h->error ? 4 : 0;
417}
418
419/**
420 * Deinits the curent active port.
421 */
422static void ahci_port_deinit_current(ahci_t __far *ahci)
423{
424 uint16_t io_base;
425 uint8_t port;
426
427 io_base = ahci->iobase;
428 port = ahci->cur_port;
429
430 if (port != 0xff)
431 {
432 /* Put the port into an idle state. */
433 ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
434 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
435
436 while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
437 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
438 {
439 DBG_AHCI("AHCI: Waiting for the port to idle\n");
440 }
441
442 /*
443 * Port idles, set up memory for commands and received FIS and program the
444 * address registers.
445 */
446 /// @todo merge memsets?
447 _fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
448 _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
449 _fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
450
451 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FB, 0);
452 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FBU, 0);
453
454 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLB, 0);
455 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLBU, 0);
456
457 /* Disable all interrupts. */
458 VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_IE, 0);
459
460 ahci->cur_port = 0xff;
461 }
462}
463
464/**
465 * Brings a port into a minimal state to make device detection possible
466 * or to queue requests.
467 */
468static void ahci_port_init(ahci_t __far *ahci, uint8_t u8Port)
469{
470 /* Deinit any other port first. */
471 ahci_port_deinit_current(ahci);
472
473 /* Put the port into an idle state. */
474 ahci_ctrl_clear_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
475 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
476
477 while (ahci_ctrl_is_bit_set(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
478 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
479 {
480 DBG_AHCI("AHCI: Waiting for the port to idle\n");
481 }
482
483 /*
484 * Port idles, set up memory for commands and received FIS and program the
485 * address registers.
486 */
487 /// @todo just one memset?
488 _fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
489 _fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
490 _fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
491
492 DBG_AHCI("AHCI: FIS receive area %lx from %x:%x\n",
493 ahci_addr_to_phys(&ahci->abFisRecv), FP_SEG(ahci->abFisRecv), FP_OFF(ahci->abFisRecv));
494 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FB, ahci_addr_to_phys(&ahci->abFisRecv));
495 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FBU, 0);
496
497 DBG_AHCI("AHCI: CMD list area %lx\n", ahci_addr_to_phys(&ahci->aCmdHdr));
498 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLB, ahci_addr_to_phys(&ahci->aCmdHdr));
499 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLBU, 0);
500
501 /* Disable all interrupts. */
502 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IE, 0);
503 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IS, 0xffffffff);
504 /* Clear all errors. */
505 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
506
507 ahci->cur_port = u8Port;
508 ahci->cur_prd = 0;
509}
510
511/**
512 * Read sectors from an attached AHCI device.
513 *
514 * @returns status code.
515 * @param bios_dsk Pointer to disk request packet (in the
516 * EBDA).
517 */
518int ahci_read_sectors(bio_dsk_t __far *bios_dsk)
519{
520 uint16_t device_id;
521 uint16_t rc;
522
523 device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
524 if (device_id > BX_MAX_AHCI_DEVICES)
525 BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
526
527 DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
528 bios_dsk->drqp.nsect, bios_dsk->drqp.lba,
529 device_id, bios_dsk->ahcidev[device_id].port);
530
531 high_bits_save(bios_dsk->ahci_seg :> 0);
532 ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
533 rc = ahci_cmd_data(bios_dsk, AHCI_CMD_READ_DMA_EXT);
534 DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
535 bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
536#ifdef DMA_WORKAROUND
537 rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.nsect * 512 / 2);
538#endif
539 high_bits_restore(bios_dsk->ahci_seg :> 0);
540 return rc;
541}
542
543/**
544 * Write sectors to an attached AHCI device.
545 *
546 * @returns status code.
547 * @param bios_dsk Pointer to disk request packet (in the
548 * EBDA).
549 */
550int ahci_write_sectors(bio_dsk_t __far *bios_dsk)
551{
552 uint16_t device_id;
553 uint16_t rc;
554
555 device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
556 if (device_id > BX_MAX_AHCI_DEVICES)
557 BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
558
559 DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
560 bios_dsk->drqp.nsect, bios_dsk->drqp.lba, device_id,
561 bios_dsk->ahcidev[device_id].port);
562
563 high_bits_save(bios_dsk->ahci_seg :> 0);
564 ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
565 rc = ahci_cmd_data(bios_dsk, AHCI_CMD_WRITE_DMA_EXT);
566 DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
567 bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
568 high_bits_restore(bios_dsk->ahci_seg :> 0);
569 return rc;
570}
571
572/// @todo move
573#define ATA_DATA_NO 0x00
574#define ATA_DATA_IN 0x01
575#define ATA_DATA_OUT 0x02
576
577uint16_t ahci_cmd_packet(uint16_t device_id, uint8_t cmdlen, char __far *cmdbuf,
578 uint32_t length, uint8_t inout, char __far *buffer)
579{
580 bio_dsk_t __far *bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
581 ahci_t __far *ahci;
582
583 /* Data out is currently not supported. */
584 if (inout == ATA_DATA_OUT) {
585 BX_INFO("%s: DATA_OUT not supported yet\n", __func__);
586 return 1;
587 }
588
589 /* Convert to AHCI specific device number. */
590 device_id = VBOX_GET_AHCI_DEVICE(device_id);
591
592 DBG_AHCI("%s: reading %lu bytes, device %d, port %d\n", __func__,
593 length, device_id, bios_dsk->ahcidev[device_id].port);
594 DBG_AHCI("%s: reading %u %u-byte sectors\n", __func__,
595 bios_dsk->drqp.nsect, bios_dsk->drqp.sect_sz);
596
597 bios_dsk->drqp.lba = length << 8; /// @todo xfer length limit
598 bios_dsk->drqp.buffer = buffer;
599 bios_dsk->drqp.nsect = length / bios_dsk->drqp.sect_sz;
600// bios_dsk->drqp.sect_sz = 2048;
601
602 ahci = bios_dsk->ahci_seg :> 0;
603 high_bits_save(ahci);
604
605 ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
606
607 /* Copy the ATAPI command where the HBA can fetch it. */
608 _fmemcpy(ahci->abAcmd, cmdbuf, cmdlen);
609
610 /* Reset transferred counts. */
611 /// @todo clear in calling code?
612 bios_dsk->drqp.trsfsectors = 0;
613 bios_dsk->drqp.trsfbytes = 0;
614
615 ahci_cmd_data(bios_dsk, ATA_CMD_PACKET);
616 DBG_AHCI("%s: transferred %lu bytes\n", __func__, ahci->aCmdHdr[1]);
617 bios_dsk->drqp.trsfbytes = ahci->aCmdHdr[1];
618#ifdef DMA_WORKAROUND
619 rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.trsfbytes / 2);
620#endif
621 high_bits_restore(ahci);
622
623 return ahci->aCmdHdr[1] == 0 ? 4 : 0;
624}
625
626/* Wait for the specified number of BIOS timer ticks or data bytes. */
627void wait_ticks_device_init( unsigned wait_ticks, unsigned wait_bytes )
628{
629}
630
631void ahci_port_detect_device(ahci_t __far *ahci, uint8_t u8Port)
632{
633 uint32_t val;
634 bio_dsk_t __far *bios_dsk;
635 volatile uint32_t __far *ticks;
636 uint32_t end_tick;
637 int device_found = 0;
638
639 ahci_port_init(ahci, u8Port);
640
641 bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
642
643 /* Reset connection. */
644 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0x01);
645 /*
646 * According to the spec we should wait at least 1msec until the reset
647 * is cleared but this is a virtual controller so we don't have to.
648 */
649 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0);
650
651 /*
652 * We do however have to wait for the device to initialize (the port reset
653 * to complete). That can take up to 10ms according to the SATA spec (device
654 * must send COMINIT within 10ms of COMRESET). We should be generous with
655 * the wait because in the typical case there are no ports without a device
656 * attached.
657 */
658 ticks = MK_FP( 0x40, 0x6C );
659 end_tick = *ticks + 3; /* Wait up to five BIOS ticks, something in 150ms range. */
660
661 while( *ticks < end_tick )
662 {
663 /* If PxSSTS.DET is 3, everything went fine. */
664 VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
665 if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 3) {
666 device_found = 1;
667 break;
668 }
669 }
670
671 /* Timed out, no device detected. */
672 if (!device_found) {
673 DBG_AHCI("AHCI: Timed out, no device detected on port %d\n", u8Port);
674 return;
675 }
676
677 if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 0x3)
678 {
679 uint8_t abBuffer[0x0200];
680 uint8_t hdcount, devcount_ahci, hd_index;
681 uint8_t cdcount;
682 uint8_t removable;
683
684 /* Clear all errors after the reset. */
685 VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
686
687 devcount_ahci = bios_dsk->ahci_devcnt;
688
689 DBG_AHCI("AHCI: Device detected on port %d\n", u8Port);
690
691 /// @todo Merge common HD/CDROM detection code
692 if (devcount_ahci < BX_MAX_AHCI_DEVICES)
693 {
694 /* Device detected, enable FIS receive. */
695 ahci_ctrl_set_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
696 AHCI_REG_PORT_CMD_FRE);
697
698 /* Check signature to determine device type. */
699 VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SIG, val);
700 if (val == 0x101)
701 {
702 uint64_t sectors;
703 uint16_t cylinders, heads, spt;
704 chs_t lgeo;
705 uint8_t idxCmosChsBase;
706
707 DBG_AHCI("AHCI: Detected hard disk\n");
708
709 /* Identify device. */
710 bios_dsk->drqp.lba = 0;
711 bios_dsk->drqp.buffer = &abBuffer;
712 bios_dsk->drqp.nsect = 1;
713 bios_dsk->drqp.sect_sz = 512;
714 ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_DEVICE);
715
716 /* Calculate index into the generic device table. */
717 hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
718
719 removable = *(abBuffer+0) & 0x80 ? 1 : 0;
720 cylinders = *(uint16_t *)(abBuffer+(1*2)); // word 1
721 heads = *(uint16_t *)(abBuffer+(3*2)); // word 3
722 spt = *(uint16_t *)(abBuffer+(6*2)); // word 6
723 sectors = *(uint32_t *)(abBuffer+(60*2)); // word 60 and word 61
724
725 if (sectors == 0x0FFFFFFF) /* For disks bigger than ~128GB */
726 sectors = *(uint64_t *)(abBuffer+(100*2)); // words 100 to 103
727
728 DBG_AHCI("AHCI: 0x%llx sectors\n", sectors);
729
730 bios_dsk->ahcidev[devcount_ahci].port = u8Port;
731 bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
732 bios_dsk->devices[hd_index].device = DSK_DEVICE_HD;
733 bios_dsk->devices[hd_index].removable = removable;
734 bios_dsk->devices[hd_index].lock = 0;
735 bios_dsk->devices[hd_index].blksize = 512;
736 bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_LBA;
737 bios_dsk->devices[hd_index].sectors = sectors;
738
739 bios_dsk->devices[hd_index].pchs.heads = heads;
740 bios_dsk->devices[hd_index].pchs.cylinders = cylinders;
741 bios_dsk->devices[hd_index].pchs.spt = spt;
742
743 /* Get logical CHS geometry. */
744 switch (devcount_ahci)
745 {
746 case 0:
747 idxCmosChsBase = 0x40;
748 break;
749 case 1:
750 idxCmosChsBase = 0x48;
751 break;
752 case 2:
753 idxCmosChsBase = 0x50;
754 break;
755 case 3:
756 idxCmosChsBase = 0x58;
757 break;
758 default:
759 idxCmosChsBase = 0;
760 }
761 if (idxCmosChsBase && inb_cmos(idxCmosChsBase+7))
762 {
763 lgeo.cylinders = get_cmos_word(idxCmosChsBase /*, idxCmosChsBase+1*/);
764 lgeo.heads = inb_cmos(idxCmosChsBase + 2);
765 lgeo.spt = inb_cmos(idxCmosChsBase + 7);
766 }
767 else
768 set_geom_lba(&lgeo, sectors); /* Default EDD-style translated LBA geometry. */
769
770 BX_INFO("AHCI %d-P#%d: PCHS=%u/%u/%u LCHS=%u/%u/%u 0x%llx sectors\n", devcount_ahci,
771 u8Port, cylinders, heads, spt, lgeo.cylinders, lgeo.heads, lgeo.spt,
772 sectors);
773
774 bios_dsk->devices[hd_index].lchs = lgeo;
775
776 /* Store the ID of the disk in the BIOS hdidmap. */
777 hdcount = bios_dsk->hdcount;
778 bios_dsk->hdidmap[hdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
779 hdcount++;
780 bios_dsk->hdcount = hdcount;
781
782 /* Update hdcount in the BDA. */
783 hdcount = read_byte(0x40, 0x75);
784 hdcount++;
785 write_byte(0x40, 0x75, hdcount);
786 }
787 else if (val == 0xeb140101)
788 {
789 DBG_AHCI("AHCI: Detected ATAPI device\n");
790
791 /* Identify packet device. */
792 bios_dsk->drqp.lba = 0;
793 bios_dsk->drqp.buffer = &abBuffer;
794 bios_dsk->drqp.nsect = 1;
795 bios_dsk->drqp.sect_sz = 512;
796 ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_PACKET);
797
798 /* Calculate index into the generic device table. */
799 hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
800
801 removable = *(abBuffer+0) & 0x80 ? 1 : 0;
802
803 bios_dsk->ahcidev[devcount_ahci].port = u8Port;
804 bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
805 bios_dsk->devices[hd_index].device = DSK_DEVICE_CDROM;
806 bios_dsk->devices[hd_index].removable = removable;
807 bios_dsk->devices[hd_index].blksize = 2048;
808 bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_NONE;
809
810 /* Store the ID of the device in the BIOS cdidmap. */
811 cdcount = bios_dsk->cdcount;
812 bios_dsk->cdidmap[cdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
813 cdcount++;
814 bios_dsk->cdcount = cdcount;
815 }
816 else
817 DBG_AHCI("AHCI: Ignoring unknown device\n");
818
819 devcount_ahci++;
820 bios_dsk->ahci_devcnt = devcount_ahci;
821 }
822 else
823 DBG_AHCI("AHCI: Reached maximum device count, skipping\n");
824 }
825}
826
827/**
828 * Allocates 1K of conventional memory.
829 */
830static uint16_t ahci_mem_alloc(void)
831{
832 uint16_t base_mem_kb;
833 uint16_t ahci_seg;
834
835 base_mem_kb = read_word(0x00, 0x0413);
836
837 DBG_AHCI("AHCI: %dK of base mem\n", base_mem_kb);
838
839 if (base_mem_kb == 0)
840 return 0;
841
842 base_mem_kb--; /* Allocate one block. */
843 ahci_seg = (((uint32_t)base_mem_kb * 1024) >> 4); /* Calculate start segment. */
844
845 write_word(0x00, 0x0413, base_mem_kb);
846
847 return ahci_seg;
848}
849
850/**
851 * Initializes the AHCI HBA and detects attached devices.
852 */
853static int ahci_hba_init(uint16_t io_base)
854{
855 uint8_t i, cPorts;
856 uint32_t val;
857 uint16_t ebda_seg;
858 uint16_t ahci_seg;
859 bio_dsk_t __far *bios_dsk;
860 ahci_t __far *ahci;
861
862
863 ebda_seg = read_word(0x0040, 0x000E);
864 bios_dsk = ebda_seg :> &EbdaData->bdisk;
865
866 AHCI_READ_REG(io_base, AHCI_REG_VS, val);
867 DBG_AHCI("AHCI: Controller version: 0x%x (major) 0x%x (minor)\n",
868 ahci_ctrl_extract_bits(val, 0xffff0000, 16),
869 ahci_ctrl_extract_bits(val, 0x0000ffff, 0));
870
871 /* Allocate 1K of base memory. */
872 ahci_seg = ahci_mem_alloc();
873 if (ahci_seg == 0)
874 {
875 DBG_AHCI("AHCI: Could not allocate 1K of memory, can't boot from controller\n");
876 return 0;
877 }
878 DBG_AHCI("AHCI: ahci_seg=%04x, size=%04x, pointer at EBDA:%04x (EBDA size=%04x)\n",
879 ahci_seg, sizeof(ahci_t), (uint16_t)&EbdaData->bdisk.ahci_seg, sizeof(ebda_data_t));
880
881 bios_dsk->ahci_seg = ahci_seg;
882 bios_dsk->ahci_devcnt = 0;
883
884 ahci = ahci_seg :> 0;
885 ahci->cur_port = 0xff;
886 ahci->iobase = io_base;
887
888 /* Reset the controller. */
889 ahci_ctrl_set_bits(io_base, AHCI_REG_GHC, AHCI_GHC_HR);
890 do
891 {
892 AHCI_READ_REG(io_base, AHCI_REG_GHC, val);
893 } while ((val & AHCI_GHC_HR) != 0);
894
895 AHCI_READ_REG(io_base, AHCI_REG_CAP, val);
896 cPorts = ahci_ctrl_extract_bits(val, 0x1f, 0) + 1; /* Extract number of ports.*/
897
898 DBG_AHCI("AHCI: HBA has %u ports\n", cPorts);
899
900 /* Go through the ports. */
901 i = 0;
902 while (i < 32)
903 {
904 if (ahci_ctrl_is_bit_set(io_base, AHCI_REG_PI, RT_BIT_32(i)) != 0)
905 {
906 DBG_AHCI("AHCI: Port %u is present\n", i);
907 ahci_port_detect_device(ahci_seg :> 0, i);
908 cPorts--;
909 if (cPorts == 0)
910 break;
911 }
912 i++;
913 }
914
915 return 0;
916}
917
918/**
919 * Init the AHCI driver and detect attached disks.
920 */
921void BIOSCALL ahci_init(void)
922{
923 uint16_t busdevfn;
924
925 busdevfn = pci_find_classcode(0x00010601);
926 if (busdevfn != VBOX_AHCI_NO_DEVICE)
927 {
928 uint8_t u8Bus, u8DevFn;
929 uint8_t u8PciCapOff;
930
931 u8Bus = (busdevfn & 0xff00) >> 8;
932 u8DevFn = busdevfn & 0x00ff;
933
934 DBG_AHCI("AHCI HBA at Bus %u DevFn 0x%x (raw 0x%x)\n", u8Bus, u8DevFn, busdevfn);
935
936 /* Examine the capability list and search for the Serial ATA Capability Register. */
937 u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
938
939 while (u8PciCapOff != 0)
940 {
941 uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
942
943 DBG_AHCI("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
944
945 if (u8PciCapId == PCI_CAP_ID_SATACR)
946 break;
947
948 /* Go on to the next capability. */
949 u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
950 }
951
952 if (u8PciCapOff != 0)
953 {
954 uint8_t u8Rev;
955
956 DBG_AHCI("AHCI HBA with SATA Capability register at 0x%x\n", u8PciCapOff);
957
958 /* Advance to the stuff behind the id and next capability pointer. */
959 u8PciCapOff += 2;
960
961 u8Rev = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
962 if (u8Rev == 0x10)
963 {
964 /* Read the SATACR1 register and get the bar and offset of the index/data pair register. */
965 uint8_t u8Bar = 0x00;
966 uint16_t u16Off = 0x00;
967 uint16_t u16BarOff = pci_read_config_word(u8Bus, u8DevFn, u8PciCapOff + 2);
968
969 DBG_AHCI("SATACR1: 0x%x\n", u16BarOff);
970
971 switch (u16BarOff & 0xf)
972 {
973 case 0x04:
974 u8Bar = 0x10;
975 break;
976 case 0x05:
977 u8Bar = 0x14;
978 break;
979 case 0x06:
980 u8Bar = 0x18;
981 break;
982 case 0x07:
983 u8Bar = 0x1c;
984 break;
985 case 0x08:
986 u8Bar = 0x20;
987 break;
988 case 0x09:
989 u8Bar = 0x24;
990 break;
991 case 0x0f:
992 default:
993 /* Reserved or unsupported. */
994 DBG_AHCI("BAR 0x%x unsupported\n", u16BarOff & 0xf);
995 }
996
997 /* Get the offset inside the BAR from bits 4:15. */
998 u16Off = (u16BarOff >> 4) * 4;
999
1000 if (u8Bar != 0x00)
1001 {
1002 uint32_t u32Bar = pci_read_config_dword(u8Bus, u8DevFn, u8Bar);
1003
1004 DBG_AHCI("BAR at 0x%x : 0x%x\n", u8Bar, u32Bar);
1005
1006 if ((u32Bar & 0x01) != 0)
1007 {
1008 int rc;
1009 uint16_t u16AhciIoBase = (u32Bar & 0xfff0) + u16Off;
1010
1011 /* Enable PCI memory, I/O, bus mastering access in command register. */
1012 pci_write_config_word(u8Bus, u8DevFn, 4, 0x7);
1013
1014 DBG_AHCI("I/O base: 0x%x\n", u16AhciIoBase);
1015 rc = ahci_hba_init(u16AhciIoBase);
1016 }
1017 else
1018 DBG_AHCI("BAR is MMIO\n");
1019 }
1020 }
1021 else
1022 DBG_AHCI("Invalid revision 0x%x\n", u8Rev);
1023 }
1024 else
1025 DBG_AHCI("AHCI HBA with no usable Index/Data register pair!\n");
1026 }
1027 else
1028 DBG_AHCI("No AHCI HBA!\n");
1029}
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