Changes between Initial Version and Version 1 of Ticket #2573
- Timestamp:
- Nov 6, 2008 8:38:03 AM (15 years ago)
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Ticket #2573 – Description
initial v1 1 1 An APIC timer is initialized as periodic: 2 {{{ 2 3 // lapic_base: u32_t *lapic_base; 3 4 4 5 // Disable timer first 5 lapic_base[APIC_DWREG_LVT_TMR] = APIC_TIMER_VECTOR | APIC_LVT_D_STAT_IDLE | APIC_LVT_TMR_PERIODIC | APIC_LVT_TRIGGER_LEVEL | APIC_LVT_MASK; 6 lapic_base[APIC_DWREG_LVT_TMR] = APIC_TIMER_VECTOR | 7 APIC_LVT_D_STAT_IDLE | 8 APIC_LVT_TMR_PERIODIC | 9 APIC_LVT_TRIGGER_LEVEL | 10 APIC_LVT_MASK; 6 11 // Write counters 7 12 lapic_base[APIC_DWREG_TMR_DIVIDE] = div; … … 10 15 // Enable if it is enabled in configruation 11 16 if (enabled) 12 lapic_base[APIC_DWREG_LVT_TMR] = APIC_TIMER_VECTOR | APIC_LVT_D_STAT_IDLE | APIC_LVT_TRIGGER_LEVEL | APIC_LVT_TMR_PERIODIC; 13 14 Timer interrupt is ok (a counter in a handler is periodically incremented) 15 Then a system is sending INIT IPI: 16 lapic_base[APIC_DWREG_ICR0] = APIC_ICR0_DST_ALL_NO_SELF | APIC_ICR0_D_MODE_INIT; 17 17 lapic_base[APIC_DWREG_LVT_TMR] = APIC_TIMER_VECTOR | 18 APIC_LVT_D_STAT_IDLE | 19 APIC_LVT_TRIGGER_LEVEL | 20 APIC_LVT_TMR_PERIODIC; 21 }}} 22 Timer interrupt is ok (a counter in a handler is periodically incremented). Then a system is sending INIT IPI: 23 {{{ 24 lapic_base[APIC_DWREG_ICR0] = APIC_ICR0_DST_ALL_NO_SELF | 25 APIC_ICR0_D_MODE_INIT; 26 }}} 18 27 And whoops... A timer dies. And no timer re-initialization helps.
