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Changes between Initial Version and Version 1 of Ticket #2573


Ignore:
Timestamp:
11/06/08 08:38:03 (5 years ago)
Author:
frank
Comment:

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  • Ticket #2573 – Description

    initial v1  
    11An APIC timer is initialized as periodic: 
     2{{{ 
    23// lapic_base: u32_t *lapic_base; 
    34 
    45    // Disable timer first 
    5     lapic_base[APIC_DWREG_LVT_TMR]      = APIC_TIMER_VECTOR | APIC_LVT_D_STAT_IDLE | APIC_LVT_TMR_PERIODIC | APIC_LVT_TRIGGER_LEVEL | APIC_LVT_MASK; 
     6    lapic_base[APIC_DWREG_LVT_TMR]      = APIC_TIMER_VECTOR | 
     7                                          APIC_LVT_D_STAT_IDLE | 
     8                                          APIC_LVT_TMR_PERIODIC | 
     9                                          APIC_LVT_TRIGGER_LEVEL | 
     10                                          APIC_LVT_MASK; 
    611    // Write counters 
    712    lapic_base[APIC_DWREG_TMR_DIVIDE]   = div; 
     
    1015    // Enable if it is enabled in configruation 
    1116    if (enabled) 
    12         lapic_base[APIC_DWREG_LVT_TMR]  = APIC_TIMER_VECTOR | APIC_LVT_D_STAT_IDLE | APIC_LVT_TRIGGER_LEVEL | APIC_LVT_TMR_PERIODIC; 
    13  
    14 Timer interrupt is ok (a counter in a handler is periodically incremented) 
    15 Then a system is sending INIT IPI: 
    16 lapic_base[APIC_DWREG_ICR0] = APIC_ICR0_DST_ALL_NO_SELF | APIC_ICR0_D_MODE_INIT; 
    17  
     17        lapic_base[APIC_DWREG_LVT_TMR]  = APIC_TIMER_VECTOR | 
     18                                          APIC_LVT_D_STAT_IDLE | 
     19                                          APIC_LVT_TRIGGER_LEVEL | 
     20                                          APIC_LVT_TMR_PERIODIC; 
     21}}} 
     22Timer interrupt is ok (a counter in a handler is periodically incremented). Then a system is sending INIT IPI: 
     23{{{ 
     24lapic_base[APIC_DWREG_ICR0] = APIC_ICR0_DST_ALL_NO_SELF | 
     25                              APIC_ICR0_D_MODE_INIT; 
     26}}} 
    1827And whoops... A timer dies. And no timer re-initialization helps. 

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