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Changes between Initial Version and Version 1 of Ticket #10532, comment 7


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Timestamp:
05/10/12 12:41:29 (2 years ago)
Author:
DJ PhoeniX
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  • Ticket #10532, comment 7

    initial v1  
    33[http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf AMD specifications] (12.3.2) 
    44> The current-task state is saved in the TSS. This includes the next-instruction pointer (EIP), EFLAGS, the general-purpose registers, and the segment-selector registers. 
     5 
    56> Up to this point, any exception that occurs aborts the task switch without changing the processor state. From this point forward, any exception that occurs does so in the context of the new task. If an exception occurs in the context of the new task during a task switch, the processor finishes loading the new-task state without performing additional checks. The processor transfers control to the #TS handler after this state is loaded, but before the first instruction is executed in the new task. When a #TS occurs, it is possible that some of the state loaded by the processor did not participate in segment access checks. The #TS handler must verify that all segments are accessible before returning to the interrupted task. 

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