[vbox-dev] ICH9 MSI handling
apallapothu at gmail.com
Tue Dec 29 04:44:24 UTC 2015
I was able to get my device working for MSI Interrupts Non-masking.
Problem was 3 folded.
1) A) Added new msiMaskEnabled function to do appropriate checkings
B) Existing check conditions inside MsiNotify are specifically
isolated incase of Non-Masking.
2) I invoke exclusive register write access to MSI control at the very
end of my constructor (after MSI registration call)
3) msiIs64Bit never returned functionally appropriate/true value. So I
modified this function to return appropriate value by reading control
config & 0x80
On Mon, Dec 28, 2015 at 4:50 AM, Michal Necasek <michal.necasek at oracle.com>
> Hmm, that doesn't make sense to me. The mask bits do not overlap anything
> else. I'm looking at figure 6-9 on page 233 of the PCI 3.0 specification.
> The code in MsiCommon.cpp is clear enough. Are you failing to set the
> fMsi64bit flag when registering the MSI capability?
> You probably also noticed that MsiInit() always sets the
> BOX_PCI_MSI_FLAGS_MASKBIT and there is currently no way to register an
> emulated device without MSI per-vector masking. That should not cause
> trouble since guest software does not have to use masking.
> - Michal
> ----- Original Message -----
> From: apallapothu at gmail.com
> To: vbox-dev at virtualbox.org
> Sent: Monday, December 21, 2015 5:16:15 AM GMT +01:00 Amsterdam / Berlin /
> Bern / Rome / Stockholm / Vienna
> Subject: [vbox-dev] ICH9 MSI handling
> Hello Developers,
> I am experimenting on ICH9 with a pluggable device. Reason for using
> ICH9 is MSI support.
> Following through AHCI, HPET device I see that code is aligned for
> specific mode of MSI configuration, "Per-Vector Masking Capable".
> MsiNotify function reads Mask Bits, Pending Bits without
> conditionally checking whether device is Per-Vector Masking Capable. So, by
> default code thinks offset 0xC reg as mask data where infact it is MSI data
> with Interrupt Vector ID incase of masking disabled. iVector value seems to
> be confusing too.
> My particular device needs to be configured for 64 bit MSI address
> capable and Mask disabled, so, MSI_MSG_CNTL @ MSI capability offset 0x02 =
> Can someone please suggest, recommend changes to handle this mode of
> MSI operation ?
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