- Timestamp:
- May 26, 2023 1:20:46 AM (16 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 7 edited
-
VMMAll/IEMAll.cpp (modified) (3 diffs)
-
VMMAll/IEMAllCImpl.cpp (modified) (59 diffs)
-
VMMAll/IEMAllCImplSvmInstr.cpp (modified) (9 diffs)
-
VMMAll/IEMAllInstructionsOneByte.cpp.h (modified) (14 diffs)
-
VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
-
include/IEMInline.h (modified) (2 diffs)
-
include/IEMInternal.h (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r99983 r99984 3815 3815 * Check and handle if the event being raised is intercepted. 3816 3816 */ 3817 VBOXSTRICTRC rcStrict0 = iemHandleSvmEventIntercept(pVCpu, u8Vector, fFlags, uErr, uCr2);3817 VBOXSTRICTRC rcStrict0 = iemHandleSvmEventIntercept(pVCpu, cbInstr, u8Vector, fFlags, uErr, uCr2); 3818 3818 if (rcStrict0 != VINF_SVM_INTERCEPT_NOT_ACTIVE) 3819 3819 return rcStrict0; … … 11225 11225 11226 11226 iemInitExec(pVCpu, false /*fBypassHandlers*/); 11227 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_3(iemCImpl_out, u16Port, fImm, cbReg); 11227 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_3(iemCImpl_out, u16Port, cbReg, 11228 ((uint8_t)fImm << 7) | 0xf /** @todo never worked with intercepts */); 11228 11229 Assert(!pVCpu->iem.s.cActiveMappings); 11229 11230 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict); … … 11248 11249 11249 11250 iemInitExec(pVCpu, false /*fBypassHandlers*/); 11250 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_3(iemCImpl_in, u16Port, fImm, cbReg); 11251 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_3(iemCImpl_in, u16Port, cbReg, 11252 ((uint8_t)fImm << 7) | 0xf /** @todo never worked with intercepts */); 11251 11253 Assert(!pVCpu->iem.s.cActiveMappings); 11252 11254 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict); -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
r99983 r99984 32 32 #define LOG_GROUP LOG_GROUP_IEM 33 33 #define VMCPU_INCL_CPUM_GST_CTX 34 ///@todo #define IEM_WITH_OPAQUE_DECODER_STATE 34 35 #include <VBox/vmm/iem.h> 35 36 #include <VBox/vmm/cpum.h> … … 622 623 { 623 624 Log2(("pushf: Guest intercept -> #VMEXIT\n")); 624 IEM_SVM_UPDATE_NRIP(pVCpu );625 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 625 626 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 626 627 } … … 688 689 { 689 690 Log2(("popf: Guest intercept -> #VMEXIT\n")); 690 IEM_SVM_UPDATE_NRIP(pVCpu );691 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 691 692 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 692 693 } … … 3965 3966 { 3966 3967 Log(("iret: Guest intercept -> #VMEXIT\n")); 3967 IEM_SVM_UPDATE_NRIP(pVCpu );3968 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 3968 3969 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 3969 3970 } … … 4268 4269 /** 4269 4270 * Implements SYSRET (AMD and Intel64). 4270 */ 4271 IEM_CIMPL_DEF_0(iemCImpl_sysret) 4271 * 4272 * @param enmEffOpSize The effective operand size. 4273 */ 4274 IEM_CIMPL_DEF_1(iemCImpl_sysret, IEMMODE, enmEffOpSize) 4272 4275 4273 4276 { … … 4307 4310 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL; 4308 4311 uint16_t uNewSs = uNewCs + 8; 4309 if ( pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)4312 if (enmEffOpSize == IEMMODE_64BIT) 4310 4313 uNewCs += 16; 4311 4314 if (uNewCs == 0 || uNewSs == 0) … … 4320 4323 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu))) 4321 4324 { 4322 if ( pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)4325 if (enmEffOpSize == IEMMODE_64BIT) 4323 4326 { 4324 4327 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11)); … … 5132 5135 { 5133 5136 Log(("lgdt: Guest intercept -> #VMEXIT\n")); 5134 IEM_SVM_UPDATE_NRIP(pVCpu );5137 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5135 5138 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5136 5139 } … … 5184 5187 { 5185 5188 Log(("sgdt: Guest intercept -> #VMEXIT\n")); 5186 IEM_SVM_UPDATE_NRIP(pVCpu );5189 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5187 5190 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5188 5191 } … … 5212 5215 { 5213 5216 Log(("lidt: Guest intercept -> #VMEXIT\n")); 5214 IEM_SVM_UPDATE_NRIP(pVCpu );5217 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5215 5218 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5216 5219 } … … 5256 5259 { 5257 5260 Log(("sidt: Guest intercept -> #VMEXIT\n")); 5258 IEM_SVM_UPDATE_NRIP(pVCpu );5261 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5259 5262 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5260 5263 } … … 5310 5313 { 5311 5314 Log(("lldt: Guest intercept -> #VMEXIT\n")); 5312 IEM_SVM_UPDATE_NRIP(pVCpu );5315 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5313 5316 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5314 5317 } … … 5385 5388 { 5386 5389 Log(("lldt: Guest intercept -> #VMEXIT\n")); 5387 IEM_SVM_UPDATE_NRIP(pVCpu );5390 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5388 5391 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5389 5392 } … … 5419 5422 } 5420 5423 5421 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0 );5424 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0, cbInstr); 5422 5425 5423 5426 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR); … … 5441 5444 IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst) 5442 5445 { 5443 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0 );5446 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0, cbInstr); 5444 5447 5445 5448 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR); … … 5490 5493 { 5491 5494 Log(("ltr: Guest intercept -> #VMEXIT\n")); 5492 IEM_SVM_UPDATE_NRIP(pVCpu );5495 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5493 5496 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 5494 5497 } … … 5595 5598 } 5596 5599 5597 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0 );5600 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0, cbInstr); 5598 5601 5599 5602 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR); … … 5624 5627 } 5625 5628 5626 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0 );5629 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0, cbInstr); 5627 5630 5628 5631 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR); … … 5649 5652 { 5650 5653 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg)); 5651 IEM_SVM_UPDATE_NRIP(pVCpu );5654 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5652 5655 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg); 5653 5656 } … … 5760 5763 IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize) 5761 5764 { 5762 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */ );5765 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */, cbInstr); 5763 5766 5764 5767 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX … … 5807 5810 IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst) 5808 5811 { 5809 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */ );5812 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */, cbInstr); 5810 5813 5811 5814 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX … … 5971 5974 { 5972 5975 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg)); 5973 IEM_SVM_UPDATE_NRIP(pVCpu );5976 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5974 5977 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg); 5975 5978 } … … 5982 5985 Assert(enmAccessCrX != IEMACCESSCRX_CLTS); 5983 5986 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg)); 5984 IEM_SVM_UPDATE_NRIP(pVCpu );5987 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 5985 5988 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg); 5986 5989 } … … 6045 6048 { 6046 6049 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg)); 6047 IEM_SVM_UPDATE_NRIP(pVCpu );6050 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6048 6051 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg); 6049 6052 } … … 6115 6118 { 6116 6119 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg)); 6117 IEM_SVM_UPDATE_NRIP(pVCpu );6120 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6118 6121 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg); 6119 6122 } … … 6184 6187 { 6185 6188 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg)); 6186 IEM_SVM_UPDATE_NRIP(pVCpu );6189 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6187 6190 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg); 6188 6191 } … … 6279 6282 { 6280 6283 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg)); 6281 IEM_SVM_UPDATE_NRIP(pVCpu );6284 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6282 6285 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg); 6283 6286 } … … 6514 6517 { 6515 6518 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg)); 6516 IEM_SVM_UPDATE_NRIP(pVCpu );6519 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6517 6520 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf), 6518 6521 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */); … … 6631 6634 { 6632 6635 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg)); 6633 IEM_SVM_UPDATE_NRIP(pVCpu );6636 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6634 6637 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf), 6635 6638 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */); … … 6783 6786 { 6784 6787 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage)); 6785 IEM_SVM_UPDATE_NRIP(pVCpu );6788 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 6786 6789 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG, 6787 6790 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */); … … 6949 6952 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_INVD, cbInstr); 6950 6953 6951 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0 );6954 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0, cbInstr); 6952 6955 6953 6956 /* We currently take no action here. */ … … 6970 6973 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WBINVD, cbInstr); 6971 6974 6972 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0 );6975 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0, cbInstr); 6973 6976 6974 6977 /* We currently take no action here. */ … … 6980 6983 IEM_CIMPL_DEF_0(iemCImpl_rsm) 6981 6984 { 6982 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0 );6985 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0, cbInstr); 6983 6986 NOREF(cbInstr); 6984 6987 return iemRaiseUndefinedOpcode(pVCpu); … … 7017 7020 { 7018 7021 Log(("rdtsc: Guest intercept -> #VMEXIT\n")); 7019 IEM_SVM_UPDATE_NRIP(pVCpu );7022 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7020 7023 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7021 7024 } … … 7072 7075 { 7073 7076 Log(("rdtscp: Guest intercept -> #VMEXIT\n")); 7074 IEM_SVM_UPDATE_NRIP(pVCpu );7077 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7075 7078 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7076 7079 } … … 7121 7124 { 7122 7125 Log(("rdpmc: Guest intercept -> #VMEXIT\n")); 7123 IEM_SVM_UPDATE_NRIP(pVCpu );7126 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7124 7127 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7125 7128 } … … 7163 7166 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT)) 7164 7167 { 7165 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */ );7168 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */, cbInstr); 7166 7169 if (rcStrict == VINF_SVM_VMEXIT) 7167 7170 return VINF_SUCCESS; … … 7249 7252 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT)) 7250 7253 { 7251 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, idMsr, true /* fWrite */ );7254 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, idMsr, true /* fWrite */, cbInstr); 7252 7255 if (rcStrict == VINF_SVM_VMEXIT) 7253 7256 return VINF_SUCCESS; … … 7292 7295 * Implements 'IN eAX, port'. 7293 7296 * 7294 * @param u16Port The source port. 7295 * @param fImm Whether the port was specified through an immediate operand 7296 * or the implicit DX register. 7297 * @param cbReg The register size. 7298 */ 7299 IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg) 7297 * @param u16Port The source port. 7298 * @param cbReg The register size. 7299 * @param bImmAndEffAddrMode Bit 7: Whether the port was specified through an 7300 * immediate operand or the implicit DX register. 7301 * Bits 3-0: Effective address mode. 7302 */ 7303 IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode) 7300 7304 { 7301 7305 /* … … 7312 7316 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) 7313 7317 { 7314 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, fImm, cbReg, cbInstr);7318 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, RT_BOOL(bImmAndEffAddrMode & 0x80), cbReg, cbInstr); 7315 7319 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE) 7316 7320 return rcStrict; 7317 7321 } 7318 7322 #else 7319 RT_NOREF( fImm);7323 RT_NOREF(bImmAndEffAddrMode); 7320 7324 #endif 7321 7325 … … 7327 7331 { 7328 7332 uint8_t cAddrSizeBits; 7329 switch ( pVCpu->iem.s.enmEffAddrMode)7333 switch (bImmAndEffAddrMode & 0xf) 7330 7334 { 7331 7335 case IEMMODE_16BIT: cAddrSizeBits = 16; break; … … 7345 7349 } 7346 7350 } 7351 #else 7352 RT_NOREF(bImmAndEffAddrMode); 7347 7353 #endif 7348 7354 … … 7392 7398 * 7393 7399 * @param cbReg The register size. 7394 */ 7395 IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg) 7396 { 7397 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg); 7400 * @param enmEffAddrMode Effective address mode. 7401 */ 7402 IEM_CIMPL_DEF_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode) 7403 { 7404 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, cbReg, 0 /* fImm */ | enmEffAddrMode); 7398 7405 } 7399 7406 … … 7402 7409 * Implements 'OUT port, eAX'. 7403 7410 * 7404 * @param u16Port The destination port. 7405 * @param fImm Whether the port was specified through an immediate operand 7406 * or the implicit DX register. 7407 * @param cbReg The register size. 7408 */ 7409 IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg) 7411 * @param u16Port The destination port. 7412 * @param cbReg The register size. 7413 * @param bImmAndEffAddrMode Bit 7: Whether the port was specified through an 7414 * immediate operand or the implicit DX register. 7415 * Bits 3-0: Effective address mode. 7416 */ 7417 IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode) 7410 7418 { 7411 7419 /* … … 7422 7430 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) 7423 7431 { 7424 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, fImm, cbReg, cbInstr);7432 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, RT_BOOL(bImmAndEffAddrMode & 0x80), cbReg, cbInstr); 7425 7433 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE) 7426 7434 return rcStrict; 7427 7435 } 7428 7436 #else 7429 RT_NOREF( fImm);7437 RT_NOREF(bImmAndEffAddrMode); 7430 7438 #endif 7431 7439 … … 7437 7445 { 7438 7446 uint8_t cAddrSizeBits; 7439 switch ( pVCpu->iem.s.enmEffAddrMode)7447 switch (bImmAndEffAddrMode & 0xf) 7440 7448 { 7441 7449 case IEMMODE_16BIT: cAddrSizeBits = 16; break; … … 7455 7463 } 7456 7464 } 7465 #else 7466 RT_NOREF(bImmAndEffAddrMode); 7457 7467 #endif 7458 7468 … … 7500 7510 * 7501 7511 * @param cbReg The register size. 7502 */ 7503 IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg) 7504 { 7505 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg); 7512 * @param enmEffAddrMode Effective address mode. 7513 */ 7514 IEM_CIMPL_DEF_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode) 7515 { 7516 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, cbReg, 0 /* fImm */ | enmEffAddrMode); 7506 7517 } 7507 7518 … … 7624 7635 { 7625 7636 Log2(("hlt: Guest intercept -> #VMEXIT\n")); 7626 IEM_SVM_UPDATE_NRIP(pVCpu );7637 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7627 7638 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7628 7639 } … … 7714 7725 { 7715 7726 Log2(("monitor: Guest intercept -> #VMEXIT\n")); 7716 IEM_SVM_UPDATE_NRIP(pVCpu );7727 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7717 7728 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7718 7729 } … … 7805 7816 { 7806 7817 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n")); 7807 IEM_SVM_UPDATE_NRIP(pVCpu );7818 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7808 7819 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7809 7820 } … … 7811 7822 { 7812 7823 Log2(("mwait: Guest intercept -> #VMEXIT\n")); 7813 IEM_SVM_UPDATE_NRIP(pVCpu );7824 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7814 7825 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7815 7826 } … … 7971 7982 { 7972 7983 Log2(("cpuid: Guest intercept -> #VMEXIT\n")); 7973 IEM_SVM_UPDATE_NRIP(pVCpu );7984 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 7974 7985 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 7975 7986 } … … 8319 8330 { 8320 8331 Log2(("xsetbv: Guest intercept -> #VMEXIT\n")); 8321 IEM_SVM_UPDATE_NRIP(pVCpu );8332 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 8322 8333 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 8323 8334 } … … 9576 9587 * 9577 9588 * @param iStReg The other stack register. 9578 */ 9579 IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg) 9589 * @param uFpuOpcode The FPU opcode (for simplicity). 9590 */ 9591 IEM_CIMPL_DEF_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode) 9580 9592 { 9581 9593 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87); … … 9616 9628 } 9617 9629 9618 iemFpuUpdateOpcodeAndIpWorker (pVCpu, pFpuCtx);9630 iemFpuUpdateOpcodeAndIpWorkerEx(pVCpu, pFpuCtx, uFpuOpcode); 9619 9631 iemHlpUsedFpu(pVCpu); 9620 9632 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); … … 9625 9637 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'. 9626 9638 * 9627 * @param iStReg The other stack register. 9628 * @param pfnAImpl The assembly comparison implementation. 9629 * @param fPop Whether we should pop the stack when done or not. 9630 */ 9631 IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop) 9639 * @param iStReg The other stack register. 9640 * @param pfnAImpl The assembly comparison implementation. 9641 * @param uPopAndFpuOpcode Bits 15-0: The FPU opcode. 9642 * Bit 31: Whether we should pop the stack when 9643 * done or not. 9644 */ 9645 IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode) 9632 9646 { 9633 9647 Assert(iStReg < 8); … … 9648 9662 * Check if any of the register accesses causes #SF + #IA. 9649 9663 */ 9664 bool fPop = RT_BOOL(uPopAndFpuOpcode & RT_BIT_32(31)); 9650 9665 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw); 9651 9666 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK; … … 9690 9705 } 9691 9706 9692 iemFpuUpdateOpcodeAndIpWorker (pVCpu, pFpuCtx);9707 iemFpuUpdateOpcodeAndIpWorkerEx(pVCpu, pFpuCtx, (uint16_t)uPopAndFpuOpcode); 9693 9708 iemHlpUsedFpu(pVCpu); 9694 9709 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp
r99220 r99984 949 949 * @returns VBox strict status code. 950 950 * @param pVCpu The cross context virtual CPU structure of the calling thread. 951 * @param cbInstr The length of the instruction in bytes triggering the 952 * event. 951 953 * @param u8Vector The interrupt or exception vector. 952 954 * @param fFlags The exception flags (see IEM_XCPT_FLAGS_XXX). … … 954 956 * @param uCr2 The CR2 value in case of a \#PF exception. 955 957 */ 956 VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT 958 VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, 959 uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT 957 960 { 958 961 Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu))); … … 981 984 { 982 985 Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n")); 983 IEM_SVM_UPDATE_NRIP(pVCpu );986 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 984 987 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */); 985 988 } … … 1012 1015 } 1013 1016 if (u8Vector == X86_XCPT_BR) 1014 IEM_SVM_UPDATE_NRIP(pVCpu );1017 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 1015 1018 Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x " 1016 1019 "uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt, … … 1028 1031 uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0; 1029 1032 Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector)); 1030 IEM_SVM_UPDATE_NRIP(pVCpu );1033 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 1031 1034 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */); 1032 1035 } … … 1074 1077 { 1075 1078 Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port)); 1076 IEM_SVM_UPDATE_NRIP(pVCpu );1079 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 1077 1080 return iemSvmVmexit(pVCpu, SVM_EXIT_IOIO, IoExitInfo.u, pVCpu->cpum.GstCtx.rip + cbInstr); 1078 1081 } … … 1103 1106 * @param cbInstr The length of the MSR read/write instruction in bytes. 1104 1107 */ 1105 VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite ) RT_NOEXCEPT1108 VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT 1106 1109 { 1107 1110 /* … … 1131 1134 if (pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm] & RT_BIT(uMsrpmBit)) 1132 1135 { 1133 IEM_SVM_UPDATE_NRIP(pVCpu );1136 IEM_SVM_UPDATE_NRIP(pVCpu, cbInstr); 1134 1137 return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */); 1135 1138 } … … 1552 1555 1553 1556 if (fCheckIntercept) 1554 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0 );1557 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0, cbInstr); 1555 1558 1556 1559 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r99814 r99984 8566 8566 /** @todo Testcase: Check if this raises \#MF? Intel mentioned it not. AMD 8567 8567 * indicates that it does. */ 8568 IEM_MC_BEGIN( 1, 3);8568 IEM_MC_BEGIN(2, 3); 8569 8569 IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value1); 8570 8570 IEM_MC_LOCAL(PCRTFLOAT80U, pr80Value2); 8571 8571 IEM_MC_LOCAL(IEMFPURESULT, FpuRes); 8572 8572 IEM_MC_ARG_CONST(uint8_t, iStReg, /*=*/ IEM_GET_MODRM_RM_8(bRm), 0); 8573 IEM_MC_ARG_CONST(uint16_t, uFpuOpcode, /*=*/ pVCpu->iem.s.uFpuOpcode, 1); 8573 8574 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 8574 8575 IEM_MC_MAYBE_RAISE_FPU_XCPT(); … … 8580 8581 IEM_MC_STORE_FPU_RESULT(FpuRes, 0); 8581 8582 } IEM_MC_ELSE() { 8582 IEM_MC_CALL_CIMPL_ 1(iemCImpl_fxch_underflow, iStReg);8583 IEM_MC_CALL_CIMPL_2(iemCImpl_fxch_underflow, iStReg, uFpuOpcode); 8583 8584 } IEM_MC_ENDIF(); 8584 8585 … … 9859 9860 { 9860 9861 IEMOP_MNEMONIC(fucomi_st0_stN, "fucomi st0,stN"); 9861 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fucomi_r80_by_r80, false /*fPop*/); 9862 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fucomi_r80_by_r80, 9863 0 /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9862 9864 } 9863 9865 … … 9867 9869 { 9868 9870 IEMOP_MNEMONIC(fcomi_st0_stN, "fcomi st0,stN"); 9869 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, false /*fPop*/); 9871 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 9872 false /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 9870 9873 } 9871 9874 … … 10789 10792 { 10790 10793 IEMOP_MNEMONIC(fucomip_st0_stN, "fucomip st0,stN"); 10791 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, true /*fPop*/); 10794 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10795 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10792 10796 } 10793 10797 … … 10797 10801 { 10798 10802 IEMOP_MNEMONIC(fcomip_st0_stN, "fcomip st0,stN"); 10799 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, true /*fPop*/); 10803 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_fcomi_fucomi, IEM_GET_MODRM_RM_8(bRm), iemAImpl_fcomi_r80_by_r80, 10804 RT_BIT_32(31) /*fPop*/ | pVCpu->iem.s.uFpuOpcode); 10800 10805 } 10801 10806 … … 11354 11359 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11355 11360 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11356 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, true /* fImm */, 1);11361 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11357 11362 } 11358 11363 … … 11364 11369 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11365 11370 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11366 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, true /* fImm */, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4); 11371 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_in, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11372 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11367 11373 } 11368 11374 … … 11374 11380 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11375 11381 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11376 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, true /* fImm */, 1);11382 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, 1, 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11377 11383 } 11378 11384 … … 11384 11390 uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); 11385 11391 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11386 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, true /* fImm */, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4); 11392 return IEM_MC_DEFER_TO_CIMPL_3(iemCImpl_out, u8Imm, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11393 0x80 /* fImm */ | pVCpu->iem.s.enmEffAddrMode); 11387 11394 } 11388 11395 … … 11494 11501 IEMOP_MNEMONIC(in_AL_DX, "in AL,DX"); 11495 11502 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11496 return IEM_MC_DEFER_TO_CIMPL_ 1(iemCImpl_in_eAX_DX, 1);11503 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in_eAX_DX, 1, pVCpu->iem.s.enmEffAddrMode); 11497 11504 } 11498 11505 … … 11503 11510 IEMOP_MNEMONIC(in_eAX_DX, "in eAX,DX"); 11504 11511 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11505 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4); 11512 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_in_eAX_DX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11513 pVCpu->iem.s.enmEffAddrMode); 11506 11514 } 11507 11515 … … 11512 11520 IEMOP_MNEMONIC(out_DX_AL, "out DX,AL"); 11513 11521 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11514 return IEM_MC_DEFER_TO_CIMPL_ 1(iemCImpl_out_DX_eAX, 1);11522 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out_DX_eAX, 1, pVCpu->iem.s.enmEffAddrMode); 11515 11523 } 11516 11524 … … 11521 11529 IEMOP_MNEMONIC(out_DX_eAX, "out DX,eAX"); 11522 11530 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11523 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4); 11531 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_out_DX_eAX, pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT ? 2 : 4, 11532 pVCpu->iem.s.enmEffAddrMode); 11524 11533 } 11525 11534 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r99337 r99984 1973 1973 IEMOP_MNEMONIC(sysret, "sysret"); /** @todo 386 LOADALL */ 1974 1974 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1975 return IEM_MC_DEFER_TO_CIMPL_ 0(iemCImpl_sysret);1975 return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_sysret, pVCpu->iem.s.enmEffOpSize); 1976 1976 } 1977 1977 -
trunk/src/VBox/VMM/include/IEMInline.h
r99983 r99984 2368 2368 2369 2369 2370 #ifndef IEM_WITH_OPAQUE_DECODER_STATE 2371 /** 2372 * Updates the FOP, FPU.CS and FPUIP registers. 2370 /** 2371 * Updates the FOP, FPU.CS and FPUIP registers, extended version. 2373 2372 * 2374 2373 * @param pVCpu The cross context virtual CPU structure of the calling thread. 2375 2374 * @param pFpuCtx The FPU context. 2376 */ 2377 DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx) RT_NOEXCEPT 2378 { 2379 Assert(pVCpu->iem.s.uFpuOpcode != UINT16_MAX); 2380 pFpuCtx->FOP = pVCpu->iem.s.uFpuOpcode; 2375 * @param uFpuOpcode The FPU opcode value (see IEMCPU::uFpuOpcode). 2376 */ 2377 DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorkerEx(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx, uint16_t uFpuOpcode) RT_NOEXCEPT 2378 { 2379 Assert(uFpuOpcode != UINT16_MAX); 2380 pFpuCtx->FOP = uFpuOpcode; 2381 2381 /** @todo x87.CS and FPUIP needs to be kept seperately. */ 2382 2382 if (IEM_IS_REAL_OR_V86_MODE(pVCpu)) … … 2395 2395 *(uint64_t *)&pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip; 2396 2396 } 2397 2398 2399 #ifndef IEM_WITH_OPAQUE_DECODER_STATE 2400 /** 2401 * Updates the FOP, FPU.CS and FPUIP registers. 2402 * 2403 * @param pVCpu The cross context virtual CPU structure of the calling thread. 2404 * @param pFpuCtx The FPU context. 2405 */ 2406 DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx) RT_NOEXCEPT 2407 { 2408 Assert(pVCpu->iem.s.uFpuOpcode != UINT16_MAX); 2409 iemFpuUpdateOpcodeAndIpWorkerEx(pVCpu, pFpuCtx, pVCpu->iem.s.uFpuOpcode); 2410 } 2397 2411 #endif /* !IEM_WITH_OPAQUE_DECODER_STATE */ 2398 2399 2400 2412 2401 2413 -
trunk/src/VBox/VMM/include/IEMInternal.h
r99982 r99984 3816 3816 * NRIP if needed. 3817 3817 */ 3818 # define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2 ) \3818 # define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \ 3819 3819 do \ 3820 3820 { \ 3821 3821 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \ 3822 3822 { \ 3823 IEM_SVM_UPDATE_NRIP(a_pVCpu ); \3823 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \ 3824 3824 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \ 3825 3825 } \ … … 3827 3827 3828 3828 /** Checks and handles SVM nested-guest CR0 read intercept. */ 3829 # define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2 ) \3829 # define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \ 3830 3830 do \ 3831 3831 { \ … … 3834 3834 else \ 3835 3835 { \ 3836 IEM_SVM_UPDATE_NRIP(a_pVCpu ); \3836 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \ 3837 3837 IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \ 3838 3838 } \ … … 3842 3842 * Updates the NextRIP (NRI) field in the nested-guest VMCB. 3843 3843 */ 3844 # define IEM_SVM_UPDATE_NRIP(a_pVCpu ) \3844 # define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \ 3845 3845 do { \ 3846 3846 if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \ 3847 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \3847 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \ 3848 3848 } while (0) 3849 3849 3850 3850 #else 3851 # define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false) 3852 # define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false) 3853 # define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false) 3854 # define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false) 3855 # define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false) 3856 # define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false) 3857 # define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0) 3858 # define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0) 3859 # define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0) 3860 # define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0) 3861 # define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0) 3851 # define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false) 3852 # define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false) 3853 # define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false) 3854 # define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false) 3855 # define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false) 3856 # define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false) 3857 # define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0) 3858 # define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0) 3859 # define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \ 3860 a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0) 3861 # define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0) 3862 # define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0) 3862 3863 3863 3864 #endif … … 4178 4179 IEM_CIMPL_PROTO_0(iemCImpl_loadall286); 4179 4180 IEM_CIMPL_PROTO_0(iemCImpl_syscall); 4180 IEM_CIMPL_PROTO_ 0(iemCImpl_sysret);4181 IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize); 4181 4182 IEM_CIMPL_PROTO_0(iemCImpl_sysenter); 4182 4183 IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize); … … 4219 4220 IEM_CIMPL_PROTO_0(iemCImpl_rdmsr); 4220 4221 IEM_CIMPL_PROTO_0(iemCImpl_wrmsr); 4221 IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);4222 IEM_CIMPL_PROTO_ 1(iemCImpl_in_eAX_DX, uint8_t, cbReg);4223 IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);4224 IEM_CIMPL_PROTO_ 1(iemCImpl_out_DX_eAX, uint8_t, cbReg);4222 IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode); 4223 IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode); 4224 IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode); 4225 IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode); 4225 4226 IEM_CIMPL_PROTO_0(iemCImpl_cli); 4226 4227 IEM_CIMPL_PROTO_0(iemCImpl_sti); … … 4256 4257 IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc); 4257 4258 IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw); 4258 IEM_CIMPL_PROTO_ 1(iemCImpl_fxch_underflow, uint8_t, iStReg);4259 IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);4259 IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode); 4260 IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode); 4260 4261 /** @} */ 4261 4262 … … 4450 4451 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM 4451 4452 VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT; 4452 VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;4453 VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT; 4453 4454 VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg, 4454 4455 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT; 4455 VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite ) RT_NOEXCEPT;4456 VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT; 4456 4457 IEM_CIMPL_PROTO_0(iemCImpl_vmrun); 4457 4458 IEM_CIMPL_PROTO_0(iemCImpl_vmload);
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