- Timestamp:
- May 24, 2023 11:39:15 AM (16 months ago)
- Location:
- trunk
- Files:
-
- 5 edited
-
include/VBox/vmm/cpum-armv8.h (modified) (2 diffs)
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include/VBox/vmm/cpumctx-armv8.h (modified) (1 diff)
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include/iprt/armv8.h (modified) (4 diffs)
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src/VBox/VMM/VMMAll/CPUMAllSysRegs-armv8.cpp (modified) (7 diffs)
-
src/VBox/VMM/VMMR3/CPUM-armv8.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/cpum-armv8.h
r99576 r99956 68 68 /** Read from a GICv3 PE ICC system register. */ 69 69 kCpumSysRegRdFn_GicV3Icc, 70 /** Read from the OSLSR_EL1 syste register. */ 71 kCpumSysRegRdFn_OslsrEl1, 70 72 71 73 /** End of valid system register read function indexes. */ … … 92 94 /** Write to a GICv3 PE ICC system register. */ 93 95 kCpumSysRegWrFn_GicV3Icc, 96 /** Write to the OSLAR_EL1 syste register. */ 97 kCpumSysRegWrFn_OslarEl1, 94 98 95 99 /** End of valid system register write function indexes. */ -
trunk/include/VBox/vmm/cpumctx-armv8.h
r99379 r99956 157 157 uint32_t fPadding0; 158 158 159 /** OS lock status accessed through OSLAR_EL1 and OSLSR_EL1. */ 160 bool fOsLck; 161 162 uint8_t afPadding1[7]; 163 159 164 /** Externalized state tracker, CPUMCTX_EXTRN_XXX. */ 160 165 uint64_t fExtrn; 161 166 162 uint64_t au64Padding 1[2];167 uint64_t au64Padding2[1]; 163 168 } CPUMCTX; 164 169 -
trunk/include/iprt/armv8.h
r99739 r99956 185 185 /** @name System register IDs. 186 186 * @{ */ 187 /** OSLAR_EL1 register - RW. */187 /** OSLAR_EL1 register - WO. */ 188 188 #define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4) 189 /** OSLSR_EL1 register - R W. */189 /** OSLSR_EL1 register - RO. */ 190 190 #define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4) 191 191 /** OSDLR_EL1 register - RW. */ … … 1068 1068 /** @} */ 1069 1069 1070 1070 1071 /** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1) 1071 1072 * @{ */ … … 1074 1075 #define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0 1075 1076 /** @} */ 1076 1077 1077 1078 1078 … … 1091 1091 1092 1092 1093 /** @name OSLAR_EL1 - OS Lock Access Register. 1094 * @{ */ 1095 /** Bit 0 - The OS Lock status bit. */ 1096 #define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0) 1097 #define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0 1098 /** @} */ 1099 1100 1101 /** @name OSLSR_EL1 - OS Lock Status Register. 1102 * @{ */ 1103 /** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */ 1104 #define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0) 1105 #define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0 1106 /** Bit 1 - The OS Lock status bit. */ 1107 #define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1) 1108 #define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1 1109 /** Bit 2 - Not 32-bit access. */ 1110 #define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2) 1111 #define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2 1112 /** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */ 1113 #define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3) 1114 #define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3 1115 /** @} */ 1116 1117 1093 1118 /** @} */ 1094 1119 -
trunk/src/VBox/VMM/VMMAll/CPUMAllSysRegs-armv8.cpp
r99388 r99956 37 37 #include <VBox/err.h> 38 38 39 #include <iprt/armv8.h> 40 39 41 40 42 /********************************************************************************************************************************* … … 160 162 161 163 164 165 /** @callback_method_impl{FNCPUMRDSYSREG} */ 166 static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegRd_OslsrEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t *puValue) 167 { 168 RT_NOREF(idSysReg, pRange); 169 *puValue = pVCpu->cpum.s.Guest.fOsLck ? ARMV8_OSLSR_EL1_AARCH64_OSLK : 0; 170 return VINF_SUCCESS; 171 } 172 173 174 /** @callback_method_impl{FNCPUMWRSYSREG} */ 175 static DECLCALLBACK(VBOXSTRICTRC) cpumSysRegWr_OslarEl1(PVMCPUCC pVCpu, uint32_t idSysReg, PCCPUMSYSREGRANGE pRange, uint64_t uValue, uint64_t uRawValue) 176 { 177 RT_NOREF(idSysReg, pRange, uRawValue); 178 Assert(!(uValue & ~ARMV8_OSLAR_EL1_AARCH64_OSLK)); 179 pVCpu->cpum.s.Guest.fOsLck = RT_BOOL(uValue); 180 return VINF_SUCCESS; 181 } 182 183 162 184 /** 163 185 * System register read function table. … … 170 192 { cpumSysRegRd_WriteOnly }, 171 193 { cpumSysRegRd_GicV3Icc }, 194 { cpumSysRegRd_OslsrEl1 }, 172 195 }; 173 196 … … 183 206 { NULL }, /* Alias */ 184 207 { cpumSysRegWr_GicV3Icc }, 208 { cpumSysRegWr_OslarEl1 }, 185 209 }; 186 210 … … 402 426 STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWrites); 403 427 STAM_REL_COUNTER_INC(&pVM->cpum.s.cSysRegWritesUnknown); 404 rcStrict = VERR_CPUM_RAISE_GP_0; 428 rcStrict = VERR_CPUM_RAISE_GP_0; /** @todo Better status code. */ 405 429 } 406 430 return rcStrict; … … 425 449 CPUM_ASSERT_RD_SYSREG_FN(WriteOnly); 426 450 CPUM_ASSERT_RD_SYSREG_FN(GicV3Icc); 451 CPUM_ASSERT_RD_SYSREG_FN(OslsrEl1); 427 452 428 453 AssertReturn(g_aCpumWrSysRegFns[kCpumSysRegWrFn_Invalid].pfnWrSysReg == NULL, VERR_CPUM_IPE_2); … … 430 455 CPUM_ASSERT_WR_SYSREG_FN(ReadOnly); 431 456 CPUM_ASSERT_WR_SYSREG_FN(GicV3Icc); 457 CPUM_ASSERT_WR_SYSREG_FN(OslarEl1); 432 458 433 459 return VINF_SUCCESS; -
trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp
r99739 r99956 71 71 72 72 /********************************************************************************************************************************* 73 * Defined Constants And Macros * 74 *********************************************************************************************************************************/ 75 76 /** Internal form used by the macros. */ 77 #ifdef VBOX_WITH_STATISTICS 78 # define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \ 79 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \ 80 { 0 }, { 0 }, { 0 }, { 0 } } 81 #else 82 # define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \ 83 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName } 84 #endif 85 86 /** Function handlers, extended version. */ 87 #define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \ 88 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName) 89 /** Function handlers, read-only. */ 90 #define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \ 91 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName) 92 /** Read-only fixed value, ignores all writes. */ 93 #define MVI(a_uMsr, a_szName, a_uValue) \ 94 RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName) 95 96 97 /********************************************************************************************************************************* 73 98 * Structures and Typedefs * 74 99 *********************************************************************************************************************************/ … … 103 128 * Global Variables * 104 129 *********************************************************************************************************************************/ 130 /** 131 * System register ranges. 132 */ 133 static CPUMSYSREGRANGE const g_aSysRegRanges[] = 134 { 135 MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)), 136 MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1), 137 MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0) 138 }; 139 140 105 141 #if 0 /** @todo Will come later. */ 106 142 /** Saved state field descriptors for CPUMCTX. */ … … 185 221 186 222 /** 223 * Initializes the guest system register states. 224 * 225 * @returns VBox status code. 226 * @param pVM The cross context VM structure. 227 */ 228 static int cpumR3InitSysRegs(PVM pVM) 229 { 230 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++) 231 { 232 int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]); 233 AssertLogRelRCReturn(rc, rc); 234 } 235 236 return VINF_SUCCESS; 237 } 238 239 240 /** 187 241 * Initializes the CPUM. 188 242 * … … 228 282 229 283 rc = cpumR3DbgInit(pVM); 284 if (RT_FAILURE(rc)) 285 return rc; 286 287 /* 288 * Initialize the Guest system register states. 289 */ 290 rc = cpumR3InitSysRegs(pVM); 230 291 if (RT_FAILURE(rc)) 231 292 return rc;
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