VirtualBox

Changeset 99578 in vbox for trunk


Ignore:
Timestamp:
May 3, 2023 10:31:20 AM (17 months ago)
Author:
vboxsync
Message:

VMM/GIC: Continue implementation, bugref:10404

Location:
trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/VBox/gic.h

    r99485 r99578  
    4848/** Size of the distributor register frame. */
    4949#define GIC_DIST_REG_FRAME_SIZE                         _64K
     50
    5051/** Distributor Control Register - RW. */
    5152#define GIC_DIST_REG_CTLR_OFF                           0x0000
     53/** Bit 0 - Enable Group 0 interrupts. */
     54# define GIC_DIST_REG_CTRL_ENABLE_GRP0                  RT_BIT_32(0)
     55# define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT              0
     56/** Bit 1 - Enable Non-secure Group 1 interrupts. */
     57# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS               RT_BIT_32(1)
     58# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT           1
     59/** Bit 2 - Enable Secure Group 1 interrupts. */
     60# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S                RT_BIT_32(2)
     61# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT            2
     62/** Bit 4 - Affinity Routing Enable, Secure state. */
     63# define GIC_DIST_REG_CTRL_ARE_S                        RT_BIT_32(4)
     64# define GIC_DIST_REG_CTRL_ARE_S_BIT                    4
     65/** Bit 5 - Affinity Routing Enable, Non-secure state. */
     66# define GIC_DIST_REG_CTRL_ARE_NS                       RT_BIT_32(5)
     67# define GIC_DIST_REG_CTRL_ARE_NS_BIT                   5
     68/** Bit 6 - Disable Security. */
     69# define GIC_DIST_REG_CTRL_DS                           RT_BIT_32(6)
     70# define GIC_DIST_REG_CTRL_DS_BIT                       6
     71/** Bit 7 - Enable 1 of N Wakeup Functionality. */
     72# define GIC_DIST_REG_CTRL_E1NWF                        RT_BIT_32(7)
     73# define GIC_DIST_REG_CTRL_E1NWF_BIT                    7
     74/** Bit 31 - Register Write Pending. */
     75# define GIC_DIST_REG_CTRL_RWP                          RT_BIT_32(31)
     76# define GIC_DIST_REG_CTRL_RWP_BIT                      31
     77
    5278/** Interrupt Controller Type Register - RO. */
    5379#define GIC_DIST_REG_TYPER_OFF                          0x0004
     80/** Bit 0 - 4 - Maximum number of SPIs supported. */
     81# define GIC_DIST_REG_TYPER_NUM_ITLINES                 (  RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT(2) \
     82                                                         | RT_BIT_32(3) | RT_BIT_32(4))
     83# define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis)  ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES)
     84/** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */
     85# define GIC_DIST_REG_TYPER_NUM_PES                     (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT(7))
     86# define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes)          (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES)
     87/** Bit 8 - Extended SPI range implemented. */
     88# define GIC_DIST_REG_TYPER_ESPI                        RT_BIT_32(8)
     89# define GIC_DIST_REG_TYPER_ESPI_BIT                    8
     90/** Bit 9 - Non-maskable interrupt priority supported. */
     91# define GIC_DIST_REG_TYPER_NMI                         RT_BIT_32(9)
     92# define GIC_DIST_REG_TYPER_NMI_BIT                     9
     93/** Bit 10 - Indicates whether the implementation supports two security states. */
     94# define GIC_DIST_REG_TYPER_SECURITY_EXTN               RT_BIT_32(10)
     95# define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT           10
     96/** Bit 11 - 15 - The number of supported LPIs. */
     97# define GIC_DIST_REG_TYPER_NUM_LPIS                    (  RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT(13) \
     98                                                         | RT_BIT_32(14) | RT_BIT_32(15))
     99# define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis)        (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS)
     100/** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */
     101# define GIC_DIST_REG_TYPER_MBIS                        RT_BIT_32(16)
     102# define GIC_DIST_REG_TYPER_MBIS_BIT                    16
     103/** Bit 17 - Indicates whether the implementation supports LPIs. */
     104# define GIC_DIST_REG_TYPER_LPIS                        RT_BIT_32(17)
     105# define GIC_DIST_REG_TYPER_LPIS_BIT                    17
     106/** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */
     107# define GIC_DIST_REG_TYPER_DVIS                        RT_BIT_32(18)
     108# define GIC_DIST_REG_TYPER_DVIS_BIT                    18
     109/** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */
     110# define GIC_DIST_REG_TYPER_IDBITS                      (  RT_BIT_32(19) | RT_BIT_32(20) | RT_BIT(21) \
     111                                                         | RT_BIT_32(22) | RT_BIT_32(23))
     112# define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits)          (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS)
     113/** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */
     114# define GIC_DIST_REG_TYPER_A3V                         RT_BIT_32(24)
     115# define GIC_DIST_REG_TYPER_A3V_BIT                     24
     116/** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */
     117# define GIC_DIST_REG_TYPER_NO1N                        RT_BIT_32(25)
     118# define GIC_DIST_REG_TYPER_NO1N_BIT                    25
     119/** Bit 26 - Range Selector Support. */
     120# define GIC_DIST_REG_TYPER_RSS                         RT_BIT_32(26)
     121# define GIC_DIST_REG_TYPER_RSS_BIT                     26
     122/** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */
     123# define GIC_DIST_REG_TYPER_ESPI_RANGE                  (  RT_BIT_32(27) | RT_BIT_32(28) | RT_BIT(29) \
     124                                                         | RT_BIT_32(30) | RT_BIT_32(31))
     125# define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range)     (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE)
     126
    54127/** Distributor Implementer Identification Register - RO. */
    55128#define GIC_DIST_REG_IIDR_OFF                           0x0008
     
    210283/** Distributor Peripheral ID2 Register - RO. */
    211284#define GIC_DIST_REG_PIDR2_OFF                          0xffe8
     285/** Bit 4 - 7 - GIC architecture revision */
     286# define GIC_DIST_REG_PIDR2_ARCH_REV                    (  RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
     287                                                         | RT_BIT_32(7))
     288# define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev)     (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
     289/** GICv1 architecture revision. */
     290#  define GIC_DIST_REG_PIDR2_ARCH_REV_GICV1             0x1
     291/** GICv2 architecture revision. */
     292#  define GIC_DIST_REG_PIDR2_ARCH_REV_GICV2             0x2
     293/** GICv3 architecture revision. */
     294#  define GIC_DIST_REG_PIDR2_ARCH_REV_GICV3             0x3
     295/** GICv4 architecture revision. */
     296#  define GIC_DIST_REG_PIDR2_ARCH_REV_GICV4             0x4
    212297/** @} */
    213298
     
    248333/** Redistributor Peripheral ID2 Register - RO. */
    249334#define GIC_REDIST_REG_PIDR2_OFF                        0xffe8
     335/** Bit 4 - 7 - GIC architecture revision */
     336# define GIC_REDIST_REG_PIDR2_ARCH_REV                  (  RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
     337                                                         | RT_BIT_32(7))
     338# define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev)   (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
     339/** GICv1 architecture revision. */
     340#  define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV1           0x1
     341/** GICv2 architecture revision. */
     342#  define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV2           0x2
     343/** GICv3 architecture revision. */
     344#  define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3           0x3
     345/** GICv4 architecture revision. */
     346#  define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV4           0x4
    250347/** @} */
    251348
  • trunk/src/VBox/VMM/VMMAll/GICAll.cpp

    r99492 r99578  
    5252*********************************************************************************************************************************/
    5353/**
    54  * Reads a GIC register.
     54 * Reads a GIC distributor register.
    5555 *
    5656 * @returns VBox status code.
     
    6060 * @param   puValue         Where to store the register value.
    6161 */
    62 DECLINLINE(VBOXSTRICTRC) gicReadRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue)
     62DECLINLINE(VBOXSTRICTRC) gicDistRegisterRead(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue)
    6363{
    6464    VMCPU_ASSERT_EMT(pVCpu);
    6565    RT_NOREF(pDevIns, pVCpu, offReg);
    6666
    67     *puValue = 0;
    68     return VINF_SUCCESS;
    69 }
    70 
    71 
    72 /**
    73  * Writes a GIC register.
     67    switch (offReg)
     68    {
     69        case GIC_DIST_REG_TYPER_OFF:
     70            *puValue =   GIC_DIST_REG_TYPER_NUM_ITLINES_SET(0)  /** @todo 32 SPIs for now. */
     71                       | GIC_DIST_REG_TYPER_NUM_PES_SET(0)      /* 1 PE */
     72                       /*| GIC_DIST_REG_TYPER_ESPI*/            /** @todo */
     73                       /*| GIC_DIST_REG_TYPER_NMI*/             /** @todo Non-maskable interrupts */
     74                       /*| GIC_DIST_REG_TYPER_SECURITY_EXTN */  /** @todo */
     75                       /*| GIC_DIST_REG_TYPER_MBIS */           /** @todo Message based interrupts */
     76                       /*| GIC_DIST_REG_TYPER_LPIS */           /** @todo Support LPIs */
     77                       | GIC_DIST_REG_TYPER_IDBITS_SET(16);
     78            break;
     79        case GIC_DIST_REG_PIDR2_OFF:
     80            *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3);
     81            break;
     82        case GIC_DIST_REG_IIDR_OFF:
     83        case GIC_DIST_REG_TYPER2_OFF:
     84        default:
     85            *puValue = 0;
     86    }
     87    return VINF_SUCCESS;
     88}
     89
     90
     91/**
     92 * Writes a GIC distributor register.
    7493 *
    7594 * @returns Strict VBox status code.
     
    7998 * @param   uValue          The register value.
    8099 */
    81 DECLINLINE(VBOXSTRICTRC) gicWriteRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue)
     100DECLINLINE(VBOXSTRICTRC) gicDistRegisterWrite(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue)
     101{
     102    VMCPU_ASSERT_EMT(pVCpu);
     103    RT_NOREF(pDevIns, pVCpu, offReg, uValue);
     104
     105    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
     106    return rcStrict;
     107}
     108
     109
     110/**
     111 * Reads a GIC redistributor register.
     112 *
     113 * @returns VBox status code.
     114 * @param   pDevIns         The device instance.
     115 * @param   pVCpu           The cross context virtual CPU structure.
     116 * @param   offReg          The offset of the register being read.
     117 * @param   puValue         Where to store the register value.
     118 */
     119DECLINLINE(VBOXSTRICTRC) gicReDistRegisterRead(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue)
     120{
     121    VMCPU_ASSERT_EMT(pVCpu);
     122    RT_NOREF(pDevIns, pVCpu, offReg);
     123
     124    switch (offReg)
     125    {
     126        case GIC_REDIST_REG_PIDR2_OFF:
     127            *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3);
     128            break;
     129        default:
     130            *puValue = 0;
     131    }
     132
     133    return VINF_SUCCESS;
     134}
     135
     136
     137/**
     138 * Writes a GIC redistributor register.
     139 *
     140 * @returns Strict VBox status code.
     141 * @param   pDevIns         The device instance.
     142 * @param   pVCpu           The cross context virtual CPU structure.
     143 * @param   offReg          The offset of the register being written.
     144 * @param   uValue          The register value.
     145 */
     146DECLINLINE(VBOXSTRICTRC) gicReDistRegisterWrite(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue)
    82147{
    83148    VMCPU_ASSERT_EMT(pVCpu);
     
    155220
    156221    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
    157     uint16_t offReg   = off & 0xff0;
     222    uint16_t offReg   = off & 0xfffc;
    158223    uint32_t uValue   = 0;
    159224
    160225    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioRead));
    161226
    162     VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicReadRegister(pDevIns, pVCpu, offReg, &uValue));
     227    VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicDistRegisterRead(pDevIns, pVCpu, offReg, &uValue));
    163228    *(uint32_t *)pv = uValue;
    164229
    165     Log2(("GIC%u: gicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     230    Log2(("GIC%u: gicDistMmioRead: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    166231    return rc;
    167232}
     
    178243
    179244    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
    180     uint16_t offReg   = off & 0xff0;
     245    uint16_t offReg   = off & 0xfffc;
    181246    uint32_t uValue   = *(uint32_t *)pv;
    182247
    183248    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioWrite));
    184249
    185     Log2(("GIC%u: gicWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    186     return gicWriteRegister(pDevIns, pVCpu, offReg, uValue);
     250    Log2(("GIC%u: gicDistMmioWrite: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     251    return gicDistRegisterWrite(pDevIns, pVCpu, offReg, uValue);
    187252}
    188253
     
    198263
    199264    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
    200     uint16_t offReg   = off & 0xff0;
     265    uint16_t offReg   = off & 0xfffc;
    201266    uint32_t uValue   = 0;
    202267
    203268    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioRead));
    204269
    205     VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicReadRegister(pDevIns, pVCpu, offReg, &uValue));
     270    VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicReDistRegisterRead(pDevIns, pVCpu, offReg, &uValue));
    206271    *(uint32_t *)pv = uValue;
    207272
    208     Log2(("GIC%u: gicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     273    Log2(("GIC%u: gicReDistMmioRead: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    209274    return rc;
    210275}
     
    221286
    222287    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
    223     uint16_t offReg   = off & 0xff0;
     288    uint16_t offReg   = off & 0xfffc;
    224289    uint32_t uValue   = *(uint32_t *)pv;
    225290
    226291    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioWrite));
    227292
    228     Log2(("GIC%u: gicWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    229     return gicWriteRegister(pDevIns, pVCpu, offReg, uValue);
     293    Log2(("GIC%u: gicReDistMmioWrite: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     294    return gicReDistRegisterWrite(pDevIns, pVCpu, offReg, uValue);
    230295}
    231296
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