- Timestamp:
- May 3, 2023 10:31:20 AM (17 months ago)
- Location:
- trunk
- Files:
-
- 2 edited
-
include/VBox/gic.h (modified) (3 diffs)
-
src/VBox/VMM/VMMAll/GICAll.cpp (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/gic.h
r99485 r99578 48 48 /** Size of the distributor register frame. */ 49 49 #define GIC_DIST_REG_FRAME_SIZE _64K 50 50 51 /** Distributor Control Register - RW. */ 51 52 #define GIC_DIST_REG_CTLR_OFF 0x0000 53 /** Bit 0 - Enable Group 0 interrupts. */ 54 # define GIC_DIST_REG_CTRL_ENABLE_GRP0 RT_BIT_32(0) 55 # define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT 0 56 /** Bit 1 - Enable Non-secure Group 1 interrupts. */ 57 # define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS RT_BIT_32(1) 58 # define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT 1 59 /** Bit 2 - Enable Secure Group 1 interrupts. */ 60 # define GIC_DIST_REG_CTRL_ENABLE_GRP1_S RT_BIT_32(2) 61 # define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT 2 62 /** Bit 4 - Affinity Routing Enable, Secure state. */ 63 # define GIC_DIST_REG_CTRL_ARE_S RT_BIT_32(4) 64 # define GIC_DIST_REG_CTRL_ARE_S_BIT 4 65 /** Bit 5 - Affinity Routing Enable, Non-secure state. */ 66 # define GIC_DIST_REG_CTRL_ARE_NS RT_BIT_32(5) 67 # define GIC_DIST_REG_CTRL_ARE_NS_BIT 5 68 /** Bit 6 - Disable Security. */ 69 # define GIC_DIST_REG_CTRL_DS RT_BIT_32(6) 70 # define GIC_DIST_REG_CTRL_DS_BIT 6 71 /** Bit 7 - Enable 1 of N Wakeup Functionality. */ 72 # define GIC_DIST_REG_CTRL_E1NWF RT_BIT_32(7) 73 # define GIC_DIST_REG_CTRL_E1NWF_BIT 7 74 /** Bit 31 - Register Write Pending. */ 75 # define GIC_DIST_REG_CTRL_RWP RT_BIT_32(31) 76 # define GIC_DIST_REG_CTRL_RWP_BIT 31 77 52 78 /** Interrupt Controller Type Register - RO. */ 53 79 #define GIC_DIST_REG_TYPER_OFF 0x0004 80 /** Bit 0 - 4 - Maximum number of SPIs supported. */ 81 # define GIC_DIST_REG_TYPER_NUM_ITLINES ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT(2) \ 82 | RT_BIT_32(3) | RT_BIT_32(4)) 83 # define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis) ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES) 84 /** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */ 85 # define GIC_DIST_REG_TYPER_NUM_PES (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT(7)) 86 # define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes) (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES) 87 /** Bit 8 - Extended SPI range implemented. */ 88 # define GIC_DIST_REG_TYPER_ESPI RT_BIT_32(8) 89 # define GIC_DIST_REG_TYPER_ESPI_BIT 8 90 /** Bit 9 - Non-maskable interrupt priority supported. */ 91 # define GIC_DIST_REG_TYPER_NMI RT_BIT_32(9) 92 # define GIC_DIST_REG_TYPER_NMI_BIT 9 93 /** Bit 10 - Indicates whether the implementation supports two security states. */ 94 # define GIC_DIST_REG_TYPER_SECURITY_EXTN RT_BIT_32(10) 95 # define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT 10 96 /** Bit 11 - 15 - The number of supported LPIs. */ 97 # define GIC_DIST_REG_TYPER_NUM_LPIS ( RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT(13) \ 98 | RT_BIT_32(14) | RT_BIT_32(15)) 99 # define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis) (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS) 100 /** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */ 101 # define GIC_DIST_REG_TYPER_MBIS RT_BIT_32(16) 102 # define GIC_DIST_REG_TYPER_MBIS_BIT 16 103 /** Bit 17 - Indicates whether the implementation supports LPIs. */ 104 # define GIC_DIST_REG_TYPER_LPIS RT_BIT_32(17) 105 # define GIC_DIST_REG_TYPER_LPIS_BIT 17 106 /** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */ 107 # define GIC_DIST_REG_TYPER_DVIS RT_BIT_32(18) 108 # define GIC_DIST_REG_TYPER_DVIS_BIT 18 109 /** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */ 110 # define GIC_DIST_REG_TYPER_IDBITS ( RT_BIT_32(19) | RT_BIT_32(20) | RT_BIT(21) \ 111 | RT_BIT_32(22) | RT_BIT_32(23)) 112 # define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits) (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS) 113 /** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */ 114 # define GIC_DIST_REG_TYPER_A3V RT_BIT_32(24) 115 # define GIC_DIST_REG_TYPER_A3V_BIT 24 116 /** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */ 117 # define GIC_DIST_REG_TYPER_NO1N RT_BIT_32(25) 118 # define GIC_DIST_REG_TYPER_NO1N_BIT 25 119 /** Bit 26 - Range Selector Support. */ 120 # define GIC_DIST_REG_TYPER_RSS RT_BIT_32(26) 121 # define GIC_DIST_REG_TYPER_RSS_BIT 26 122 /** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */ 123 # define GIC_DIST_REG_TYPER_ESPI_RANGE ( RT_BIT_32(27) | RT_BIT_32(28) | RT_BIT(29) \ 124 | RT_BIT_32(30) | RT_BIT_32(31)) 125 # define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range) (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE) 126 54 127 /** Distributor Implementer Identification Register - RO. */ 55 128 #define GIC_DIST_REG_IIDR_OFF 0x0008 … … 210 283 /** Distributor Peripheral ID2 Register - RO. */ 211 284 #define GIC_DIST_REG_PIDR2_OFF 0xffe8 285 /** Bit 4 - 7 - GIC architecture revision */ 286 # define GIC_DIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \ 287 | RT_BIT_32(7)) 288 # define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV) 289 /** GICv1 architecture revision. */ 290 # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV1 0x1 291 /** GICv2 architecture revision. */ 292 # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV2 0x2 293 /** GICv3 architecture revision. */ 294 # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV3 0x3 295 /** GICv4 architecture revision. */ 296 # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV4 0x4 212 297 /** @} */ 213 298 … … 248 333 /** Redistributor Peripheral ID2 Register - RO. */ 249 334 #define GIC_REDIST_REG_PIDR2_OFF 0xffe8 335 /** Bit 4 - 7 - GIC architecture revision */ 336 # define GIC_REDIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \ 337 | RT_BIT_32(7)) 338 # define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV) 339 /** GICv1 architecture revision. */ 340 # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV1 0x1 341 /** GICv2 architecture revision. */ 342 # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV2 0x2 343 /** GICv3 architecture revision. */ 344 # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3 0x3 345 /** GICv4 architecture revision. */ 346 # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV4 0x4 250 347 /** @} */ 251 348 -
trunk/src/VBox/VMM/VMMAll/GICAll.cpp
r99492 r99578 52 52 *********************************************************************************************************************************/ 53 53 /** 54 * Reads a GIC register.54 * Reads a GIC distributor register. 55 55 * 56 56 * @returns VBox status code. … … 60 60 * @param puValue Where to store the register value. 61 61 */ 62 DECLINLINE(VBOXSTRICTRC) gic ReadRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue)62 DECLINLINE(VBOXSTRICTRC) gicDistRegisterRead(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue) 63 63 { 64 64 VMCPU_ASSERT_EMT(pVCpu); 65 65 RT_NOREF(pDevIns, pVCpu, offReg); 66 66 67 *puValue = 0; 68 return VINF_SUCCESS; 69 } 70 71 72 /** 73 * Writes a GIC register. 67 switch (offReg) 68 { 69 case GIC_DIST_REG_TYPER_OFF: 70 *puValue = GIC_DIST_REG_TYPER_NUM_ITLINES_SET(0) /** @todo 32 SPIs for now. */ 71 | GIC_DIST_REG_TYPER_NUM_PES_SET(0) /* 1 PE */ 72 /*| GIC_DIST_REG_TYPER_ESPI*/ /** @todo */ 73 /*| GIC_DIST_REG_TYPER_NMI*/ /** @todo Non-maskable interrupts */ 74 /*| GIC_DIST_REG_TYPER_SECURITY_EXTN */ /** @todo */ 75 /*| GIC_DIST_REG_TYPER_MBIS */ /** @todo Message based interrupts */ 76 /*| GIC_DIST_REG_TYPER_LPIS */ /** @todo Support LPIs */ 77 | GIC_DIST_REG_TYPER_IDBITS_SET(16); 78 break; 79 case GIC_DIST_REG_PIDR2_OFF: 80 *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3); 81 break; 82 case GIC_DIST_REG_IIDR_OFF: 83 case GIC_DIST_REG_TYPER2_OFF: 84 default: 85 *puValue = 0; 86 } 87 return VINF_SUCCESS; 88 } 89 90 91 /** 92 * Writes a GIC distributor register. 74 93 * 75 94 * @returns Strict VBox status code. … … 79 98 * @param uValue The register value. 80 99 */ 81 DECLINLINE(VBOXSTRICTRC) gicWriteRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue) 100 DECLINLINE(VBOXSTRICTRC) gicDistRegisterWrite(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue) 101 { 102 VMCPU_ASSERT_EMT(pVCpu); 103 RT_NOREF(pDevIns, pVCpu, offReg, uValue); 104 105 VBOXSTRICTRC rcStrict = VINF_SUCCESS; 106 return rcStrict; 107 } 108 109 110 /** 111 * Reads a GIC redistributor register. 112 * 113 * @returns VBox status code. 114 * @param pDevIns The device instance. 115 * @param pVCpu The cross context virtual CPU structure. 116 * @param offReg The offset of the register being read. 117 * @param puValue Where to store the register value. 118 */ 119 DECLINLINE(VBOXSTRICTRC) gicReDistRegisterRead(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t *puValue) 120 { 121 VMCPU_ASSERT_EMT(pVCpu); 122 RT_NOREF(pDevIns, pVCpu, offReg); 123 124 switch (offReg) 125 { 126 case GIC_REDIST_REG_PIDR2_OFF: 127 *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3); 128 break; 129 default: 130 *puValue = 0; 131 } 132 133 return VINF_SUCCESS; 134 } 135 136 137 /** 138 * Writes a GIC redistributor register. 139 * 140 * @returns Strict VBox status code. 141 * @param pDevIns The device instance. 142 * @param pVCpu The cross context virtual CPU structure. 143 * @param offReg The offset of the register being written. 144 * @param uValue The register value. 145 */ 146 DECLINLINE(VBOXSTRICTRC) gicReDistRegisterWrite(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint16_t offReg, uint32_t uValue) 82 147 { 83 148 VMCPU_ASSERT_EMT(pVCpu); … … 155 220 156 221 PVMCPUCC pVCpu = PDMDevHlpGetVMCPU(pDevIns); 157 uint16_t offReg = off & 0xff 0;222 uint16_t offReg = off & 0xfffc; 158 223 uint32_t uValue = 0; 159 224 160 225 STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioRead)); 161 226 162 VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gic ReadRegister(pDevIns, pVCpu, offReg, &uValue));227 VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicDistRegisterRead(pDevIns, pVCpu, offReg, &uValue)); 163 228 *(uint32_t *)pv = uValue; 164 229 165 Log2(("GIC%u: gic ReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));230 Log2(("GIC%u: gicDistMmioRead: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue)); 166 231 return rc; 167 232 } … … 178 243 179 244 PVMCPUCC pVCpu = PDMDevHlpGetVMCPU(pDevIns); 180 uint16_t offReg = off & 0xff 0;245 uint16_t offReg = off & 0xfffc; 181 246 uint32_t uValue = *(uint32_t *)pv; 182 247 183 248 STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioWrite)); 184 249 185 Log2(("GIC%u: gic WriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));186 return gic WriteRegister(pDevIns, pVCpu, offReg, uValue);250 Log2(("GIC%u: gicDistMmioWrite: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue)); 251 return gicDistRegisterWrite(pDevIns, pVCpu, offReg, uValue); 187 252 } 188 253 … … 198 263 199 264 PVMCPUCC pVCpu = PDMDevHlpGetVMCPU(pDevIns); 200 uint16_t offReg = off & 0xff 0;265 uint16_t offReg = off & 0xfffc; 201 266 uint32_t uValue = 0; 202 267 203 268 STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioRead)); 204 269 205 VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicRe adRegister(pDevIns, pVCpu, offReg, &uValue));270 VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicReDistRegisterRead(pDevIns, pVCpu, offReg, &uValue)); 206 271 *(uint32_t *)pv = uValue; 207 272 208 Log2(("GIC%u: gicRe adMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));273 Log2(("GIC%u: gicReDistMmioRead: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue)); 209 274 return rc; 210 275 } … … 221 286 222 287 PVMCPUCC pVCpu = PDMDevHlpGetVMCPU(pDevIns); 223 uint16_t offReg = off & 0xff 0;288 uint16_t offReg = off & 0xfffc; 224 289 uint32_t uValue = *(uint32_t *)pv; 225 290 226 291 STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioWrite)); 227 292 228 Log2(("GIC%u: gic WriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));229 return gic WriteRegister(pDevIns, pVCpu, offReg, uValue);293 Log2(("GIC%u: gicReDistMmioWrite: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue)); 294 return gicReDistRegisterWrite(pDevIns, pVCpu, offReg, uValue); 230 295 } 231 296
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