VirtualBox

Changeset 99556 in vbox


Ignore:
Timestamp:
Apr 28, 2023 12:26:58 PM (17 months ago)
Author:
vboxsync
Message:

include/iprt/x86.h: Add definitions for Intels CET

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/iprt/x86.h

    r98103 r99556  
    644644/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
    645645#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE             RT_BIT_32(4)
     646/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
     647#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS            RT_BIT_32(7)
    646648/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
    647649#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU             UINT32_C(0x003e0000)
     
    653655/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
    654656#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR          RT_BIT_32(10)
     657/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
     658#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT           RT_BIT_32(20)
    655659/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
    656660 *  IBPB command in IA32_PRED_CMD. */
     
    17601764/** Core Performance Limit Reasons. */
    17611765#define MSR_CORE_PERF_LIMIT_REASONS         0x64f
     1766
     1767/** Userspace Control flow Enforcement Technology setting. */
     1768#define MSR_IA32_U_CET                      0x6a0
     1769/** Supervisor space Control flow Enforcement Technology setting. */
     1770#define MSR_IA32_S_CET                      0x6a2
     1771/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
     1772 * @{ */
     1773/** Enables the Shadow stack. */
     1774# define MSR_IA32_CET_SH_STK_EN             RT_BIT_64(0)
     1775/** Enables WRSS{D,Q}W instructions. */
     1776# define MSR_IA32_CET_WR_SHSTK_EN           RT_BIT_64(1)
     1777/** Enables indirect branch tracking. */
     1778# define MSR_IA32_CET_ENDBR_EN              RT_BIT_64(2)
     1779/** Enable legacy compatibility treatment for indirect branch tracking. */
     1780# define MSR_IA32_CET_LEG_IW_EN             RT_BIT_64(3)
     1781/** Enables the use of no-track prefix for indirect branch tracking. */
     1782# define MSR_IA32_CET_NO_TRACK_EN           RT_BIT_64(4)
     1783/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
     1784# define MSR_IA32_CET_SUPPRESS_DIS          RT_BIT_64(5)
     1785/** Suppresses indirect branch tracking. */
     1786# define MSR_IA32_CET_SUPPRESS              RT_BIT_64(10)
     1787/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
     1788# define MSR_IA32_CET_TRACKER               RT_BIT_64(11)
     1789/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
     1790 * on a ENDBRANCH instruction. */
     1791# define MSR_IA32_CET_EB_LEG_BITMAP_BASE    UINT64_C(0xfffffffffffff000)
     1792/** @} */
    17621793
    17631794/** X2APIC MSR range start. */
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette