VirtualBox

Changeset 9888 in vbox


Ignore:
Timestamp:
Jun 23, 2008 3:46:11 PM (16 years ago)
Author:
vboxsync
Message:

Updates for amd64 paging.

Location:
trunk/src/VBox/VMM
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/PGMInternal.h

    r9881 r9888  
    12911291/** Page Map Level-4 (64-bit root). */
    12921292#define PGMPOOL_IDX_PML4        8
     1293/** AMD64 cr3 level. */
     1294#define PGMPOOL_IDX_AMD64_CR3   9
    12931295/** The first normal index. */
    1294 #define PGMPOOL_IDX_FIRST       9
     1296#define PGMPOOL_IDX_FIRST       10
    12951297/** The last valid index. (inclusive, 14 bits) */
    12961298#define PGMPOOL_IDX_LAST        0x3fff
     
    20002002    /** The Physical Address (HC) of the Page Map Level 4 table. */
    20012003    RTHCPHYS                    HCPhysPaePML4;
     2004    /** The pgm pool page descriptor for the current active CR3. */
     2005    R3R0PTRTYPE(PPGMPOOLPAGE)   pShwAmd64CR3;
     2006
    20022007    /** @}*/
    20032008
  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r9824 r9888  
    825825
    826826    Assert(!HWACCMIsNestedPagingActive(pVM));
     827    Assert(pVM->pgm.s.pShwAmd64CR3);
    827828
    828829    /* Allocate page directory pointer table if not present. */
     
    834835
    835836        Assert(!(pPml4e->u & X86_PML4E_PG_MASK));
    836         rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, PGMPOOL_IDX_PML4, iPml4e, &pShwPage);
     837        rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e, &pShwPage);
    837838        if (rc == VERR_PGM_POOL_FLUSHED)
    838839            return VINF_PGM_SYNC_CR3;
  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r9874 r9888  
    9393#  define GST_PDPT_MASK             X86_PDPT_MASK_PAE
    9494#  define GST_PTE_PG_MASK           X86_PTE_PAE_PG_MASK
     95#  define GST_CR3_PAGE_MASK         X86_CR3_PAE_PAGE_MASK
    9596# else
    9697#  define GST_TOTAL_PD_ENTRIES      (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
     
    100101#  define GST_PDPT_MASK             X86_PDPT_MASK_AMD64
    101102#  define GST_PTE_PG_MASK           X86_PTE_PAE_PG_MASK_FULL
     103#  define GST_CR3_PAGE_MASK         X86_CR3_AMD64_PAGE_MASK
    102104# endif
    103105# define GST_PT_SHIFT               X86_PT_PAE_SHIFT
    104106# define GST_PT_MASK                X86_PT_PAE_MASK
    105 # define GST_CR3_PAGE_MASK          X86_CR3_PAE_PAGE_MASK
    106107#endif
    107108
     
    466467            }
    467468# elif PGM_GST_TYPE == PGM_TYPE_AMD64
     469            PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
     470
    468471            pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
     472
     473            if (pVM->pgm.s.pShwAmd64CR3)
     474                pgmPoolFreeByPage(pPool, pVM->pgm.s.pShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pShwAmd64CR3->GCPhys >> PAGE_SHIFT);
     475
     476            Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
     477            rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pShwAmd64CR3);
     478            if (rc == VERR_PGM_POOL_FLUSHED)
     479            {
     480                AssertFailed(); /* check if we handle this properly!! */
     481                return VINF_PGM_SYNC_CR3;
     482            }
    469483# endif
    470484        }
     
    510524#elif PGM_GST_TYPE == PGM_TYPE_AMD64
    511525    pVM->pgm.s.pGstPaePML4HC = 0;
     526    if (pVM->pgm.s.pShwAmd64CR3)
     527    {
     528        PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
     529        pgmPoolFreeByPage(pPool, pVM->pgm.s.pShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pShwAmd64CR3->GCPhys >> PAGE_SHIFT);
     530    }
     531
    512532#else /* prot/real mode stub */
    513533    /* nothing to do */
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