Changeset 9817 in vbox
- Timestamp:
- Jun 19, 2008 11:47:38 AM (16 years ago)
- Location:
- trunk
- Files:
-
- 10 edited
-
include/VBox/cpum.h (modified) (3 diffs)
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include/VBox/cpum.mac (modified) (2 diffs)
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src/VBox/VMM/CPUM.cpp (modified) (2 diffs)
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src/VBox/VMM/CPUMInternal.mac (modified) (4 diffs)
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src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/EMAll.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMAll/SELMAll.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMR0/HWACCMR0A.asm (modified) (1 diff)
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src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (1 diff)
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src/recompiler/VBoxRecompiler.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/cpum.h
r9806 r9817 328 328 uint64_t msrCSTAR; /* compatibility mode syscall rip */ 329 329 uint64_t msrSFMASK; /* syscall flag mask */ 330 uint64_t msrFSBASE;331 uint64_t msrGSBASE;332 330 uint64_t msrKERNELGSBASE;/* swapgs exchange value */ 333 331 /** @} */ … … 340 338 341 339 /* padding to get 32byte aligned size */ 342 uint32_t padding[ 2];340 uint32_t padding[6]; 343 341 } CPUMCTX; 344 342 #pragma pack() … … 445 443 CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM); 446 444 CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM); 447 CPUMDECL(uint64_t) CPUMGetGuestFSBASE(PVM pVM);448 CPUMDECL(uint64_t) CPUMGetGuestGSBASE(PVM pVM);449 445 /** @} */ 450 446 -
trunk/include/VBox/cpum.mac
r9430 r9817 193 193 .msrCSTAR resb 8 194 194 .msrSFMASK resb 8 195 .msrFSBASE resb 8196 .msrGSBASE resb 8197 195 .msrKERNELGSBASE resb 8 198 196 … … 206 204 207 205 ; padding 208 .padding resd 2206 .padding resd 6 209 207 endstruc 210 208 -
trunk/src/VBox/VMM/CPUM.cpp
r9795 r9817 944 944 "%sLSTAR =%016RX64\n" 945 945 "%sSFMASK =%016RX64\n" 946 "%sFSBASE =%016RX64\n"947 "%sGSBASE =%016RX64\n"948 946 "%sKERNELGSBASE =%016RX64\n", 949 947 pszPrefix, pCtx->msrEFER, … … 953 951 pszPrefix, pCtx->msrLSTAR, 954 952 pszPrefix, pCtx->msrSFMASK, 955 pszPrefix, pCtx->msrFSBASE,956 pszPrefix, pCtx->msrGSBASE,957 953 pszPrefix, pCtx->msrKERNELGSBASE); 958 954 -
trunk/src/VBox/VMM/CPUMInternal.mac
r9430 r9817 264 264 .Hyper.msrCSTAR resb 8 265 265 .Hyper.msrSFMASK resb 8 266 .Hyper.msrFSBASE resb 8267 .Hyper.msrGSBASE resb 8268 266 .Hyper.msrKERNELGSBASE resb 8 269 267 … … 277 275 278 276 ; padding 279 .Hyper.padding resd 2277 .Hyper.padding resd 6 280 278 281 279 … … 378 376 .Guest.msrCSTAR resb 8 379 377 .Guest.msrSFMASK resb 8 380 .Guest.msrFSBASE resb 8381 .Guest.msrGSBASE resb 8382 378 .Guest.msrKERNELGSBASE resb 8 383 379 … … 391 387 392 388 ; padding 393 .Guest.padding resd 2389 .Guest.padding resd 6 394 390 395 391 -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r9675 r9817 889 889 } 890 890 891 CPUMDECL(uint64_t) CPUMGetGuestFSBASE(PVM pVM)892 {893 return pVM->cpum.s.Guest.msrFSBASE;894 }895 896 CPUMDECL(uint64_t) CPUMGetGuestGSBASE(PVM pVM)897 {898 return pVM->cpum.s.Guest.msrGSBASE;899 }900 901 891 /** 902 892 * Gets a CpuId leaf. -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r9750 r9817 2244 2244 2245 2245 case MSR_K8_FS_BASE: 2246 val = pCtx-> msrFSBASE;2246 val = pCtx->fsHid.u64Base; 2247 2247 break; 2248 2248 2249 2249 case MSR_K8_GS_BASE: 2250 val = pCtx-> msrGSBASE;2250 val = pCtx->gsHid.u64Base; 2251 2251 break; 2252 2252 … … 2373 2373 2374 2374 case MSR_K8_FS_BASE: 2375 pCtx-> msrFSBASE= val;2375 pCtx->fsHid.u64Base = val; 2376 2376 break; 2377 2377 2378 2378 case MSR_K8_GS_BASE: 2379 pCtx-> msrGSBASE= val;2379 pCtx->gsHid.u64Base = val; 2380 2380 break; 2381 2381 -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r9710 r9817 120 120 { 121 121 case DIS_SELREG_FS: 122 return (RTGCPTR)(CPUMGetGuestFSBASE(pVM) + Addr);123 124 122 case DIS_SELREG_GS: 125 return (RTGCPTR)( CPUMGetGuestGSBASE(pVM)+ Addr);123 return (RTGCPTR)(pHiddenSel->u64Base + Addr); 126 124 127 125 default: … … 200 198 { 201 199 case DIS_SELREG_FS: 202 pvFlat = (CPUMGetGuestFSBASE(pVM) + Addr);203 break;204 205 200 case DIS_SELREG_GS: 206 pvFlat = ( CPUMGetGuestGSBASE(pVM)+ Addr);201 pvFlat = (pHiddenSel->u64Base + Addr); 207 202 break; 208 203 -
trunk/src/VBox/VMM/VMMR0/HWACCMR0A.asm
r9815 r9817 457 457 LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE 458 458 459 ; Load the guest MSRs for FS & GS base (saved in MYPUSHSEGS)460 mov rcx, MSR_K8_FS_BASE461 mov rax, qword [xSI + CPUMCTX.msrFSBASE]462 wrmsr463 464 mov rcx, MSR_K8_GS_BASE465 mov rax, qword [xSI + CPUMCTX.msrGSBASE]466 wrmsr467 468 459 ; Save the pCtx pointer 469 460 push xSI -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r9814 r9817 969 969 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64; 970 970 #endif 971 /* Unconditionally update these as wrmsr might have changed them. */ 972 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base); 973 AssertRC(rc); 974 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base); 975 AssertRC(rc); 971 976 } 972 977 else -
trunk/src/recompiler/VBoxRecompiler.c
r9802 r9817 1825 1825 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF); 1826 1826 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF); 1827 1828 /* FS & GS base addresses need to be loaded from the MSRs if in 64 bits mode. */ 1829 if (CPUMIsGuestIn64BitCodeEx(pCtx)) 1830 { 1831 /* Note that the base values in the hidden fs & gs registers are cut to 32 bits and can't be used in this case. */ 1832 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->msrFSBASE, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF); 1833 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->msrGSBASE, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF); 1834 } 1835 else 1836 { 1837 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF); 1838 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF); 1839 } 1827 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF); 1828 cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF); 1840 1829 } 1841 1830 else … … 2222 2211 pCtx->msrCSTAR = pVM->rem.s.Env.cstar; 2223 2212 pCtx->msrSFMASK = pVM->rem.s.Env.fmask; 2224 pCtx->msrFSBASE = pVM->rem.s.Env.segs[R_FS].base;2225 pCtx->msrGSBASE = pVM->rem.s.Env.segs[R_GS].base;2226 2213 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase; 2227 2214 #endif … … 2424 2411 pCtx->msrCSTAR = pVM->rem.s.Env.cstar; 2425 2412 pCtx->msrSFMASK = pVM->rem.s.Env.fmask; 2426 pCtx->msrFSBASE = pVM->rem.s.Env.segs[R_FS].base;2427 pCtx->msrGSBASE = pVM->rem.s.Env.segs[R_GS].base;2428 2413 pCtx->msrKERNELGSBASE = pVM->rem.s.Env.kernelgsbase; 2429 2414 #endif
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