Changeset 97370 in vbox
- Timestamp:
- Nov 2, 2022 12:53:30 AM (2 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 8 edited
-
VMMAll/IEMAll.cpp (modified) (1 diff)
-
VMMAll/IEMAllCImpl.cpp (modified) (86 diffs)
-
VMMAll/IEMAllCImplStrInstr.cpp.h (modified) (25 diffs)
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VMMAll/IEMAllCImplSvmInstr.cpp (modified) (7 diffs)
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VMMAll/IEMAllCImplVmxInstr.cpp (modified) (46 diffs)
-
VMMAll/IEMAllInstructionsOneByte.cpp.h (modified) (1 diff)
-
include/IEMInline.h (modified) (2 diffs)
-
include/IEMMc.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r97346 r97370 4169 4169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE) 4170 4170 return iemRaiseXcptOrInt(pVCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); 4171 else 4172 { 4173 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */ 4174 PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq */, 1 /* u8Level */, 0 /* uTagSrc */); 4175 iemRegUpdateRipAndClearRF(pVCpu); 4176 return VINF_SUCCESS; 4177 } 4171 4172 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */ 4173 PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq */, 1 /* u8Level */, 0 /* uTagSrc */); 4174 return iemRegUpdateRipAndFinishClearingRF(pVCpu); 4178 4175 } 4179 4176 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
r97297 r97370 332 332 { 333 333 pVCpu->cpum.GstCtx.rsp = TmpRsp.u; 334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);334 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 335 335 } 336 336 } … … 353 353 { 354 354 iemRegAddToRsp(pVCpu, 16); 355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);355 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 356 356 } 357 357 } … … 412 412 #endif 413 413 pVCpu->cpum.GstCtx.rsp = TmpRsp.u; 414 iemRegAddToRipAndClearRF(pVCpu, cbInstr);414 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 415 415 } 416 416 } … … 433 433 { 434 434 iemRegAddToRsp(pVCpu, 32); 435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);435 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 436 436 } 437 437 } … … 482 482 { 483 483 pVCpu->cpum.GstCtx.rsp = TmpRsp.u; 484 iemRegAddToRipAndClearRF(pVCpu, cbInstr);484 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 485 485 } 486 486 } … … 504 504 { 505 505 iemRegSubFromRsp(pVCpu, 16); 506 iemRegAddToRipAndClearRF(pVCpu, cbInstr);506 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 507 507 } 508 508 } … … 553 553 { 554 554 pVCpu->cpum.GstCtx.rsp = TmpRsp.u; 555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);555 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 556 556 } 557 557 } … … 575 575 { 576 576 iemRegSubFromRsp(pVCpu, 32); 577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);577 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 578 578 } 579 579 } … … 641 641 } 642 642 } 643 if (rcStrict != VINF_SUCCESS) 644 return rcStrict; 645 646 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 647 return VINF_SUCCESS; 643 644 if (rcStrict == VINF_SUCCESS) 645 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 646 return rcStrict; 648 647 } 649 648 … … 807 806 Assert(fEflNew & RT_BIT_32(1)); 808 807 IEMMISC_SET_EFL(pVCpu, fEflNew); 809 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 810 811 return VINF_SUCCESS; 808 return iemRegAddToRipAndFinishingClearingRfEx(pVCpu, cbInstr, fEflOld); 812 809 } 813 810 … … 2817 2814 pVCpu->cpum.GstCtx.rbp = NewRbp.u; 2818 2815 pVCpu->cpum.GstCtx.rsp = NewRsp.u; 2819 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 2820 2821 return VINF_SUCCESS; 2816 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 2822 2817 } 2823 2818 … … 2872 2867 pVCpu->cpum.GstCtx.rbp = NewRbp.u; 2873 2868 pVCpu->cpum.GstCtx.rsp = NewRsp.u; 2874 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 2875 2876 return VINF_SUCCESS; 2869 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 2877 2870 } 2878 2871 … … 4547 4540 #endif 4548 4541 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS); 4549 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 4550 return VINF_SUCCESS; 4542 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 4551 4543 } 4552 4544 … … 4584 4576 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS); 4585 4577 4586 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 4587 return VINF_SUCCESS; 4578 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 4588 4579 } 4589 4580 … … 4690 4681 4691 4682 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS); 4692 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 4693 return VINF_SUCCESS; 4683 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 4694 4684 } 4695 4685 … … 4912 4902 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible; 4913 4903 4914 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 4915 return VINF_SUCCESS; 4904 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 4916 4905 } 4917 4906 … … 5017 5006 /* commit flags value and advance rip. */ 5018 5007 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk; 5019 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5020 5021 return VINF_SUCCESS; 5008 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5022 5009 } 5023 5010 … … 5080 5067 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit); 5081 5068 if (rcStrict == VINF_SUCCESS) 5082 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5069 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5083 5070 } 5084 5071 else … … 5122 5109 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst); 5123 5110 if (rcStrict == VINF_SUCCESS) 5124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5111 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5125 5112 return rcStrict; 5126 5113 } … … 5159 5146 { 5160 5147 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit); 5161 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5148 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5162 5149 } 5163 5150 else … … 5194 5181 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst); 5195 5182 if (rcStrict == VINF_SUCCESS) 5196 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5183 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5197 5184 return rcStrict; 5198 5185 } … … 5263 5250 } 5264 5251 5265 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5266 return VINF_SUCCESS; 5252 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5267 5253 } 5268 5254 … … 5332 5318 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base; 5333 5319 5334 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5335 return VINF_SUCCESS; 5320 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5336 5321 } 5337 5322 … … 5362 5347 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5363 5348 } 5364 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5365 return VINF_SUCCESS; 5349 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5366 5350 } 5367 5351 … … 5380 5364 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel); 5381 5365 if (rcStrict == VINF_SUCCESS) 5382 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5366 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5383 5367 return rcStrict; 5384 5368 } … … 5510 5494 pVCpu->cpum.GstCtx.tr.u64Base = u64Base; 5511 5495 5512 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5513 return VINF_SUCCESS; 5496 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5514 5497 } 5515 5498 … … 5540 5523 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 5541 5524 } 5542 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5543 return VINF_SUCCESS; 5525 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5544 5526 } 5545 5527 … … 5565 5547 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel); 5566 5548 if (rcStrict == VINF_SUCCESS) 5567 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5549 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5568 5550 return rcStrict; 5569 5551 } … … 5684 5666 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX; 5685 5667 5686 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5687 return VINF_SUCCESS; 5668 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5688 5669 } 5689 5670 … … 5732 5713 } 5733 5714 5734 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 5735 return VINF_SUCCESS; 5715 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5736 5716 } 5737 5717 … … 5768 5748 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value); 5769 5749 if (rcStrict == VINF_SUCCESS) 5770 iemRegAddToRipAndClearRF(pVCpu, cbInstr);5750 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 5771 5751 return rcStrict; 5772 5752 } … … 6240 6220 { 6241 6221 if (rcStrict != VINF_SUCCESS) 6242 rcStrict =iemSetPassUpStatus(pVCpu, rcStrict);6243 iemRegAddToRipAndClearRF(pVCpu, cbInstr);6222 iemSetPassUpStatus(pVCpu, rcStrict); 6223 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6244 6224 } 6245 6225 … … 6455 6435 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX; 6456 6436 6457 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6458 return VINF_SUCCESS; 6437 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6459 6438 } 6460 6439 … … 6578 6557 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc); 6579 6558 6580 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6581 return VINF_SUCCESS; 6559 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6582 6560 } 6583 6561 … … 6629 6607 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX; 6630 6608 6631 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6632 return VINF_SUCCESS; 6609 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6633 6610 } 6634 6611 … … 6675 6652 RT_NOREF(uNewTrX); 6676 6653 6677 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6678 return VINF_SUCCESS; 6654 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6679 6655 } 6680 6656 … … 6712 6688 6713 6689 int rc = PGMInvalidatePage(pVCpu, GCPtrPage); 6714 iemRegAddToRipAndClearRF(pVCpu, cbInstr);6715 6716 6690 if (rc == VINF_SUCCESS) 6717 return VINF_SUCCESS;6691 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6718 6692 if (rc == VINF_PGM_SYNC_CR3) 6719 return iemSetPassUpStatus(pVCpu, rc); 6720 6721 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc)); 6693 { 6694 iemSetPassUpStatus(pVCpu, rc); 6695 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6696 } 6697 6698 AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc)); 6722 6699 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc)); 6723 6700 return rc; … … 6851 6828 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 6852 6829 } 6853 iemRegAddToRipAndClearRF(pVCpu, cbInstr);6830 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6854 6831 } 6855 6832 return rcStrict; … … 6874 6851 6875 6852 /* We currently take no action here. */ 6876 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6877 return VINF_SUCCESS; 6853 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6878 6854 } 6879 6855 … … 6896 6872 6897 6873 /* We currently take no action here. */ 6898 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6899 return VINF_SUCCESS; 6874 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6900 6875 } 6901 6876 … … 6955 6930 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks); 6956 6931 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */ 6957 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 6958 return VINF_SUCCESS; 6932 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 6959 6933 } 6960 6934 … … 7019 6993 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks); 7020 6994 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */ 7021 iemRegAddToRipAndClearRF(pVCpu, cbInstr);6995 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7022 6996 } 7023 6997 return rcStrict; … … 7057 7031 * ecx but see @bugref{3472}! */ 7058 7032 7059 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7060 return VINF_SUCCESS; 7033 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7061 7034 } 7062 7035 … … 7114 7087 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); 7115 7088 7116 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7117 return VINF_SUCCESS; 7089 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7118 7090 } 7119 7091 … … 7192 7164 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, idMsr, uValue.u); 7193 7165 if (rcStrict == VINF_SUCCESS) 7194 { 7195 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7196 return VINF_SUCCESS; 7197 } 7166 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7198 7167 7199 7168 #ifndef IN_RING3 … … 7280 7249 * Perform the I/O. 7281 7250 */ 7282 uint32_t u32Value = 0; 7283 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg); 7251 PVMCC const pVM = pVCpu->CTX_SUFF(pVM); 7252 uint32_t u32Value = 0; 7253 rcStrict = IOMIOPortRead(pVM, pVCpu, u16Port, &u32Value, cbReg); 7284 7254 if (IOM_SUCCESS(rcStrict)) 7285 7255 { … … 7291 7261 default: AssertFailedReturn(VERR_IEM_IPE_3); 7292 7262 } 7293 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7263 7294 7264 pVCpu->iem.s.cPotentialExits++; 7295 7265 if (rcStrict != VINF_SUCCESS) 7296 rcStrict =iemSetPassUpStatus(pVCpu, rcStrict);7297 Assert(rcStrict == VINF_SUCCESS); /* assumed below */7266 iemSetPassUpStatus(pVCpu, rcStrict); 7267 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7298 7268 7299 7269 /* 7300 7270 * Check for I/O breakpoints. 7301 7271 */ 7272 /** @todo this should set a internal flag and be raised by 7273 * iemRegAddToRipAndFinishingClearingRF! */ 7302 7274 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7]; 7303 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK) 7304 && X86_DR7_ANY_RW_IO(uDr7) 7305 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)) 7306 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM)))) 7275 if (RT_UNLIKELY( ( ( (uDr7 & X86_DR7_ENABLED_MASK) 7276 && X86_DR7_ANY_RW_IO(uDr7) 7277 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)) 7278 || DBGFBpIsHwIoArmed(pVM)) 7279 && rcStrict == VINF_SUCCESS)) 7307 7280 { 7308 7281 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6); 7309 rcStrict = DBGFBpCheckIo(pV Cpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);7282 rcStrict = DBGFBpCheckIo(pVM, pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg); 7310 7283 if (rcStrict == VINF_EM_RAW_GUEST_TRAP) 7311 7284 rcStrict = iemRaiseDebugException(pVCpu); … … 7389 7362 * Perform the I/O. 7390 7363 */ 7364 PVMCC const pVM = pVCpu->CTX_SUFF(pVM); 7391 7365 uint32_t u32Value; 7392 7366 switch (cbReg) … … 7397 7371 default: AssertFailedReturn(VERR_IEM_IPE_4); 7398 7372 } 7399 rcStrict = IOMIOPortWrite(pV Cpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);7373 rcStrict = IOMIOPortWrite(pVM, pVCpu, u16Port, u32Value, cbReg); 7400 7374 if (IOM_SUCCESS(rcStrict)) 7401 7375 { 7402 iemRegAddToRipAndClearRF(pVCpu, cbInstr);7403 7376 pVCpu->iem.s.cPotentialExits++; 7404 7377 if (rcStrict != VINF_SUCCESS) 7405 rcStrict =iemSetPassUpStatus(pVCpu, rcStrict);7406 Assert(rcStrict == VINF_SUCCESS); /* assumed below */7378 iemSetPassUpStatus(pVCpu, rcStrict); 7379 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7407 7380 7408 7381 /* 7409 7382 * Check for I/O breakpoints. 7410 7383 */ 7384 /** @todo this should set a internal flag and be raised by 7385 * iemRegAddToRipAndFinishingClearingRF! */ 7411 7386 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7]; 7412 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK) 7413 && X86_DR7_ANY_RW_IO(uDr7) 7414 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)) 7415 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM)))) 7387 if (RT_UNLIKELY( ( ( (uDr7 & X86_DR7_ENABLED_MASK) 7388 && X86_DR7_ANY_RW_IO(uDr7) 7389 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)) 7390 || DBGFBpIsHwIoArmed(pVM)) 7391 && rcStrict == VINF_SUCCESS)) 7416 7392 { 7417 7393 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6); 7418 rcStrict = DBGFBpCheckIo(pV Cpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);7394 rcStrict = DBGFBpCheckIo(pVM, pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg); 7419 7395 if (rcStrict == VINF_EM_RAW_GUEST_TRAP) 7420 7396 rcStrict = iemRaiseDebugException(pVCpu); … … 7442 7418 { 7443 7419 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu); 7420 #ifdef LOG_ENABLED 7444 7421 uint32_t const fEflOld = fEfl; 7422 #endif 7445 7423 7446 7424 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4); … … 7473 7451 /* Commit. */ 7474 7452 IEMMISC_SET_EFL(pVCpu, fEfl); 7475 iemRegAddToRipAndClearRF(pVCpu, cbInstr);7476 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);7477 return VINF_SUCCESS;7453 VBOXSTRICTRC const rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7454 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); 7455 return rcStrict; 7478 7456 } 7479 7457 … … 7522 7500 */ 7523 7501 IEMMISC_SET_EFL(pVCpu, fEfl); 7524 iemRegAddToRipAndClearRF(pVCpu, cbInstr);7502 VBOXSTRICTRC const rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7525 7503 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF)) 7526 7504 { … … 7529 7507 } 7530 7508 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl)); 7531 return VINF_SUCCESS;7509 return rcStrict; 7532 7510 } 7533 7511 … … 7555 7533 } 7556 7534 7557 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7558 return VINF_EM_HALT; 7535 /** @todo finish: This ASSUMES that iemRegAddToRipAndFinishingClearingRF won't 7536 * be returning any status codes relating to non-guest events being raised, as 7537 * we'll mess up the guest HALT otherwise. */ 7538 VBOXSTRICTRC rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7539 if (rcStrict == VINF_SUCCESS) 7540 rcStrict = VINF_EM_HALT; 7541 return rcStrict; 7559 7542 } 7560 7543 … … 7644 7627 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem); 7645 7628 Assert(rcStrict == VINF_SUCCESS); 7646 7647 iemRegAddToRipAndClearRF(pVCpu, cbInstr);7629 if (rcStrict == VINF_SUCCESS) 7630 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7648 7631 return rcStrict; 7649 7632 } … … 7712 7695 if ( IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INT_WINDOW_EXIT) 7713 7696 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)) 7714 { 7715 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7716 return VINF_SUCCESS; 7717 } 7697 /** @todo finish: check up this out after we move int window stuff out of the 7698 * run loop and into the instruction finishing logic here. */ 7699 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7718 7700 } 7719 7701 #endif … … 7739 7721 /* 7740 7722 * Call EM to prepare the monitor/wait. 7723 * 7724 * This will return VINF_EM_HALT. If there the trap flag is set, we may 7725 * override it when executing iemRegAddToRipAndFinishingClearingRF ASSUMING 7726 * that will only return guest related events. 7741 7727 */ 7742 7728 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx); 7743 7729 7744 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7730 /** @todo finish: This needs more thinking as we should suppress internal 7731 * debugger events here, or we'll bugger up the guest state even more than we 7732 * alread do around VINF_EM_HALT. */ 7733 VBOXSTRICTRC rcStrict2 = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7734 if (rcStrict2 != VINF_SUCCESS) 7735 { 7736 Log2(("mwait: %Rrc (perform) -> %Rrc (finish)!\n", VBOXSTRICTRC_VAL(rcStrict), VBOXSTRICTRC_VAL(rcStrict2) )); 7737 rcStrict = rcStrict2; 7738 } 7739 7745 7740 return rcStrict; 7746 7741 } … … 7771 7766 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase; 7772 7767 7773 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7774 return VINF_SUCCESS; 7768 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7775 7769 } 7776 7770 … … 7917 7911 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX); 7918 7912 7919 iemRegAddToRipAndClearRF(pVCpu, cbInstr);7920 7913 pVCpu->iem.s.cPotentialExits++; 7921 return VINF_SUCCESS;7914 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7922 7915 } 7923 7916 … … 7937 7930 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF); 7938 7931 7939 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7940 return VINF_SUCCESS; 7932 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7941 7933 } 7942 7934 … … 7959 7951 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF); 7960 7952 7961 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7962 return VINF_SUCCESS; 7953 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7963 7954 } 7964 7955 … … 7990 7981 7991 7982 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF); 7992 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7993 return VINF_SUCCESS; 7983 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7994 7984 } 7995 7985 … … 8024 8014 8025 8015 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF); 8026 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8027 return VINF_SUCCESS; 8016 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8028 8017 } 8029 8018 … … 8069 8058 } 8070 8059 8071 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8072 return VINF_SUCCESS; 8060 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8073 8061 } 8074 8062 … … 8114 8102 } 8115 8103 8116 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8117 return VINF_SUCCESS; 8104 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8118 8105 } 8119 8106 … … 8133 8120 if ( idxArray >= idxLowerBound 8134 8121 && idxArray <= idxUpperBound) 8135 { 8136 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8137 return VINF_SUCCESS; 8138 } 8139 8122 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8140 8123 return iemRaiseBoundRangeExceeded(pVCpu); 8141 8124 } … … 8152 8135 if ( idxArray >= idxLowerBound 8153 8136 && idxArray <= idxUpperBound) 8154 { 8155 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8156 return VINF_SUCCESS; 8157 } 8158 8137 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8159 8138 return iemRaiseBoundRangeExceeded(pVCpu); 8160 8139 } … … 8227 8206 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]); 8228 8207 8229 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8230 return VINF_SUCCESS; 8208 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8231 8209 } 8232 8210 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n")); … … 8277 8255 } 8278 8256 8279 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8280 return VINF_SUCCESS; 8257 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8281 8258 } 8282 8259 … … 8352 8329 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi; 8353 8330 } 8354 iemRegAddToRipAndClearRF(pVCpu, cbInstr);8331 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8355 8332 } 8356 8333 } … … 8401 8378 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE 8402 8379 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR) 8403 return rcStrict;8380 return rcStrict; 8404 8381 } 8405 8382 #endif 8406 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8407 return VINF_SUCCESS; 8383 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8408 8384 } 8409 8385 } … … 8461 8437 8462 8438 iemHlpUsedFpu(pVCpu); 8463 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8464 return VINF_SUCCESS; 8439 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8465 8440 } 8466 8441 … … 8553 8528 return rcStrict; 8554 8529 8555 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8556 return VINF_SUCCESS; 8530 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8557 8531 } 8558 8532 … … 8660 8634 8661 8635 iemHlpUsedFpu(pVCpu); 8662 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8663 return VINF_SUCCESS; 8636 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8664 8637 } 8665 8638 … … 8812 8785 return rcStrict; 8813 8786 8814 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8815 return VINF_SUCCESS; 8787 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8816 8788 } 8817 8789 … … 9029 9001 } 9030 9002 9031 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9032 return VINF_SUCCESS; 9003 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9033 9004 } 9034 9005 … … 9059 9030 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR); 9060 9031 if (rcStrict == VINF_SUCCESS) 9061 { 9062 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9063 return VINF_SUCCESS; 9064 } 9032 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9065 9033 return rcStrict; 9066 9034 } … … 9096 9064 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR); 9097 9065 if (rcStrict == VINF_SUCCESS) 9098 { 9099 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9100 return VINF_SUCCESS; 9101 } 9066 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9102 9067 return rcStrict; 9103 9068 } … … 9139 9104 { 9140 9105 pVCpu->cpum.GstCtx.XState.x87.MXCSR = fNewMxCsr; 9141 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9142 return VINF_SUCCESS; 9106 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9143 9107 } 9144 9108 Log(("ldmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n", … … 9340 9304 9341 9305 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */ 9342 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9343 return VINF_SUCCESS; 9306 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9344 9307 } 9345 9308 … … 9394 9357 9395 9358 iemHlpUsedFpu(pVCpu); 9396 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9397 return VINF_SUCCESS; 9359 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9398 9360 } 9399 9361 … … 9423 9385 9424 9386 iemHlpUsedFpu(pVCpu); 9425 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9426 return VINF_SUCCESS; 9387 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9427 9388 } 9428 9389 … … 9459 9420 9460 9421 iemHlpUsedFpu(pVCpu); 9461 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9462 return VINF_SUCCESS; 9422 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9463 9423 } 9464 9424 … … 9492 9452 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */ 9493 9453 iemHlpUsedFpu(pVCpu); 9494 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9495 return VINF_SUCCESS; 9454 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9496 9455 } 9497 9456 … … 9544 9503 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx); 9545 9504 iemHlpUsedFpu(pVCpu); 9546 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9547 return VINF_SUCCESS; 9505 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9548 9506 } 9549 9507 … … 9619 9577 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx); 9620 9578 iemHlpUsedFpu(pVCpu); 9621 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9622 return VINF_SUCCESS; 9579 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9623 9580 } 9624 9581 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h
r96407 r97370 148 148 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 149 149 if (uCounterReg == 0) 150 { 151 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 152 return VINF_SUCCESS; 153 } 150 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 154 151 155 152 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iEffSeg) | CPUMCTX_EXTRN_ES); … … 301 298 * Done. 302 299 */ 303 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 304 return VINF_SUCCESS; 300 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 305 301 } 306 302 … … 318 314 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 319 315 if (uCounterReg == 0) 320 { 321 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 322 return VINF_SUCCESS; 323 } 316 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 324 317 325 318 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iEffSeg) | CPUMCTX_EXTRN_ES); … … 471 464 * Done. 472 465 */ 473 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 474 return VINF_SUCCESS; 466 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 475 467 } 476 468 … … 488 480 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 489 481 if (uCounterReg == 0) 490 { 491 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 492 return VINF_SUCCESS; 493 } 482 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 494 483 495 484 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ES); … … 603 592 * Done. 604 593 */ 605 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 606 return VINF_SUCCESS; 594 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 607 595 } 608 596 … … 620 608 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 621 609 if (uCounterReg == 0) 622 { 623 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 624 return VINF_SUCCESS; 625 } 610 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 626 611 627 612 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ES); … … 734 719 * Done. 735 720 */ 736 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 737 return VINF_SUCCESS; 721 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 738 722 } 739 723 … … 753 737 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 754 738 if (uCounterReg == 0) 755 { 756 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 757 return VINF_SUCCESS; 758 } 739 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 759 740 760 741 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iEffSeg) | CPUMCTX_EXTRN_ES); … … 896 877 * Done. 897 878 */ 898 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 899 return VINF_SUCCESS; 879 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 900 880 } 901 881 … … 913 893 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 914 894 if (uCounterReg == 0) 915 { 916 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 917 return VINF_SUCCESS; 918 } 895 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 919 896 920 897 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ES); … … 1045 1022 * Done. 1046 1023 */ 1047 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1048 return VINF_SUCCESS; 1024 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1049 1025 } 1050 1026 … … 1062 1038 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 1063 1039 if (uCounterReg == 0) 1064 { 1065 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1066 return VINF_SUCCESS; 1067 } 1040 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1068 1041 1069 1042 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iEffSeg)); … … 1171 1144 * Done. 1172 1145 */ 1173 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1174 return VINF_SUCCESS; 1146 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1175 1147 } 1176 1148 … … 1250 1222 if (IOM_SUCCESS(rcStrict)) 1251 1223 { 1224 /** 1225 * @todo I/O breakpoint support for INS 1226 */ 1252 1227 *puMem = (OP_TYPE)u32Value; 1253 1228 # ifdef IN_RING3 … … 1262 1237 else 1263 1238 pVCpu->cpum.GstCtx.ADDR_rDI -= OP_SIZE / 8; 1264 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1239 1240 /** @todo finish: work out how this should work wrt status codes. Not sure we 1241 * can use iemSetPassUpStatus here, but it depends on what 1242 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1243 rcStrict2 = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1244 if (rcStrict2 != VINF_SUCCESS) 1245 { 1246 iemSetPassUpStatus(pVCpu, rcStrict); 1247 rcStrict = rcStrict2; 1248 } 1249 pVCpu->iem.s.cPotentialExits++; 1265 1250 } 1266 1251 else … … 1328 1313 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 1329 1314 if (uCounterReg == 0) 1330 { 1331 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1332 return VINF_SUCCESS; 1333 } 1315 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1334 1316 1335 1317 uint64_t uBaseAddr = 0; /* gcc may not be used uninitialized */ … … 1399 1381 if (IOM_SUCCESS(rcStrict)) 1400 1382 { 1383 /** @todo finish: work out how this should work wrt status codes. Not sure we 1384 * can use iemSetPassUpStatus here, but it depends on what 1385 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1401 1386 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict); 1402 1387 if (uCounterReg == 0) 1403 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1388 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1389 pVCpu->iem.s.cPotentialExits++; 1404 1390 } 1405 1391 return rcStrict; … … 1463 1449 if (rcStrict != VINF_SUCCESS) 1464 1450 { 1451 /** @todo finish: work out how this should work wrt status codes. Not sure we 1452 * can use iemSetPassUpStatus here, but it depends on what 1453 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1454 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict); 1465 1455 if (uCounterReg == 0) 1466 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1467 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);1456 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1457 pVCpu->iem.s.cPotentialExits++; 1468 1458 return rcStrict; 1469 1459 } … … 1484 1474 * Done. 1485 1475 */ 1486 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1487 return VINF_SUCCESS;1476 pVCpu->iem.s.cPotentialExits++; 1477 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1488 1478 } 1489 1479 … … 1553 1543 else 1554 1544 pVCpu->cpum.GstCtx.ADDR_rSI -= OP_SIZE / 8; 1555 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1545 /** @todo finish: work out how this should work wrt status codes. Not sure we 1546 * can use iemSetPassUpStatus here, but it depends on what 1547 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1556 1548 if (rcStrict != VINF_SUCCESS) 1557 1549 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict); 1550 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1551 pVCpu->iem.s.cPotentialExits++; 1558 1552 } 1559 1553 } … … 1617 1611 ADDR_TYPE uCounterReg = pVCpu->cpum.GstCtx.ADDR_rCX; 1618 1612 if (uCounterReg == 0) 1619 { 1620 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1621 return VINF_SUCCESS; 1622 } 1613 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1623 1614 1624 1615 PCCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iEffSeg); … … 1680 1671 if (IOM_SUCCESS(rcStrict)) 1681 1672 { 1673 /** @todo finish: work out how this should work wrt status codes. Not sure we 1674 * can use iemSetPassUpStatus here, but it depends on what 1675 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1682 1676 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict); 1683 1677 if (uCounterReg == 0) 1684 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1678 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1679 pVCpu->iem.s.cPotentialExits++; 1685 1680 } 1686 1681 return rcStrict; … … 1729 1724 if (IOM_SUCCESS(rcStrict)) 1730 1725 { 1726 /** @todo finish: work out how this should work wrt status codes. Not sure we 1727 * can use iemSetPassUpStatus here, but it depends on what 1728 * iemRegAddToRipAndFinishingClearingRF may eventually return (if anything)... */ 1729 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict); 1731 1730 if (uCounterReg == 0) 1732 iemRegAddToRipAnd ClearRF(pVCpu, cbInstr);1733 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);1731 iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1732 pVCpu->iem.s.cPotentialExits++; 1734 1733 } 1735 1734 return rcStrict; … … 1750 1749 * Done. 1751 1750 */ 1752 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1753 return VINF_SUCCESS;1751 pVCpu->iem.s.cPotentialExits++; 1752 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1754 1753 } 1755 1754 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp
r97286 r97370 1252 1252 pVCpu->cpum.GstCtx.SysEnter.eip = VmcbNstGst.u64SysEnterEIP; 1253 1253 1254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1254 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1255 1255 } 1256 1256 return rcStrict; … … 1332 1332 sizeof(SVMVMCBSTATESAVE)); 1333 1333 if (rcStrict == VINF_SUCCESS) 1334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1334 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1335 1335 } 1336 1336 return rcStrict; … … 1376 1376 1377 1377 CPUMSetGuestGif(&pVCpu->cpum.GstCtx, false); 1378 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1379 1378 1380 1379 # if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3) 1380 iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1381 1381 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); 1382 1382 # else 1383 return VINF_SUCCESS;1383 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1384 1384 # endif 1385 1385 # endif … … 1424 1424 1425 1425 CPUMSetGuestGif(&pVCpu->cpum.GstCtx, true); 1426 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1427 1426 1428 1427 # if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3) 1428 iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1429 1429 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); 1430 1430 # else 1431 return VINF_SUCCESS;1431 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1432 1432 # endif 1433 1433 # endif … … 1474 1474 1475 1475 PGMInvalidatePage(pVCpu, GCPtrPage); 1476 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1477 return VINF_SUCCESS; 1476 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1478 1477 } 1479 1478 … … 1553 1552 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0); 1554 1553 1555 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 1556 return VINF_SUCCESS; 1554 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1557 1555 } 1558 1556 … … 1570 1568 if (RT_SUCCESS(rcStrict)) 1571 1569 { 1570 /** @todo finish: Sort out assertion here when iemRegAddToRipAndFinishingClearingRF 1571 * starts returning non-VINF_SUCCESS statuses. */ 1572 1572 if (rcStrict == VINF_SUCCESS) 1573 iemRegAddToRipAndClearRF(pVCpu, cbInstr);1573 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 1574 1574 if ( rcStrict == VINF_SUCCESS 1575 1575 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING) -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp
r97286 r97370 7734 7734 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid; 7735 7735 iemVmxVmFailInvalid(pVCpu); 7736 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7737 return VINF_SUCCESS; 7736 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7738 7737 } 7739 7738 … … 7746 7745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs; 7747 7746 iemVmxVmFailInvalid(pVCpu); 7748 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7749 return VINF_SUCCESS; 7747 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7750 7748 } 7751 7749 … … 7759 7757 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS; 7760 7758 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS); 7761 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7762 return VINF_SUCCESS; 7759 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7763 7760 } 7764 7761 … … 7773 7770 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear; 7774 7771 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS); 7775 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7776 return VINF_SUCCESS; 7772 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7777 7773 } 7778 7774 } … … 7787 7783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch; 7788 7784 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS); 7789 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7790 return VINF_SUCCESS; 7785 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7791 7786 } 7792 7787 } … … 7933 7928 7934 7929 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE); 7935 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7936 return VINF_SUCCESS; 7930 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7937 7931 } 7938 7932 7939 7933 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS); 7940 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 7941 return VINF_SUCCESS; 7934 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 7942 7935 # endif 7943 7936 } … … 8113 8106 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid; 8114 8107 iemVmxVmFailInvalid(pVCpu); 8115 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8116 return VINF_SUCCESS; 8108 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8117 8109 } 8118 8110 … … 8126 8118 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid; 8127 8119 iemVmxVmFailInvalid(pVCpu); 8128 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8129 return VINF_SUCCESS; 8120 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8130 8121 } 8131 8122 … … 8139 8130 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField; 8140 8131 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT); 8141 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8142 return VINF_SUCCESS; 8132 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8143 8133 } 8144 8134 … … 8173 8163 { 8174 8164 iemVmxVmSucceed(pVCpu); 8175 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8176 return VINF_SUCCESS; 8165 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8177 8166 } 8178 8167 … … 8202 8191 *pu32Dst = u64Dst; 8203 8192 iemVmxVmSucceed(pVCpu); 8204 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8205 return VINF_SUCCESS; 8193 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8206 8194 } 8207 8195 … … 8242 8230 { 8243 8231 iemVmxVmSucceed(pVCpu); 8244 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8245 return VINF_SUCCESS; 8232 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8246 8233 } 8247 8234 … … 8416 8403 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid; 8417 8404 iemVmxVmFailInvalid(pVCpu); 8418 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8419 return VINF_SUCCESS; 8405 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8420 8406 } 8421 8407 … … 8429 8415 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid; 8430 8416 iemVmxVmFailInvalid(pVCpu); 8431 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8432 return VINF_SUCCESS; 8417 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8433 8418 } 8434 8419 … … 8464 8449 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField; 8465 8450 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT); 8466 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8467 return VINF_SUCCESS; 8451 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8468 8452 } 8469 8453 … … 8479 8463 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField; 8480 8464 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT); 8481 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8482 return VINF_SUCCESS; 8465 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8483 8466 } 8484 8467 … … 8501 8484 8502 8485 iemVmxVmSucceed(pVCpu); 8503 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8504 return VINF_SUCCESS; 8486 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8505 8487 } 8506 8488 … … 8602 8584 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8603 8585 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR); 8604 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8605 return VINF_SUCCESS; 8586 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8606 8587 } 8607 8588 … … 8615 8596 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8616 8597 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR); 8617 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8618 return VINF_SUCCESS; 8598 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8619 8599 } 8620 8600 … … 8628 8608 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8629 8609 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR); 8630 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8631 return VINF_SUCCESS; 8610 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8632 8611 } 8633 8612 … … 8642 8621 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8643 8622 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR); 8644 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8645 return VINF_SUCCESS; 8623 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8646 8624 } 8647 8625 … … 8671 8649 8672 8650 iemVmxVmSucceed(pVCpu); 8673 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8674 return VINF_SUCCESS; 8651 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8675 8652 } 8676 8653 … … 8744 8721 { 8745 8722 iemVmxVmSucceed(pVCpu); 8746 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8747 return rcStrict; 8723 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8748 8724 } 8749 8725 … … 8837 8813 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8838 8814 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR); 8839 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8840 return VINF_SUCCESS; 8815 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8841 8816 } 8842 8817 … … 8850 8825 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8851 8826 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR); 8852 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8853 return VINF_SUCCESS; 8827 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8854 8828 } 8855 8829 … … 8863 8837 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8864 8838 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR); 8865 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8866 return VINF_SUCCESS; 8839 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8867 8840 } 8868 8841 … … 8877 8850 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs; 8878 8851 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR); 8879 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8880 return VINF_SUCCESS; 8852 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8881 8853 } 8882 8854 … … 8909 8881 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs)); 8910 8882 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId; 8911 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV); 8912 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8913 return VINF_SUCCESS; 8914 } 8915 8916 Log(("vmptrld: Shadow VMCS -> VMFail()\n")); 8917 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs; 8883 } 8884 else 8885 { 8886 Log(("vmptrld: Shadow VMCS -> VMFail()\n")); 8887 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs; 8888 } 8918 8889 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV); 8919 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8920 return VINF_SUCCESS; 8890 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8921 8891 } 8922 8892 … … 8954 8924 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu)); 8955 8925 iemVmxVmSucceed(pVCpu); 8956 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 8957 return VINF_SUCCESS; 8926 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 8958 8927 } 8959 8928 … … 9054 9023 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType; 9055 9024 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND); 9056 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9057 return VINF_SUCCESS; 9025 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9058 9026 } 9059 9027 … … 9076 9044 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo; 9077 9045 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND); 9078 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9079 return VINF_SUCCESS; 9046 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9080 9047 } 9081 9048 … … 9163 9130 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9164 9131 } 9165 iemRegAddToRipAndClearRF(pVCpu, cbInstr);9132 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9166 9133 } 9167 9134 return rcStrict; … … 9266 9233 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType; 9267 9234 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND); 9268 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9269 return VINF_SUCCESS; 9235 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9270 9236 } 9271 9237 … … 9291 9257 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi; 9292 9258 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND); 9293 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9294 return VINF_SUCCESS; 9259 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9295 9260 } 9296 9261 … … 9310 9275 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr; 9311 9276 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND); 9312 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9313 return VINF_SUCCESS; 9277 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9314 9278 } 9315 9279 } … … 9321 9285 9322 9286 iemVmxVmSucceed(pVCpu); 9323 iemRegAddToRipAndClearRF(pVCpu, cbInstr);9287 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9324 9288 } 9325 9289 … … 9487 9451 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon; 9488 9452 iemVmxVmFailInvalid(pVCpu); 9489 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9490 return VINF_SUCCESS; 9453 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9491 9454 } 9492 9455 … … 9500 9463 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon; 9501 9464 iemVmxVmFailInvalid(pVCpu); 9502 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9503 return VINF_SUCCESS; 9465 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9504 9466 } 9505 9467 … … 9514 9476 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon; 9515 9477 iemVmxVmFailInvalid(pVCpu); 9516 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9517 return VINF_SUCCESS; 9478 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9518 9479 } 9519 9480 … … 9542 9503 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId; 9543 9504 iemVmxVmFailInvalid(pVCpu); 9544 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9545 return VINF_SUCCESS; 9505 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9546 9506 } 9547 9507 … … 9550 9510 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs; 9551 9511 iemVmxVmFailInvalid(pVCpu); 9552 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9553 return VINF_SUCCESS; 9512 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9554 9513 } 9555 9514 … … 9566 9525 9567 9526 iemVmxVmSucceed(pVCpu); 9568 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9569 return VINF_SUCCESS; 9570 } 9571 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) 9527 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9528 } 9529 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) 9572 9530 { 9573 9531 /* Nested-guest intercept. */ … … 9590 9548 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE); 9591 9549 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot; 9592 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9593 return VINF_SUCCESS; 9550 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9594 9551 } 9595 9552 … … 9649 9606 { 9650 9607 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON); 9651 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9652 return VINF_SUCCESS; 9608 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9653 9609 } 9654 9610 … … 9664 9620 9665 9621 iemVmxVmSucceed(pVCpu); 9666 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9667 return VINF_SUCCESS; 9622 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9668 9623 } 9669 9624 … … 9833 9788 * a VM-exit, the instruction operates normally. 9834 9789 */ 9835 iemRegAddToRipAndClearRF(pVCpu, cbInstr); 9836 return VINF_SUCCESS; 9790 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr); 9837 9791 } 9838 9792 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r97361 r97370 4348 4348 { 4349 4349 pVCpu->cpum.GstCtx.rsp = TmpRsp.u; 4350 iemRegUpdateRipAndClearRF(pVCpu);4350 return iemRegUpdateRipAndFinishClearingRF(pVCpu); 4351 4351 } 4352 4352 return rcStrict; -
trunk/src/VBox/VMM/include/IEMInline.h
r97358 r97370 1614 1614 * @param cbInstr The number of bytes to add. 1615 1615 */ 1616 DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAnd ClearRF(PVMCPUCC pVCpu, uint8_t cbInstr)1616 DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) 1617 1617 { 1618 1618 /* … … 1647 1647 1648 1648 /** 1649 * Extended version of iemRegAddToRipAndFinishingClearingRF for use by POPF and 1650 * others potentially updating EFLAGS.TF. 1651 * 1652 * The single step event must be generated using the TF value at the start of 1653 * the instruction, not the new value set by it. 1654 * 1655 * @param pVCpu The cross context virtual CPU structure of the calling thread. 1656 * @param cbInstr The number of bytes to add. 1657 * @param fEflOld The EFLAGS at the start of the instruction 1658 * execution. 1659 */ 1660 DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRfEx(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t fEflOld) 1661 { 1662 /* 1663 * Advance RIP. 1664 * 1665 * When we're targetting 8086/8, 80186/8 or 80286 mode the updates are 16-bit, 1666 * while in all other modes except LM64 the updates are 32-bit. This means 1667 * we need to watch for both 32-bit and 16-bit "carry" situations, i.e. 1668 * 4GB and 64KB rollovers, and decide whether anything needs masking. 1669 * 1670 * See PC wrap around tests in bs3-cpu-weird-1. 1671 */ 1672 uint64_t const uRipPrev = pVCpu->cpum.GstCtx.rip; 1673 uint64_t const uRipNext = uRipPrev + cbInstr; 1674 if (RT_LIKELY( !((uRipNext ^ uRipPrev) & (RT_BIT_64(32) | RT_BIT_64(16))) 1675 || CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))) 1676 pVCpu->cpum.GstCtx.rip = uRipNext; 1677 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386) 1678 pVCpu->cpum.GstCtx.rip = (uint32_t)uRipNext; 1679 else 1680 pVCpu->cpum.GstCtx.rip = (uint16_t)uRipNext; 1681 1682 /* 1683 * Clear RF and interrupt shadowing. 1684 */ 1685 AssertCompile(CPUMCTX_INHIBIT_SHADOW < UINT32_MAX); 1686 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW); 1687 1688 RT_NOREF(fEflOld); 1689 return VINF_SUCCESS; 1690 } 1691 1692 1693 /** 1649 1694 * Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF. 1650 1695 * 1651 1696 * @param pVCpu The cross context virtual CPU structure of the calling thread. 1652 1697 */ 1653 DECLINLINE(VBOXSTRICTRC) iemRegUpdateRipAnd ClearRF(PVMCPUCC pVCpu)1654 { 1655 return iemRegAddToRipAnd ClearRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu));1698 DECLINLINE(VBOXSTRICTRC) iemRegUpdateRipAndFinishClearingRF(PVMCPUCC pVCpu) 1699 { 1700 return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu)); 1656 1701 } 1657 1702 -
trunk/src/VBox/VMM/include/IEMMc.h
r97358 r97370 55 55 /** Advances RIP, finishes the instruction and returns. 56 56 * This may include raising debug exceptions and such. */ 57 #define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegUpdateRipAnd ClearRF(pVCpu)57 #define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegUpdateRipAndFinishClearingRF(pVCpu) 58 58 /** Sets RIP (may trigger \#GP), finishes the instruction and returns. */ 59 59 #define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) return iemRegRipRelativeJumpS8(pVCpu, (a_i8))
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