- Timestamp:
- Oct 20, 2022 6:02:21 AM (2 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (8 diffs)
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trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r97197 r97243 64 64 DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3); 65 65 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT 66 static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, 67 PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk); 68 static int pgmGstSlatWalkPhys(PVMCPUCC pVCpu, PGMSLAT enmSlatMode, RTGCPHYS GCPhysNested, PPGMPTWALK pWalk, 69 PPGMPTWALKGST pGstWalk); 66 static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk, 67 PPGMPTWALKGST pGstWalk); 70 68 static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3); 71 69 static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT *ppPdpt, PEPTPD *ppPD, … … 2020 2018 } 2021 2019 2020 2022 2021 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT 2023 2024 2022 /** 2025 2023 * Performs a guest second-level address translation (SLAT). 2026 *2027 * The guest paging mode must be 32-bit, PAE or AMD64 when making a call to this2028 * function.2029 2024 * 2030 2025 * @returns VBox status code. … … 2035 2030 * 2036 2031 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 2037 * @param GCPhysNested The nested-guest physical address being translated 2038 * (input). 2039 * @param fIsLinearAddrValid Whether the linear address in @a GCPtrNested is 2040 * valid. This indicates the SLAT is caused when 2041 * translating a nested-guest linear address. 2032 * @param GCPhysNested The nested-guest physical address being translated. 2033 * @param fIsLinearAddrValid Whether the linear address in @a GCPtrNested is the 2034 * cause for this translation. 2042 2035 * @param GCPtrNested The nested-guest virtual address that initiated the 2043 * SLAT. If none, pass NIL_RTGCPTR. 2044 * @param pWalk Where to return the walk result. This is valid for 2045 * some error codes as well. 2046 * @param pGstWalk The second-level paging-mode specific walk 2047 * information. 2036 * SLAT. If none, pass 0 (and not NIL_RTGCPTR). 2037 * @param pWalk Where to return the walk result. This is updated for 2038 * all error codes other than 2039 * VERR_PGM_NOT_USED_IN_MODE. 2040 * @param pGstWalk Where to store the second-level paging-mode specific 2041 * walk info. 2048 2042 */ 2049 2043 static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, … … 2053 2047 Assert( pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT 2054 2048 && pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID); 2049 AssertPtr(pWalk); 2050 AssertPtr(pGstWalk); 2055 2051 switch (pVCpu->pgm.s.enmGuestSlatMode) 2056 2052 { … … 2065 2061 } 2066 2062 } 2067 2068 2069 /**2070 * Performs a guest second-level address translation (SLAT) for a nested-guest2071 * physical address.2072 *2073 * This version requires the SLAT mode to be provided by the caller because we could2074 * be in the process of switching paging modes (MOV CRX) and cannot presume control2075 * register values.2076 *2077 * @returns VBox status code.2078 * @param pVCpu The cross context virtual CPU structure of the calling EMT.2079 * @param enmSlatMode The second-level paging mode to use.2080 * @param GCPhysNested The nested-guest physical address to translate.2081 * @param pWalk Where to store the walk result.2082 * @param pGstWalk Where to store the second-level paging-mode specific2083 * walk information.2084 */2085 static int pgmGstSlatWalkPhys(PVMCPUCC pVCpu, PGMSLAT enmSlatMode, RTGCPHYS GCPhysNested, PPGMPTWALK pWalk,2086 PPGMPTWALKGST pGstWalk)2087 {2088 AssertPtr(pWalk);2089 AssertPtr(pGstWalk);2090 switch (enmSlatMode)2091 {2092 case PGMSLAT_EPT:2093 pGstWalk->enmType = PGMPTWALKGSTTYPE_EPT;2094 return PGM_GST_SLAT_NAME_EPT(Walk)(pVCpu, GCPhysNested, false /* fIsLinearaddrValid */, 0 /* GCPtrNested */,2095 pWalk, &pGstWalk->u.Ept);2096 2097 default:2098 AssertFailed();2099 return VERR_PGM_NOT_USED_IN_MODE;2100 }2101 }2102 2103 2063 #endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */ 2064 2104 2065 2105 2066 /** … … 2562 2523 PGMPTWALK Walk; 2563 2524 PGMPTWALKGST GstWalk; 2564 int const rc = pgmGstSlatWalk Phys(pVCpu, PGMSLAT_EPT, uCr3, &Walk, &GstWalk);2525 int const rc = pgmGstSlatWalk(pVCpu, uCr3, false /* fIsLinearAddrValid */, 0 /* GCPtrNested */, &Walk, &GstWalk); 2565 2526 if (RT_SUCCESS(rc)) 2566 2527 { … … 2956 2917 PGMPTWALKGST GstWalk; 2957 2918 RTGCPHYS const GCPhysNested = PaePdpe.u & X86_PDPE_PG_MASK; 2958 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, GCPhysNested, &Walk, &GstWalk); 2919 int const rc = pgmGstSlatWalk(pVCpu, GCPhysNested, false /* fIsLinearAddrValid */, 0 /* GCPtrNested */, 2920 &Walk, &GstWalk); 2959 2921 if (RT_SUCCESS(rc)) 2960 2922 GCPhys = Walk.GCPhys; … … 3551 3513 PGMPTWALK Walk; 3552 3514 PGMPTWALKGST GstWalk; 3553 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, GCPhysCR3, &Walk, &GstWalk); 3515 int const rc = pgmGstSlatWalk(pVCpu, GCPhysCR3, false /* fIsLinearAddrValid */, 0 /* GCPtrNested */, &Walk, 3516 &GstWalk); 3554 3517 if (RT_SUCCESS(rc)) 3555 3518 { /* likely */ }
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