- Timestamp:
- Oct 19, 2022 9:12:57 AM (2 years ago)
- Location:
- trunk
- Files:
-
- 10 edited
-
include/VBox/vmm/cpum.h (modified) (4 diffs)
-
include/VBox/vmm/cpumctx.h (modified) (5 diffs)
-
include/iprt/x86.h (modified) (1 diff)
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src/VBox/VMM/VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/IEMAllCImpl.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h (modified) (1 diff)
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src/VBox/VMM/VMMR3/CPUM.cpp (modified) (6 diffs)
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src/VBox/VMM/VMMR3/EM.cpp (modified) (1 diff)
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src/VBox/VMM/include/CPUMInternal.h (modified) (1 diff)
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src/VBox/VMM/include/IEMMc.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.h
r97213 r97231 1517 1517 1518 1518 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 1519 VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);1520 VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);1519 VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves); 1520 VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX); 1521 1521 #endif 1522 1523 VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu); 1524 1522 1525 1523 1526 /** @name Guest Register Getters. … … 2753 2756 DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx) 2754 2757 { 2755 pCtx->eflags.u 32&= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);2758 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF); 2756 2759 } 2757 2760 … … 2763 2766 DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx) 2764 2767 { 2765 pCtx->eflags.u 32&= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);2766 pCtx->eflags.u 32|= X86_EFL_CF;2768 pCtx->eflags.uBoth &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF); 2769 pCtx->eflags.uBoth |= X86_EFL_CF; 2767 2770 } 2768 2771 … … 2775 2778 DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr) 2776 2779 { 2777 pCtx->eflags.u 32&= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);2778 pCtx->eflags.u 32|= X86_EFL_ZF;2780 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF); 2781 pCtx->eflags.uBoth |= X86_EFL_ZF; 2779 2782 pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr; 2780 2783 } -
trunk/include/VBox/vmm/cpumctx.h
r97213 r97231 227 227 AssertCompileSize(CPUMHWVIRT, 4); 228 228 #endif 229 230 /** Number of EFLAGS bits we put aside for the hardware EFLAGS, with the bits 231 * above this we use for storing internal state not visible to the guest. 232 * 233 * The initial plan was to use 24 or 22 here and keep bits that needs clearing 234 * on instruction boundrary in the top of the first 32 bits, allowing us to use 235 * a AND with a 32-bit immediate for clearing both RF and the interrupt shadow 236 * bits. However, when using anything less than 32, there is a significant code 237 * size increase: VMMR0.ro is 2475709 bytes with 32 bits, 2482069 bytes with 24 238 * bits, and 2482261 bytes with 22 bits. 239 * 240 * So, for now we're best off setting this to 32. 241 */ 242 #define CPUMX86EFLAGS_HW_BITS 32 243 /** Mask for the hardware EFLAGS bits, 64-bit version. */ 244 #define CPUMX86EFLAGS_HW_MASK_64 (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1)) 245 /** Mask for the hardware EFLAGS bits, 32-bit version. */ 246 #if CPUMX86EFLAGS_HW_BITS == 32 247 # define CPUMX86EFLAGS_HW_MASK_32 UINT32_MAX 248 #elif CPUMX86EFLAGS_HW_BITS < 32 && CPUMX86EFLAGS_HW_BITS >= 22 249 # define CPUMX86EFLAGS_HW_MASK_32 (RT_BIT_32(CPUMX86EFLAGS_HW_BITS) - UINT32_C(1)) 250 #else 251 # error "Misconfigured CPUMX86EFLAGS_HW_BITS value!" 252 #endif 253 254 /** Mask of internal flags kept with EFLAGS, 64-bit version. */ 255 #define CPUMX86EFLAGS_INT_MASK_64 UINT64_C(0x0000000000000000) 256 /** Mask of internal flags kept with EFLAGS, 32-bit version. */ 257 #define CPUMX86EFLAGS_INT_MASK_32 UINT64_C(0x0000000000000000) 258 259 260 /** 261 * CPUM EFLAGS. 262 * 263 * This differs from X86EFLAGS in that we could use bits 31:22 for internal 264 * purposes, see CPUMX86EFLAGS_HW_BITS. 265 */ 266 typedef union CPUMX86EFLAGS 267 { 268 /** The full unsigned view, both hardware and VBox bits. */ 269 uint32_t uBoth; 270 /** The plain unsigned view of the hardware bits. */ 271 #if CPUMX86EFLAGS_HW_BITS == 32 272 uint32_t u; 273 #else 274 uint32_t u : CPUMX86EFLAGS_HW_BITS; 275 #endif 276 #ifndef VBOX_FOR_DTRACE_LIB 277 /** The bitfield view. */ 278 X86EFLAGSBITS Bits; 279 #endif 280 } CPUMX86EFLAGS; 281 /** Pointer to CPUM EFLAGS. */ 282 typedef CPUMX86EFLAGS *PCPUMX86EFLAGS; 283 /** Pointer to const CPUM EFLAGS. */ 284 typedef const CPUMX86EFLAGS *PCCPUMX86EFLAGS; 285 286 /** 287 * CPUM RFLAGS. 288 * 289 * This differs from X86EFLAGS in that we use could be using bits 63:22 for 290 * internal purposes, see CPUMX86EFLAGS_HW_BITS. 291 */ 292 typedef union CPUMX86RFLAGS 293 { 294 /** The full unsigned view, both hardware and VBox bits. */ 295 uint64_t uBoth; 296 /** The plain unsigned view of the hardware bits. */ 297 #if CPUMX86EFLAGS_HW_BITS == 32 298 uint32_t u; 299 #else 300 uint32_t u : CPUMX86EFLAGS_HW_BITS; 301 #endif 302 #ifndef VBOX_FOR_DTRACE_LIB 303 /** The bitfield view. */ 304 X86EFLAGSBITS Bits; 305 #endif 306 } CPUMX86RFLAGS; 307 /** Pointer to CPUM RFLAGS. */ 308 typedef CPUMX86RFLAGS *PCPUMX86RFLAGS; 309 /** Pointer to const CPUM RFLAGS. */ 310 typedef const CPUMX86RFLAGS *PCCPUMX86RFLAGS; 229 311 230 312 … … 306 388 union 307 389 { 308 X86EFLAGSeflags;309 X86RFLAGSrflags;390 CPUMX86EFLAGS eflags; 391 CPUMX86RFLAGS rflags; 310 392 } CPUM_UNION_NM(rflags); 311 393 … … 322 404 uint64_t cr3; 323 405 uint64_t cr4; 324 /** @todo Add the 4 PAE PDPE registers. See PGMCPU::aGstPaePdpeRegs. */325 406 /** @} */ 326 407 … … 351 432 /** @name System MSRs. 352 433 * @{ */ 353 uint64_t msrEFER; 434 uint64_t msrEFER; /**< @todo move EFER up to the crX registers for better cacheline mojo */ 354 435 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */ 355 436 uint64_t msrPAT; /**< Page attribute table. */ … … 570 651 AssertCompileMemberOffset(CPUMCTX, tr, 0x0128); 571 652 AssertCompileMemberOffset(CPUMCTX, rip, 0x0140); 653 AssertCompileMemberOffset(CPUMCTX, eflags, 0x0148); 572 654 AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148); 573 655 AssertCompileMemberOffset(CPUMCTX, fInhibit, 0x0150); -
trunk/include/iprt/x86.h
r96977 r97231 231 231 /** Read as 1 bits. */ 232 232 #define X86_EFL_RA1_MASK RT_BIT_32(1) 233 /** Read as 0 bits, excluding bits 31:22. 234 * Bits 3, 5, 15, and 22 thru 31. */ 235 #define X86_EFL_RAZ_MASK UINT32_C(0xffc08028) 236 /** Read as 0 bits, excluding bits 31:22. 237 * Bits 3, 5 and 15. */ 238 #define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028) 233 239 /** IOPL shift. */ 234 240 #define X86_EFL_IOPL_SHIFT 12 -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r97220 r97231 184 184 { 185 185 return pVCpu->cpum.s.Hyper.dr[7]; 186 } 187 188 189 /** 190 * Checks that the special cookie stored in unused reserved RFLAGS bits 191 * 192 * @retval true if cookie is ok. 193 * @retval false if cookie is not ok. 194 * @param pVM The cross context VM structure. 195 * @param pVCpu The cross context virtual CPU structure. 196 */ 197 VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu) 198 { 199 AssertLogRelMsgReturn( (pVCpu->cpum.s.Guest.rflags.uBoth & ~(uint64_t)(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK)) 200 == pVM->cpum.s.fReservedRFlagsCookie 201 && (pVCpu->cpum.s.Guest.rflags.uBoth & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK, 202 ("rflags=%#RX64 vs fReservedRFlagsCookie=%#RX64\n", 203 pVCpu->cpum.s.Guest.rflags.uBoth, pVM->cpum.s.fReservedRFlagsCookie), 204 false); 205 return true; 186 206 } 187 207 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
r97208 r97231 8024 8024 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10) 8025 8025 { 8026 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u 32);8026 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth); 8027 8027 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1; 8028 8028 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1; … … 8069 8069 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10) 8070 8070 { 8071 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u 32);8071 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth); 8072 8072 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1; 8073 8073 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1; -
trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r97223 r97231 1805 1805 Use 32-bit VMWRITE. */ 1806 1806 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u; 1807 Assert( fEFlags &X86_EFL_RA1_MASK);1808 Assert (!(fEFlags & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));1807 Assert((fEFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK); 1808 AssertMsg(!(fEFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK)), ("%#x\n", fEFlags)); 1809 1809 1810 1810 #ifndef IN_NEM_DARWIN -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r97219 r97231 145 145 #include <iprt/mem.h> 146 146 #include <iprt/mp.h> 147 #include <iprt/rand.h> 147 148 #include <iprt/string.h> 148 149 … … 2205 2206 2206 2207 /* 2208 * Generate the RFLAGS cookie. 2209 */ 2210 pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64); 2211 2212 /* 2207 2213 * Init the VMX/SVM state. 2208 2214 * … … 2220 2226 Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE); 2221 2227 2228 /* 2229 * Initialize the general guest CPU state. 2230 */ 2222 2231 CPUMR3Reset(pVM); 2232 2223 2233 return VINF_SUCCESS; 2224 2234 } … … 2303 2313 pCtx->eip = 0x0000fff0; 2304 2314 pCtx->edx = 0x00000600; /* P6 processor */ 2305 pCtx->eflags.Bits.u1Reserved0 = 1; 2315 2316 Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK | X86_EFL_RAZ_LO_MASK | X86_EFL_RA1_MASK)) == 0); 2317 pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie | X86_EFL_RA1_MASK; 2306 2318 2307 2319 pCtx->cs.Sel = 0xf000; … … 2495 2507 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 2496 2508 { 2497 PVMCPU pVCpu = pVM->apCpusR3[idCpu]; 2498 2509 PVMCPU const pVCpu = pVM->apCpusR3[idCpu]; 2510 PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest; 2511 2512 /** @todo ditch this the next time we change the saved state. */ 2499 2513 SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL); 2500 2514 2501 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest; 2515 uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth; 2516 pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */ 2502 2517 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL); 2518 pGstCtx->rflags.uBoth = fSavedRFlags; 2519 2503 2520 SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL); 2504 2521 if (pGstCtx->fXStateMask != 0) … … 2922 2939 AssertRCReturn(rc, rc); 2923 2940 2941 /* Deal with the reusing of reserved RFLAGS bits. */ 2942 pGstCtx->rflags.uBoth |= pVM->cpum.s.fReservedRFlagsCookie; 2943 2924 2944 /* REM and other may have cleared must-be-one fields in DR6 and 2925 2945 DR7, fix these. */ -
trunk/src/VBox/VMM/VMMR3/EM.cpp
r97178 r97231 2210 2210 fFFDone = false; 2211 2211 2212 #ifdef VBOX_STRICT 2213 CPUMAssertGuestRFlagsCookie(pVM, pVCpu); 2214 #endif 2215 2212 2216 /* 2213 2217 * Now what to do? -
trunk/src/VBox/VMM/include/CPUMInternal.h
r97213 r97231 382 382 uint8_t abPadding1[1]; 383 383 384 /** Random value we store in the reserved RFLAGS bits we don't use ourselves so 385 * we can detect corruption. */ 386 uint64_t fReservedRFlagsCookie; 387 384 388 /** Align to 64-byte boundary. */ 385 uint8_t abPadding2[ 20+4];389 uint8_t abPadding2[16]; 386 390 387 391 /** Host CPU feature information. -
trunk/src/VBox/VMM/include/IEMMc.h
r97153 r97231 334 334 #define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg)) 335 335 #define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg)) 336 /** @note Not for IOPL or IF testing or modification. */ 337 #define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u 336 /** @note Not for IOPL or IF testing or modification. 337 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */ 338 #define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth 338 339 #define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR 339 340
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