- Timestamp:
- Oct 18, 2022 11:09:55 AM (2 years ago)
- Location:
- trunk
- Files:
-
- 14 edited
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include/VBox/vmm/em.h (modified) (1 diff)
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include/VBox/vmm/iem.h (modified) (1 diff)
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include/VBox/vmm/pgm.h (modified) (4 diffs)
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src/VBox/VMM/VMMAll/EMAll.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/IOMAllMmioNew.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (24 diffs)
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src/VBox/VMM/VMMAll/PGMAllPhys.cpp (modified) (3 diffs)
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src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h (modified) (3 diffs)
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src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR0/PGMR0.cpp (modified) (3 diffs)
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src/VBox/VMM/include/PGMInternal.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/em.h
r97193 r97197 271 271 VMM_INT_DECL(int) EMInterpretDisasOneEx(PVMCPUCC pVCpu, RTGCUINTPTR GCPtrInstr, 272 272 PDISCPUSTATE pDISState, unsigned *pcbInstr); 273 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu , PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);273 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu); 274 274 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten); 275 275 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPUCC pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx, -
trunk/include/VBox/vmm/iem.h
r96407 r97197 292 292 VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC, 293 293 const void *pvOpcodeBytes, size_t cbOpcodeBytes); 294 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore,uint32_t *pcbWritten);294 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten); 295 295 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC, 296 296 const void *pvOpcodeBytes, size_t cbOpcodeBytes); -
trunk/include/VBox/vmm/pgm.h
r96979 r97197 206 206 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 207 207 * @param uErrorCode CPU Error code. 208 * @param pRegFrame Trap register frame. 209 * NULL on DMA and other non CPU access. 208 * @param pCtx Pointer to the register context for the CPU. 210 209 * @param pvFault The fault address (cr2). 211 210 * @param GCPhysFault The GC physical address corresponding to pvFault. … … 213 212 * @thread EMT(pVCpu) 214 213 */ 215 typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX CORE pRegFrame,214 typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx, 216 215 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)); 217 216 /** Pointer to PGM access callback. */ … … 619 618 VMMDECL(void) PGMDeregisterStringFormatTypes(void); 620 619 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu); 621 VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPTR pvFault);620 VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault); 622 621 VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage); 623 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMC C pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);622 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault); 624 623 VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys); 625 624 VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags); … … 984 983 PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault); 985 984 VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, 986 PCPUMCTX CORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);985 PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr); 987 986 VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu); 988 987 -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r97193 r97197 958 958 * 959 959 * @param pVCpu The cross context virtual CPU structure. 960 * @param pRegFrame The register frame. 961 * Updates the EIP if an instruction was executed successfully. 962 * @param pvFault The fault address (CR2). 963 * 964 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel 965 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need 966 * to worry about e.g. invalid modrm combinations (!) 967 */ 968 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault) 969 { 970 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu)); 971 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault)); 972 NOREF(pvFault); 973 974 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL); 960 * 961 * @remark Invalid opcode exceptions have a higher priority than \#GP (see 962 * Intel Architecture System Developers Manual, Vol 3, 5.5) so we don't 963 * need to worry about e.g. invalid modrm combinations (!) 964 */ 965 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu) 966 { 967 LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu))); 968 969 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, NULL /*pcbWritten*/); 975 970 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED 976 971 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)) … … 978 973 if (rc != VINF_SUCCESS) 979 974 Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc))); 980 981 return rc;982 }983 984 985 /**986 * Interprets the current instruction.987 *988 * @returns VBox status code.989 * @retval VINF_* Scheduling instructions.990 * @retval VERR_EM_INTERPRETER Something we can't cope with.991 * @retval VERR_* Fatal errors.992 *993 * @param pVCpu The cross context virtual CPU structure of the calling EMT.994 * @param pRegFrame The register frame.995 * Updates the EIP if an instruction was executed successfully.996 * @param pvFault The fault address (CR2).997 * @param pcbWritten Size of the write (if applicable).998 *999 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel1000 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need1001 * to worry about e.g. invalid modrm combinations (!)1002 */1003 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)1004 {1005 LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));1006 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));1007 NOREF(pvFault);1008 1009 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);1010 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED1011 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))1012 rc = VERR_EM_INTERPRETER;1013 if (rc != VINF_SUCCESS)1014 Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));1015 975 1016 976 return rc; -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r97178 r97197 9849 9849 9850 9850 9851 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten) 9852 { 9853 AssertReturn(CPUMCTX2CORE(IEM_GET_CTX(pVCpu)) == pCtxCore, VERR_IEM_IPE_3); 9854 9851 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten) 9852 { 9855 9853 uint32_t const cbOldWritten = pVCpu->iem.s.cbWritten; 9856 9854 VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pVCpu, true, false); -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp
r97180 r97197 9882 9882 * \#PF access handler callback for guest VMX APIC-access page.} 9883 9883 */ 9884 DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame,9884 DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, 9885 9885 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser) 9886 9886 9887 9887 { 9888 RT_NOREF3(pVM, p RegFrame, uUser);9888 RT_NOREF3(pVM, pCtx, uUser); 9889 9889 9890 9890 /* -
trunk/src/VBox/VMM/VMMAll/IOMAllMmioNew.cpp
r96407 r97197 738 738 * @remarks The @a uUser argument is the MMIO handle. 739 739 */ 740 DECLCALLBACK(VBOXSTRICTRC) iomMmioPfHandlerNew(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX CORE pCtxCore,740 DECLCALLBACK(VBOXSTRICTRC) iomMmioPfHandlerNew(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx, 741 741 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser) 742 742 { 743 743 STAM_PROFILE_START(&pVM->iom.s.StatMmioPfHandler, Prf); 744 744 LogFlow(("iomMmioPfHandlerNew: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n", 745 GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtx Core->rip));746 RT_NOREF(pvFault, pCtx Core);745 GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtx->rip)); 746 RT_NOREF(pvFault, pCtx); 747 747 748 748 /* Translate the MMIO handle to a registration entry for the current context. */ -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r97039 r97197 975 975 * @param pVCpu The cross context virtual CPU structure. 976 976 * @param uErr The trap error code. 977 * @param p RegFrame Trap register frame.977 * @param pCtx Pointer to the register context for the CPU. 978 978 * @param pvFault The fault address. 979 979 */ 980 VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPTR pvFault)980 VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault) 981 981 { 982 982 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 983 983 984 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, p RegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));984 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu))); 985 985 STAM_PROFILE_START(&pVCpu->pgm.s.Stats.StatRZTrap0e, a); 986 986 STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = NULL; } ); … … 1034 1034 AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE); 1035 1035 bool fLockTaken = false; 1036 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, p RegFrame, pvFault, &fLockTaken);1036 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pCtx, pvFault, &fLockTaken); 1037 1037 if (fLockTaken) 1038 1038 { … … 1056 1056 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */ 1057 1057 { 1058 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, p RegFrame->rip));1058 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pCtx->rip)); 1059 1059 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */ 1060 1060 rc = VINF_SUCCESS; … … 1152 1152 * 1153 1153 * @returns VBox status code (appropriate for trap handling and GC return). 1154 * @param pVM The cross context VM structure.1155 1154 * @param pVCpu The cross context virtual CPU structure. 1156 * @param pRegFrame Register frame.1157 1155 * @param pvFault Fault address. 1158 1156 */ 1159 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMC C pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)1160 { 1161 NOREF(pVM);1162 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu , pRegFrame, pvFault);1157 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault) 1158 { 1159 RT_NOREF(pvFault); 1160 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu); 1163 1161 if (rc == VERR_EM_INTERPRETER) 1164 1162 rc = VINF_EM_RAW_EMULATE_INSTR; -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r97158 r97197 46 46 PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3); 47 47 #ifndef IN_RING3 48 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);49 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPHYS GCPhysNestedFault,48 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken); 49 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault, 50 50 bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken); 51 51 # if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT … … 226 226 * @param pVCpu The cross context virtual CPU structure of the calling EMT. 227 227 * @param uErr The error code. 228 * @param p RegFrame The register frame.228 * @param pCtx Pointer to the register context for the CPU. 229 229 * @param pvFault The fault address. 230 230 * @param pPage The guest page at @a pvFault. … … 234 234 * when we're called. 235 235 */ 236 static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame,236 static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, 237 237 RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken 238 238 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) || defined(DOXYGEN_RUNNING) … … 337 337 if (pCurType->fKeepPgmLock) 338 338 { 339 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, p RegFrame, pvFault, GCPhysFault,339 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, 340 340 !pCurType->fRing0DevInsIdx ? pCur->uUser 341 341 : (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser)); … … 350 350 *pfLockTaken = false; 351 351 352 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, p RegFrame, pvFault, GCPhysFault, uUser);352 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser); 353 353 354 354 STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */ … … 396 396 * It's writing to an unhandled part of the LDT page several million times. 397 397 */ 398 rcStrict = PGMInterpretInstruction(pV M, pVCpu, pRegFrame, pvFault);398 rcStrict = PGMInterpretInstruction(pVCpu, pvFault); 399 399 LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage)); 400 400 STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; }); … … 411 411 * @param pVCpu The cross context virtual CPU structure. 412 412 * @param uErr The trap error code. 413 * @param p RegFrame Trap register frame.413 * @param pCtx Pointer to the register context for the CPU. 414 414 * @param pvFault The fault address. 415 415 * @param pfLockTaken PGM lock taken here or not (out) 416 416 */ 417 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)417 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken) 418 418 { 419 419 PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM); … … 563 563 rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage); 564 564 if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) 565 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, p RegFrame, pvFault, pPage,565 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, 566 566 pfLockTaken, &Walk, &GstWalk)); 567 567 rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr); … … 569 569 rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage); 570 570 if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) 571 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, 572 pfLockTaken)); 571 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken)); 573 572 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr); 574 573 # endif … … 713 712 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage)) 714 713 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) 715 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, p RegFrame, pvFault, pPage, pfLockTaken,714 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken, 716 715 &Walk, &GstWalk)); 717 716 # else 718 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, p RegFrame, pvFault, pPage, pfLockTaken));717 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken)); 719 718 # endif 720 719 … … 740 739 our shadow page tables. (Required for e.g. Solaris guests; soft 741 740 ecc, random nr generator.) */ 742 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pV M, pVCpu, pRegFrame, pvFault));741 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault)); 743 742 LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage)); 744 743 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon)); … … 836 835 837 836 /* Interpret the access. */ 838 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pV M, pVCpu, pRegFrame, pvFault));837 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault)); 839 838 Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK))); 840 839 if (RT_SUCCESS(rc)) … … 979 978 */ 980 979 LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n", 981 __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, p RegFrame->cs.Sel, pRegFrame->rip));980 __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip)); 982 981 return rc; 983 982 984 983 # else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */ 985 NOREF(uErr); NOREF(p RegFrame); NOREF(pvFault);984 NOREF(uErr); NOREF(pCtx); NOREF(pvFault); 986 985 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE)); 987 986 return VERR_PGM_NOT_USED_IN_MODE; … … 997 996 * @param pVCpu The cross context virtual CPU structure. 998 997 * @param uErr The error code. 999 * @param p RegFrame The register frame.998 * @param pCtx Pointer to the register context for the CPU. 1000 999 * @param GCPhysNestedFault The nested-guest physical address of the fault. 1001 1000 * @param pPage The guest page at @a GCPhysNestedFault. … … 1007 1006 * @note The caller has taken the PGM lock. 1008 1007 */ 1009 static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame,1008 static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, 1010 1009 RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage, 1011 1010 RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll, … … 1094 1093 if (pCurType->fKeepPgmLock) 1095 1094 { 1096 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, p RegFrame, GCPhysNestedFault, GCPhysFault, uUser);1095 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser); 1097 1096 STAM_PROFILE_STOP(&pCur->Stat, h); 1098 1097 } … … 1101 1100 PGM_UNLOCK(pVM); 1102 1101 *pfLockTaken = false; 1103 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, p RegFrame, GCPhysNestedFault, GCPhysFault, uUser);1102 rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser); 1104 1103 STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */ 1105 1104 } … … 1115 1114 1116 1115 # else 1117 RT_NOREF8(pVCpu, uErr, p RegFrame, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);1116 RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken); 1118 1117 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE)); 1119 1118 return VERR_PGM_NOT_USED_IN_MODE; … … 1130 1129 * @param pVCpu The cross context virtual CPU structure. 1131 1130 * @param uErr The fault error (X86_TRAP_PF_*). 1132 * @param p RegFrame The register frame.1131 * @param pCtx Pointer to the register context for the CPU. 1133 1132 * @param GCPhysNestedFault The nested-guest physical address of the fault. 1134 1133 * @param fIsLinearAddrValid Whether translation of a nested-guest linear address … … 1140 1139 * when this function completes. 1141 1140 */ 1142 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPHYS GCPhysNestedFault,1141 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault, 1143 1142 bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken) 1144 1143 { … … 1165 1164 if (fIsLinearAddrValid) 1166 1165 Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n", 1167 p RegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));1166 pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault)); 1168 1167 else 1169 1168 Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n", 1170 p RegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedFault, uErr));1169 pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr)); 1171 1170 PGMPTWALKGST GstWalkAll; 1172 1171 int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll); … … 1258 1257 { 1259 1258 Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage)); 1260 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, p RegFrame, GCPhysNestedFault,1259 return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault, 1261 1260 pPage, pWalk->GCPhys, &GstWalkAll, 1262 1261 pfLockTaken)); … … 1323 1322 */ 1324 1323 Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n", 1325 p RegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));1324 pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys)); 1326 1325 rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll); 1327 1326 if (RT_SUCCESS(rc)) … … 1337 1336 */ 1338 1337 LogRelFunc(("GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n", rc, GCPhysNestedFault, GCPhysPage, 1339 (uint32_t)uErr, p RegFrame->cs.Sel, pRegFrame->rip));1338 (uint32_t)uErr, pCtx->cs.Sel, pCtx->rip)); 1340 1339 return VERR_PGM_MAPPING_IPE; 1341 1340 1342 1341 # else 1343 RT_NOREF7(pVCpu, uErr, p RegFrame, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);1342 RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk); 1344 1343 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE)); 1345 1344 return VERR_PGM_NOT_USED_IN_MODE; -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r97193 r97197 200 200 * @remarks The @a uUser argument is the PGMROMRANGE::GCPhys value. 201 201 */ 202 DECLCALLBACK(VBOXSTRICTRC) pgmPhysRomWritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX CORE pRegFrame,202 DECLCALLBACK(VBOXSTRICTRC) pgmPhysRomWritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx, 203 203 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser) 204 204 … … 234 234 * adding this kind of detection to DIS or EM. */ 235 235 case OP_MOV: 236 p RegFrame->rip += cbOp;236 pCtx->rip += cbOp; 237 237 STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZGuestROMWriteHandled); 238 238 return VINF_SUCCESS; … … 435 435 * @remarks The @a uUser is the MMIO2 index. 436 436 */ 437 DECLCALLBACK(VBOXSTRICTRC) pgmPhysMmio2WritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX CORE pRegFrame,437 DECLCALLBACK(VBOXSTRICTRC) pgmPhysMmio2WritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx, 438 438 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser) 439 439 { 440 RT_NOREF(pVCpu, uErrorCode, p RegFrame);440 RT_NOREF(pVCpu, uErrorCode, pCtx); 441 441 VBOXSTRICTRC rcStrict = PGM_LOCK(pVM); /* We should already have it, but just make sure we do. */ 442 442 if (RT_SUCCESS(rcStrict)) -
trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r97196 r97197 6853 6853 } 6854 6854 6855 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;6856 6855 int rc = vmxHCImportGuestState<HMVMX_CPUMCTX_EXTRN_ALL>(pVCpu, pVmxTransient->pVmcsInfo, __FUNCTION__); 6857 6856 AssertRCReturn(rc, rc); 6858 6857 6859 Log4Func(("#PF: cs:rip=%#04x:%08RX64 err_code=%#RX32 exit_qual=%#RX64 cr3=%#RX64\n", p Ctx->cs.Sel, pCtx->rip,6860 pV mxTransient->uExitIntErrorCode, pVmxTransient->uExitQual, pCtx->cr3));6858 Log4Func(("#PF: cs:rip=%#04x:%08RX64 err_code=%#RX32 exit_qual=%#RX64 cr3=%#RX64\n", pVCpu->cpum.GstCtx.cs.Sel, 6859 pVCpu->cpum.GstCtx.rip, pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual, pVCpu->cpum.GstCtx.cr3)); 6861 6860 6862 6861 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode); 6863 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);6862 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, &pVCpu->cpum.GstCtx, (RTGCPTR)pVmxTransient->uExitQual); 6864 6863 6865 6864 Log4Func(("#PF: rc=%Rrc\n", rc)); … … 9286 9285 */ 9287 9286 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 9288 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;9289 9287 /** @todo bird: We can probably just go straight to IOM here and assume that 9290 9288 * it's MMIO, then fall back on PGM if that hunch didn't work out so … … 9296 9294 * updating and use a bit more carefully first (or do all updates via 9297 9295 * rendezvous) */ 9298 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);9299 Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, p Ctx->rip, VBOXSTRICTRC_VAL(rcStrict)));9296 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, &pVCpu->cpum.GstCtx, GCPhys, UINT32_MAX); 9297 Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict))); 9300 9298 if ( rcStrict == VINF_SUCCESS 9301 9299 || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r97196 r97197 7570 7570 */ 7571 7571 /** @todo Decode assist. */ 7572 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu , CPUMCTX2CORE(pCtx), 0 /* pvFault */);7572 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu); 7573 7573 Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc))); 7574 7574 if (RT_LIKELY(rc == VINF_SUCCESS)) … … 7949 7949 { 7950 7950 7951 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr, 7952 u32ErrCode); 7951 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, pCtx, GCPhysFaultAddr, u32ErrCode); 7953 7952 7954 7953 /* … … 8293 8292 8294 8293 TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode); 8295 int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);8294 int rc = PGMTrap0eHandler(pVCpu, uErrCode, pCtx, (RTGCPTR)uFaultAddress); 8296 8295 8297 8296 Log4Func(("#PF: rc=%Rrc\n", rc)); … … 9113 9112 instruction(s) when interrupt inhibition is set as part of emulating the VMRUN 9114 9113 instruction itself, see @bugref{7243#c126} */ 9115 rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),NULL /* pcbWritten */);9114 rcStrict = IEMExecOneBypassEx(pVCpu, NULL /* pcbWritten */); 9116 9115 } 9117 9116 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z); -
trunk/src/VBox/VMM/VMMR0/PGMR0.cpp
r96979 r97197 1279 1279 * EMT. 1280 1280 * @param enmShwPagingMode Paging mode for the nested page tables. 1281 * @param p RegFrame Trap register frame.1281 * @param pCtx Pointer to the register context for the CPU. 1282 1282 * @param GCPhysFault The fault address. 1283 1283 * @param uErr The error code, UINT32_MAX if not available … … 1285 1285 */ 1286 1286 VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, 1287 PCPUMCTX CORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr)1287 PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr) 1288 1288 { 1289 1289 #ifdef PGM_WITH_MMIO_OPTIMIZATIONS … … 1330 1330 1331 1331 Log6(("PGMR0Trap0eHandlerNPMisconfig: calling %p(,%#x,,%RGp,%p)\n", pHandlerType->pfnPfHandler, uErr, GCPhysFault, uUser)); 1332 rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, p RegFrame,1332 rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, pCtx, 1333 1333 GCPhysFault, GCPhysFault, uUser); 1334 1334 -
trunk/src/VBox/VMM/include/PGMInternal.h
r97145 r97197 2797 2797 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)); 2798 2798 #ifndef IN_RING3 2799 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));2800 DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX CORE pRegFrame, RTGCPHYS GCPhysNested,2799 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)); 2800 DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested, 2801 2801 bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk, 2802 2802 bool *pfLockTaken));
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