VirtualBox

Changeset 97197 in vbox for trunk


Ignore:
Timestamp:
Oct 18, 2022 11:09:55 AM (2 years ago)
Author:
vboxsync
Message:

VMM/PGM,IEM,EM: Changed FNPGMRZPHYSPFHANDLER, PGMTrap0eHandler and PGMR0Trap0eHandlerNPMisconfig to take PCPUMCTX instead of PCPUMCTXCORE parameters; dropped PCPUMCTXCORE parameters from IEMExecOneBypassEx, PGMInterpretInstruction and EMInterpretInstruction together with some associated cleanups.

Location:
trunk
Files:
14 edited

Legend:

Unmodified
Added
Removed
  • trunk/include/VBox/vmm/em.h

    r97193 r97197  
    271271VMM_INT_DECL(int)               EMInterpretDisasOneEx(PVMCPUCC pVCpu, RTGCUINTPTR GCPtrInstr,
    272272                                                      PDISCPUSTATE pDISState, unsigned *pcbInstr);
    273 VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstruction(PVMCPUCC pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
     273VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstruction(PVMCPUCC pVCpu);
    274274VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstructionEx(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
    275275VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstructionDisasState(PVMCPUCC pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
  • trunk/include/VBox/vmm/iem.h

    r96407 r97197  
    292292VMMDECL(VBOXSTRICTRC)       IEMExecOneWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
    293293                                                         const void *pvOpcodeBytes, size_t cbOpcodeBytes);
    294 VMMDECL(VBOXSTRICTRC)       IEMExecOneBypassEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
     294VMMDECL(VBOXSTRICTRC)       IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten);
    295295VMMDECL(VBOXSTRICTRC)       IEMExecOneBypassWithPrefetchedByPC(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
    296296                                                               const void *pvOpcodeBytes, size_t cbOpcodeBytes);
  • trunk/include/VBox/vmm/pgm.h

    r96979 r97197  
    206206 * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
    207207 * @param   uErrorCode  CPU Error code.
    208  * @param   pRegFrame   Trap register frame.
    209  *                      NULL on DMA and other non CPU access.
     208 * @param   pCtx        Pointer to the register context for the CPU.
    210209 * @param   pvFault     The fault address (cr2).
    211210 * @param   GCPhysFault The GC physical address corresponding to pvFault.
     
    213212 * @thread  EMT(pVCpu)
    214213 */
    215 typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
     214typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
    216215                                                             RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
    217216/** Pointer to PGM access callback. */
     
    619618VMMDECL(void)           PGMDeregisterStringFormatTypes(void);
    620619VMMDECL(RTHCPHYS)       PGMGetHyperCR3(PVMCPU pVCpu);
    621 VMMDECL(int)            PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     620VMMDECL(int)            PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault);
    622621VMMDECL(int)            PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
    623 VMMDECL(VBOXSTRICTRC)   PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     622VMMDECL(VBOXSTRICTRC)   PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault);
    624623VMMDECL(int)            PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
    625624VMMDECL(int)            PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
     
    984983                                                    PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
    985984VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
    986                                                       PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
     985                                                      PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr);
    987986VMMR0_INT_DECL(int)  PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
    988987
  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r97193 r97197  
    958958 *
    959959 * @param   pVCpu       The cross context virtual CPU structure.
    960  * @param   pRegFrame   The register frame.
    961  *                      Updates the EIP if an instruction was executed successfully.
    962  * @param   pvFault     The fault address (CR2).
    963  *
    964  * @remark  Invalid opcode exceptions have a higher priority than GP (see Intel
    965  *          Architecture System Developers Manual, Vol 3, 5.5) so we don't need
    966  *          to worry about e.g. invalid modrm combinations (!)
    967  */
    968 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    969 {
    970     Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    971     LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    972     NOREF(pvFault);
    973 
    974     VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
     960 *
     961 * @remark  Invalid opcode exceptions have a higher priority than \#GP (see
     962 *          Intel Architecture System Developers Manual, Vol 3, 5.5) so we don't
     963 *          need to worry about e.g. invalid modrm combinations (!)
     964 */
     965VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu)
     966{
     967    LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
     968
     969    VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, NULL /*pcbWritten*/);
    975970    if (RT_UNLIKELY(   rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
    976971                    || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
     
    978973    if (rc != VINF_SUCCESS)
    979974        Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
    980 
    981     return rc;
    982 }
    983 
    984 
    985 /**
    986  * Interprets the current instruction.
    987  *
    988  * @returns VBox status code.
    989  * @retval  VINF_*                  Scheduling instructions.
    990  * @retval  VERR_EM_INTERPRETER     Something we can't cope with.
    991  * @retval  VERR_*                  Fatal errors.
    992  *
    993  * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
    994  * @param   pRegFrame   The register frame.
    995  *                      Updates the EIP if an instruction was executed successfully.
    996  * @param   pvFault     The fault address (CR2).
    997  * @param   pcbWritten  Size of the write (if applicable).
    998  *
    999  * @remark  Invalid opcode exceptions have a higher priority than GP (see Intel
    1000  *          Architecture System Developers Manual, Vol 3, 5.5) so we don't need
    1001  *          to worry about e.g. invalid modrm combinations (!)
    1002  */
    1003 VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
    1004 {
    1005     LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
    1006     Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    1007     NOREF(pvFault);
    1008 
    1009     VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
    1010     if (RT_UNLIKELY(   rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
    1011                     || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
    1012         rc = VERR_EM_INTERPRETER;
    1013     if (rc != VINF_SUCCESS)
    1014         Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
    1015975
    1016976    return rc;
  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r97178 r97197  
    98499849
    98509850
    9851 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten)
    9852 {
    9853     AssertReturn(CPUMCTX2CORE(IEM_GET_CTX(pVCpu)) == pCtxCore, VERR_IEM_IPE_3);
    9854 
     9851VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten)
     9852{
    98559853    uint32_t const cbOldWritten = pVCpu->iem.s.cbWritten;
    98569854    VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pVCpu, true, false);
  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp

    r97180 r97197  
    98829882 *      \#PF access handler callback for guest VMX APIC-access page.}
    98839883 */
    9884 DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
     9884DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
    98859885                                                         RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
    98869886
    98879887{
    9888     RT_NOREF3(pVM, pRegFrame, uUser);
     9888    RT_NOREF3(pVM, pCtx, uUser);
    98899889
    98909890    /*
  • trunk/src/VBox/VMM/VMMAll/IOMAllMmioNew.cpp

    r96407 r97197  
    738738 * @remarks The @a uUser argument is the MMIO handle.
    739739 */
    740 DECLCALLBACK(VBOXSTRICTRC) iomMmioPfHandlerNew(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pCtxCore,
     740DECLCALLBACK(VBOXSTRICTRC) iomMmioPfHandlerNew(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
    741741                                               RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
    742742{
    743743    STAM_PROFILE_START(&pVM->iom.s.StatMmioPfHandler, Prf);
    744744    LogFlow(("iomMmioPfHandlerNew: GCPhys=%RGp uErr=%#x pvFault=%RGv rip=%RGv\n",
    745              GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtxCore->rip));
    746     RT_NOREF(pvFault, pCtxCore);
     745             GCPhysFault, (uint32_t)uErrorCode, pvFault, (RTGCPTR)pCtx->rip));
     746    RT_NOREF(pvFault, pCtx);
    747747
    748748    /* Translate the MMIO handle to a registration entry for the current context. */
  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r97039 r97197  
    975975 * @param   pVCpu       The cross context virtual CPU structure.
    976976 * @param   uErr        The trap error code.
    977  * @param   pRegFrame   Trap register frame.
     977 * @param   pCtx        Pointer to the register context for the CPU.
    978978 * @param   pvFault     The fault address.
    979979 */
    980 VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
     980VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault)
    981981{
    982982    PVMCC pVM = pVCpu->CTX_SUFF(pVM);
    983983
    984     Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
     984    Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
    985985    STAM_PROFILE_START(&pVCpu->pgm.s.Stats.StatRZTrap0e, a);
    986986    STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = NULL; } );
     
    10341034    AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
    10351035    bool fLockTaken = false;
    1036     int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
     1036    int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pCtx, pvFault, &fLockTaken);
    10371037    if (fLockTaken)
    10381038    {
     
    10561056            ||  rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)     /* precaution */
    10571057        {
    1058             Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
     1058            Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pCtx->rip));
    10591059            /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
    10601060            rc = VINF_SUCCESS;
     
    11521152 *
    11531153 * @returns VBox status code (appropriate for trap handling and GC return).
    1154  * @param   pVM         The cross context VM structure.
    11551154 * @param   pVCpu       The cross context virtual CPU structure.
    1156  * @param   pRegFrame   Register frame.
    11571155 * @param   pvFault     Fault address.
    11581156 */
    1159 VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
    1160 {
    1161     NOREF(pVM);
    1162     VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
     1157VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault)
     1158{
     1159    RT_NOREF(pvFault);
     1160    VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu);
    11631161    if (rc == VERR_EM_INTERPRETER)
    11641162        rc = VINF_EM_RAW_EMULATE_INSTR;
  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r97158 r97197  
    4646PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
    4747#ifndef IN_RING3
    48 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
    49 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNestedFault,
     48PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken);
     49PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
    5050                                       bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
    5151# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
     
    226226 * @param   pVCpu           The cross context virtual CPU structure of the calling EMT.
    227227 * @param   uErr            The error code.
    228  * @param   pRegFrame       The register frame.
     228 * @param   pCtx            Pointer to the register context for the CPU.
    229229 * @param   pvFault         The fault address.
    230230 * @param   pPage           The guest page at @a pvFault.
     
    234234 *                          when we're called.
    235235 */
    236 static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
     236static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
    237237                                                                RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
    238238# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) || defined(DOXYGEN_RUNNING)
     
    337337                if (pCurType->fKeepPgmLock)
    338338                {
    339                     rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault,
     339                    rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault,
    340340                                                      !pCurType->fRing0DevInsIdx ? pCur->uUser
    341341                                                      : (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
     
    350350                    *pfLockTaken = false;
    351351
    352                     rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, uUser);
     352                    rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser);
    353353
    354354                    STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
     
    396396     *        It's writing to an unhandled part of the LDT page several million times.
    397397     */
    398     rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
     398    rcStrict = PGMInterpretInstruction(pVCpu, pvFault);
    399399    LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
    400400    STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
     
    411411 * @param   pVCpu       The cross context virtual CPU structure.
    412412 * @param   uErr        The trap error code.
    413  * @param   pRegFrame   Trap register frame.
     413 * @param   pCtx        Pointer to the register context for the CPU.
    414414 * @param   pvFault     The fault address.
    415415 * @param   pfLockTaken PGM lock taken here or not (out)
    416416 */
    417 PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
     417PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)
    418418{
    419419    PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
     
    563563        rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
    564564        if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
    565             return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
     565            return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage,
    566566                                                                                 pfLockTaken, &Walk, &GstWalk));
    567567        rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
     
    569569        rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
    570570        if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
    571             return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
    572                                                                                  pfLockTaken));
     571            return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
    573572        rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
    574573#   endif
     
    713712    if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
    714713# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    715         return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
     714        return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken,
    716715                                                                             &Walk, &GstWalk));
    717716# else
    718         return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
     717        return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
    719718# endif
    720719
     
    740739               our shadow page tables. (Required for e.g. Solaris guests; soft
    741740               ecc, random nr generator.) */
    742             rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
     741            rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
    743742            LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
    744743            STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
     
    836835
    837836                /* Interpret the access. */
    838                 rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
     837                rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
    839838                Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
    840839                if (RT_SUCCESS(rc))
     
    979978     */
    980979    LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
    981             __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
     980            __PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip));
    982981    return rc;
    983982
    984983# else  /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE.   */
    985     NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
     984    NOREF(uErr); NOREF(pCtx); NOREF(pvFault);
    986985    AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
    987986    return VERR_PGM_NOT_USED_IN_MODE;
     
    997996 * @param   pVCpu               The cross context virtual CPU structure.
    998997 * @param   uErr                The error code.
    999  * @param   pRegFrame           The register frame.
     998 * @param   pCtx                Pointer to the register context for the CPU.
    1000999 * @param   GCPhysNestedFault   The nested-guest physical address of the fault.
    10011000 * @param   pPage               The guest page at @a GCPhysNestedFault.
     
    10071006 * @note    The caller has taken the PGM lock.
    10081007 */
    1009 static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
     1008static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
    10101009                                                                      RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
    10111010                                                                      RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
     
    10941093        if (pCurType->fKeepPgmLock)
    10951094        {
    1096             rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, GCPhysNestedFault, GCPhysFault, uUser);
     1095            rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
    10971096            STAM_PROFILE_STOP(&pCur->Stat, h);
    10981097        }
     
    11011100            PGM_UNLOCK(pVM);
    11021101            *pfLockTaken = false;
    1103             rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, GCPhysNestedFault, GCPhysFault, uUser);
     1102            rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
    11041103            STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
    11051104        }
     
    11151114
    11161115#  else
    1117     RT_NOREF8(pVCpu, uErr, pRegFrame, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
     1116    RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
    11181117    AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
    11191118    return VERR_PGM_NOT_USED_IN_MODE;
     
    11301129 * @param   pVCpu               The cross context virtual CPU structure.
    11311130 * @param   uErr                The fault error (X86_TRAP_PF_*).
    1132  * @param   pRegFrame           The register frame.
     1131 * @param   pCtx                Pointer to the register context for the CPU.
    11331132 * @param   GCPhysNestedFault   The nested-guest physical address of the fault.
    11341133 * @param   fIsLinearAddrValid  Whether translation of a nested-guest linear address
     
    11401139 *                              when this function completes.
    11411140 */
    1142 PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNestedFault,
     1141PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
    11431142                                       bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
    11441143{
     
    11651164    if (fIsLinearAddrValid)
    11661165        Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n",
    1167                   pRegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
     1166                  pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
    11681167    else
    11691168        Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n",
    1170                   pRegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedFault, uErr));
     1169                  pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr));
    11711170    PGMPTWALKGST GstWalkAll;
    11721171    int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
     
    12581257    {
    12591258        Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
    1260         return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, GCPhysNestedFault,
     1259        return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault,
    12611260                                                                                   pPage, pWalk->GCPhys, &GstWalkAll,
    12621261                                                                                   pfLockTaken));
     
    13231322         */
    13241323        Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
    1325                   pRegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
     1324                  pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
    13261325        rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
    13271326        if (RT_SUCCESS(rc))
     
    13371336     */
    13381337    LogRelFunc(("GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n", rc, GCPhysNestedFault, GCPhysPage,
    1339                 (uint32_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
     1338                (uint32_t)uErr, pCtx->cs.Sel, pCtx->rip));
    13401339    return VERR_PGM_MAPPING_IPE;
    13411340
    13421341# else
    1343     RT_NOREF7(pVCpu, uErr, pRegFrame, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
     1342    RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
    13441343    AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
    13451344    return VERR_PGM_NOT_USED_IN_MODE;
  • trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

    r97193 r97197  
    200200 * @remarks The @a uUser argument is the PGMROMRANGE::GCPhys value.
    201201 */
    202 DECLCALLBACK(VBOXSTRICTRC) pgmPhysRomWritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
     202DECLCALLBACK(VBOXSTRICTRC) pgmPhysRomWritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
    203203                                                    RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
    204204
     
    234234                     * adding this kind of detection to DIS or EM. */
    235235                    case OP_MOV:
    236                         pRegFrame->rip += cbOp;
     236                        pCtx->rip += cbOp;
    237237                        STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZGuestROMWriteHandled);
    238238                        return VINF_SUCCESS;
     
    435435 * @remarks The @a uUser is the MMIO2 index.
    436436 */
    437 DECLCALLBACK(VBOXSTRICTRC) pgmPhysMmio2WritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
     437DECLCALLBACK(VBOXSTRICTRC) pgmPhysMmio2WritePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
    438438                                                      RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
    439439{
    440     RT_NOREF(pVCpu, uErrorCode, pRegFrame);
     440    RT_NOREF(pVCpu, uErrorCode, pCtx);
    441441    VBOXSTRICTRC rcStrict = PGM_LOCK(pVM); /* We should already have it, but just make sure we do. */
    442442    if (RT_SUCCESS(rcStrict))
  • trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h

    r97196 r97197  
    68536853    }
    68546854
    6855     PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
    68566855    int rc = vmxHCImportGuestState<HMVMX_CPUMCTX_EXTRN_ALL>(pVCpu, pVmxTransient->pVmcsInfo, __FUNCTION__);
    68576856    AssertRCReturn(rc, rc);
    68586857
    6859     Log4Func(("#PF: cs:rip=%#04x:%08RX64 err_code=%#RX32 exit_qual=%#RX64 cr3=%#RX64\n", pCtx->cs.Sel, pCtx->rip,
    6860               pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual, pCtx->cr3));
     6858    Log4Func(("#PF: cs:rip=%#04x:%08RX64 err_code=%#RX32 exit_qual=%#RX64 cr3=%#RX64\n", pVCpu->cpum.GstCtx.cs.Sel,
     6859              pVCpu->cpum.GstCtx.rip, pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual, pVCpu->cpum.GstCtx.cr3));
    68616860
    68626861    TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
    6863     rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);
     6862    rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, &pVCpu->cpum.GstCtx, (RTGCPTR)pVmxTransient->uExitQual);
    68646863
    68656864    Log4Func(("#PF: rc=%Rrc\n", rc));
     
    92869285         */
    92879286        PVMCC    pVM  = pVCpu->CTX_SUFF(pVM);
    9288         PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
    92899287/** @todo bird: We can probably just go straight to IOM here and assume that
    92909288 *        it's MMIO, then fall back on PGM if that hunch didn't work out so
     
    92969294 *        updating and use a bit more carefully first (or do all updates via
    92979295 *        rendezvous) */
    9298         rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
    9299         Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pCtx->rip, VBOXSTRICTRC_VAL(rcStrict)));
     9296        rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, &pVCpu->cpum.GstCtx, GCPhys, UINT32_MAX);
     9297        Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict)));
    93009298        if (   rcStrict == VINF_SUCCESS
    93019299            || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r97196 r97197  
    75707570     */
    75717571    /** @todo Decode assist.  */
    7572     VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
     7572    VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu);
    75737573    Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
    75747574    if (RT_LIKELY(rc == VINF_SUCCESS))
     
    79497949        {
    79507950
    7951             rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
    7952                                                      u32ErrCode);
     7951            rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, pCtx, GCPhysFaultAddr, u32ErrCode);
    79537952
    79547953            /*
     
    82938292
    82948293    TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
    8295     int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
     8294    int rc = PGMTrap0eHandler(pVCpu, uErrCode, pCtx, (RTGCPTR)uFaultAddress);
    82968295
    82978296    Log4Func(("#PF: rc=%Rrc\n", rc));
     
    91139112           instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
    91149113           instruction itself, see @bugref{7243#c126} */
    9115         rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
     9114        rcStrict = IEMExecOneBypassEx(pVCpu, NULL /* pcbWritten */);
    91169115    }
    91179116    STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
  • trunk/src/VBox/VMM/VMMR0/PGMR0.cpp

    r96979 r97197  
    12791279 *                              EMT.
    12801280 * @param   enmShwPagingMode    Paging mode for the nested page tables.
    1281  * @param   pRegFrame           Trap register frame.
     1281 * @param   pCtx                Pointer to the register context for the CPU.
    12821282 * @param   GCPhysFault         The fault address.
    12831283 * @param   uErr                The error code, UINT32_MAX if not available
     
    12851285 */
    12861286VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
    1287                                                       PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr)
     1287                                                      PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr)
    12881288{
    12891289#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
     
    13301330
    13311331                    Log6(("PGMR0Trap0eHandlerNPMisconfig: calling %p(,%#x,,%RGp,%p)\n", pHandlerType->pfnPfHandler, uErr, GCPhysFault, uUser));
    1332                     rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, pRegFrame,
     1332                    rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, pCtx,
    13331333                                                    GCPhysFault, GCPhysFault, uUser);
    13341334
  • trunk/src/VBox/VMM/include/PGMInternal.h

    r97145 r97197  
    27972797    DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
    27982798#ifndef IN_RING3
    2799     DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
    2800     DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNested,
     2799    DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
     2800    DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
    28012801                                                    bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
    28022802                                                    bool *pfLockTaken));
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