- Timestamp:
- Oct 18, 2022 10:42:52 AM (2 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
-
include/VBox/vmm/dbgf.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/DBGFAllBp.cpp (modified) (11 diffs)
-
src/VBox/VMM/VMMAll/IEMAllCImpl.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h (modified) (5 diffs)
-
src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/dbgf.h
r96407 r97196 1127 1127 VMM_INT_DECL(VBOXSTRICTRC) DBGFEventGenericWithArgs(PVM pVM, PVMCPU pVCpu, DBGFEVENTTYPE enmEvent, DBGFEVENTCTX enmCtx, 1128 1128 unsigned cArgs, ...); 1129 VMM_INT_DECL(int) DBGFTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX CORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping);1130 VMM_INT_DECL(VBOXSTRICTRC) DBGFTrap03Handler(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX CORE pRegFrame);1129 VMM_INT_DECL(int) DBGFTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCUINTREG uDr6, bool fAltStepping); 1130 VMM_INT_DECL(VBOXSTRICTRC) DBGFTrap03Handler(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx); 1131 1131 1132 1132 -
trunk/src/VBox/VMM/VMMAll/DBGFAllBp.cpp
r96407 r97196 154 154 * @param pVM The cross context VM structure. 155 155 * @param pVCpu The cross context virtual CPU structure. 156 * @param p RegFrame Pointer to the register frame for the trap.156 * @param pCtx Pointer to the register context for the CPU. 157 157 * @param hBp The breakpoint handle which hit. 158 158 * @param pBp The shared breakpoint state. … … 160 160 */ 161 161 #ifdef IN_RING0 162 DECLINLINE(int) dbgfBpHit(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX CORE pRegFrame, DBGFBP hBp, PDBGFBPINT pBp, PDBGFBPINTR0 pBpR0)163 #else 164 DECLINLINE(int) dbgfBpHit(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX CORE pRegFrame, DBGFBP hBp, PDBGFBPINT pBp)162 DECLINLINE(int) dbgfBpHit(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, DBGFBP hBp, PDBGFBPINT pBp, PDBGFBPINTR0 pBpR0) 163 #else 164 DECLINLINE(int) dbgfBpHit(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, DBGFBP hBp, PDBGFBPINT pBp) 165 165 #endif 166 166 { 167 167 uint64_t cHits = ASMAtomicIncU64(&pBp->Pub.cHits); RT_NOREF(cHits); 168 168 169 RT_NOREF(pRegFrame); 170 LogFlow(("dbgfBpHit: hit breakpoint %u at %04x:%RGv cHits=0x%RX64\n", 171 hBp, pRegFrame->cs.Sel, pRegFrame->rip, cHits)); 169 RT_NOREF(pCtx); 170 LogFlow(("dbgfBpHit: hit breakpoint %u at %04x:%RGv cHits=0x%RX64\n", hBp, pCtx->cs.Sel, pCtx->rip, cHits)); 172 171 173 172 int rc = VINF_EM_DBG_BREAKPOINT; … … 335 334 * @param pVM The cross context VM structure. 336 335 * @param pVCpu The cross context virtual CPU structure. 337 * @param p RegFrame Pointer to the register frame for the trap.336 * @param pCtx Pointer to the register context for the CPU. 338 337 * @param idxL2Root L2 table index of the table root. 339 338 * @param GCPtrKey The key to search for. 340 339 */ 341 static int dbgfBpL2Walk(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, 342 uint32_t idxL2Root, RTGCUINTPTR GCPtrKey) 340 static int dbgfBpL2Walk(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, uint32_t idxL2Root, RTGCUINTPTR GCPtrKey) 343 341 { 344 342 /** @todo We don't use the depth right now but abort the walking after a fixed amount of levels. */ … … 369 367 && DBGF_BP_PUB_GET_TYPE(&pBp->Pub) == DBGFBPTYPE_INT3) 370 368 #ifdef IN_RING3 371 return dbgfBpHit(pVM, pVCpu, p RegFrame, hBp, pBp);372 #else 373 return dbgfBpHit(pVM, pVCpu, p RegFrame, hBp, pBp, pBpR0);369 return dbgfBpHit(pVM, pVCpu, pCtx, hBp, pBp); 370 #else 371 return dbgfBpHit(pVM, pVCpu, pCtx, hBp, pBp, pBpR0); 374 372 #endif 375 373 … … 483 481 * @param pVM The cross context VM structure. 484 482 * @param pVCpu The cross context virtual CPU structure. 485 * @param p RegFrame Pointer to the register frame for the trap.483 * @param pCtx Pointer to the register context for the CPU. 486 484 * @param uDr6 The DR6 hypervisor register value. 487 485 * @param fAltStepping Alternative stepping indicator. 488 486 */ 489 VMM_INT_DECL(int) DBGFTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX CORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping)487 VMM_INT_DECL(int) DBGFTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCUINTREG uDr6, bool fAltStepping) 490 488 { 491 489 /** @todo Intel docs say that X86_DR6_BS has the highest priority... */ 492 RT_NOREF(p RegFrame);490 RT_NOREF(pCtx); 493 491 494 492 /* … … 506 504 pVCpu->dbgf.s.fSingleSteppingRaw = false; 507 505 LogFlow(("DBGFRZTrap03Handler: hit hw breakpoint %x at %04x:%RGv\n", 508 pVM->dbgf.s.aHwBreakpoints[iBp].hBp, p RegFrame->cs.Sel, pRegFrame->rip));506 pVM->dbgf.s.aHwBreakpoints[iBp].hBp, pCtx->cs.Sel, pCtx->rip)); 509 507 510 508 return VINF_EM_DBG_BREAKPOINT; … … 520 518 { 521 519 pVCpu->dbgf.s.fSingleSteppingRaw = false; 522 LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", p RegFrame->cs.Sel, pRegFrame->rip));520 LogFlow(("DBGFRZTrap01Handler: single step at %04x:%RGv\n", pCtx->cs.Sel, pCtx->rip)); 523 521 return VINF_EM_DBG_STEPPED; 524 522 } 525 523 526 LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, p RegFrame->cs.Sel, pRegFrame->rip));524 LogFlow(("DBGFRZTrap01Handler: guest debug event %#x at %04x:%RGv!\n", (uint32_t)uDr6, pCtx->cs.Sel, pCtx->rip)); 527 525 return VINF_EM_RAW_GUEST_TRAP; 528 526 } … … 538 536 * @param pVM The cross context VM structure. 539 537 * @param pVCpu The cross context virtual CPU structure. 540 * @param p RegFrame Pointer to the register frame for the trap.541 */ 542 VMM_INT_DECL(VBOXSTRICTRC) DBGFTrap03Handler(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX CORE pRegFrame)538 * @param pCtx Pointer to the register context for the CPU. 539 */ 540 VMM_INT_DECL(VBOXSTRICTRC) DBGFTrap03Handler(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx) 543 541 { 544 542 #if defined(IN_RING0) … … 553 551 { 554 552 RTGCPTR GCPtrBp; 555 int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs, 556 pRegFrame->rip /* no -1 in R0 */, 557 &GCPtrBp); 553 int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtx->eflags, pCtx->ss.Sel, pCtx->cs.Sel, &pCtx->cs, 554 pCtx->rip /* no -1 outside non-rawmode */, &GCPtrBp); 558 555 AssertRCReturn(rc, rc); 559 556 … … 581 578 if (pBp->Pub.u.Int3.GCPtr == (RTGCUINTPTR)GCPtrBp) 582 579 #ifdef IN_RING3 583 rc = dbgfBpHit(pVM, pVCpu, p RegFrame, hBp, pBp);584 #else 585 rc = dbgfBpHit(pVM, pVCpu, p RegFrame, hBp, pBp, pBpR0);580 rc = dbgfBpHit(pVM, pVCpu, pCtx, hBp, pBp); 581 #else 582 rc = dbgfBpHit(pVM, pVCpu, pCtx, hBp, pBp, pBpR0); 586 583 #endif 587 584 else … … 592 589 } 593 590 else if (u8Type == DBGF_BP_INT3_L1_ENTRY_TYPE_L2_IDX) 594 rc = dbgfBpL2Walk(pVM, pVCpu, p RegFrame, DBGF_BP_INT3_L1_ENTRY_GET_L2_IDX(u32L1Entry),591 rc = dbgfBpL2Walk(pVM, pVCpu, pCtx, DBGF_BP_INT3_L1_ENTRY_GET_L2_IDX(u32L1Entry), 595 592 DBGF_BP_INT3_L2_KEY_EXTRACT_FROM_ADDR((RTGCUINTPTR)GCPtrBp)); 596 593 else /* Some invalid type. */ -
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
r97183 r97196 2898 2898 else 2899 2899 { 2900 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx));2900 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVM, pVCpu, &pVCpu->cpum.GstCtx); 2901 2901 Log(("iemCImpl_int: DBGFTrap03Handler -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) )); 2902 2902 if (rcStrict != VINF_EM_RAW_GUEST_TRAP) -
trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r97188 r97196 6953 6953 VBOXSTRICTRC rcStrict; 6954 6954 if (!pVmxTransient->fIsNestedGuest) 6955 rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx));6955 rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx); 6956 6956 else 6957 6957 rcStrict = VINF_EM_RAW_GUEST_TRAP; … … 7100 7100 7101 7101 int rc; 7102 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;7103 7102 if (!pVmxTransient->fIsNestedGuest) 7104 7103 { 7105 rc = DBGFTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), uDR6, VCPU_2_VMXSTATE(pVCpu).fSingleInstruction);7104 rc = DBGFTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx, uDR6, VCPU_2_VMXSTATE(pVCpu).fSingleInstruction); 7106 7105 7107 7106 /* … … 7131 7130 HM_DISABLE_PREEMPT(pVCpu); 7132 7131 7133 p Ctx->dr[6] &= ~X86_DR6_B_MASK;7134 p Ctx->dr[6] |= uDR6;7132 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK; 7133 pVCpu->cpum.GstCtx.dr[6] |= uDR6; 7135 7134 if (CPUMIsGuestDebugStateActive(pVCpu)) 7136 ASMSetDR6(p Ctx->dr[6]);7135 ASMSetDR6(pVCpu->cpum.GstCtx.dr[6]); 7137 7136 7138 7137 HM_RESTORE_PREEMPT(); … … 7146 7145 7147 7146 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */ 7148 p Ctx->dr[7] &= ~(uint64_t)X86_DR7_GD;7147 pVCpu->cpum.GstCtx.dr[7] &= ~(uint64_t)X86_DR7_GD; 7149 7148 7150 7149 /* Paranoia. */ 7151 p Ctx->dr[7] &= ~(uint64_t)X86_DR7_RAZ_MASK;7152 p Ctx->dr[7] |= X86_DR7_RA1_MASK;7153 7154 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_DR7, p Ctx->dr[7]);7150 pVCpu->cpum.GstCtx.dr[7] &= ~(uint64_t)X86_DR7_RAZ_MASK; 7151 pVCpu->cpum.GstCtx.dr[7] |= X86_DR7_RA1_MASK; 7152 7153 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_DR7, pVCpu->cpum.GstCtx.dr[7]); 7155 7154 AssertRC(rc); 7156 7155 … … 7167 7166 */ 7168 7167 vmxHCSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 7169 pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);7168 pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */); 7170 7169 return VINF_SUCCESS; 7171 7170 } -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r97193 r97196 8556 8556 * handler expects. See AMD spec. 15.12.2 "#DB (Debug)". 8557 8557 */ 8558 PVMCC pVM = pVCpu->CTX_SUFF(pVM);8558 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 8559 8559 PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; 8560 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 8561 int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction); 8560 int rc = DBGFTrap01Handler(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction); 8562 8561 if (rc == VINF_EM_RAW_GUEST_TRAP) 8563 8562 { … … 8622 8621 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); 8623 8622 8624 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 8625 VBOXSTRICTRC rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx)); 8623 VBOXSTRICTRC rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx); 8626 8624 if (rc == VINF_EM_RAW_GUEST_TRAP) 8627 8625 {
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