Changeset 96653 in vbox
- Timestamp:
- Sep 8, 2022 8:51:37 AM (2 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r96538 r96653 2835 2835 %endif 2836 2836 2837 ; 2838 ; [V]PCLMULQDQ 2839 ; 2840 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM1, XMM2, 0FFh 2841 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM1, FSxBX, 0FFh 2842 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM1, XMM2, 000h 2843 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM1, FSxBX, 000h 2844 2845 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM1, XMM2, XMM3, 0FFh 2846 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM1, XMM2, FSxBX, 0FFh 2847 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM1, XMM2, XMM3, 000h 2848 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM1, XMM2, FSxBX, 000h 2849 2850 %if TMPL_BITS == 64 2851 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM8, XMM9, 0FFh 2852 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM8, FSxBX, 0FFh 2853 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM8, XMM9, 000h 2854 EMIT_INSTR_PLUS_ICEBP pclmulqdq, XMM8, FSxBX, 000h 2855 2856 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM8, XMM9, XMM10, 0FFh 2857 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM8, XMM9, FSxBX, 0FFh 2858 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM8, XMM9, XMM10, 000h 2859 EMIT_INSTR_PLUS_ICEBP vpclmulqdq, XMM8, XMM9, FSxBX, 000h 2860 %endif 2861 2837 2862 2838 2863 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r96649 r96653 81 81 T_SSE4_2, 82 82 T_SSE4A, 83 T_PCLMUL, 83 84 T_AVX_128, 84 85 T_AVX2_128, 86 T_AVX_PCLMUL, 85 87 T_AVX_256, 86 88 T_256BITS = T_AVX_256, … … 7393 7395 { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7394 7396 { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7397 }; 7398 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 7399 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 7400 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 7401 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 7402 } 7403 7404 7405 /* 7406 * [V]PCLMULQDQ - Carry-less multiplication of a quadword. 7407 */ 7408 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp); 7409 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp); 7410 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp); 7411 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp); 7412 extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_XMM9_0FFh_icebp_c64; 7413 extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_0FFh_icebp_c64; 7414 extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_XMM9_000h_icebp_c64; 7415 extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_000h_icebp_c64; 7416 7417 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp); 7418 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp); 7419 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp); 7420 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp); 7421 extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_0FFh_icebp_c64; 7422 extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_0FFh_icebp_c64; 7423 extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64; 7424 extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64; 7425 7426 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pclmulqdq(uint8_t bMode) 7427 { 7428 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = 7429 { 7430 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 7431 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 7432 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 7433 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7434 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 7435 /* => */ RTUINT256_INIT_C( 1, 2, 0x6541a5056544a512, 0x6753a7176756a740) }, 7436 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7437 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7438 /* => */ RTUINT256_INIT_C( 5, 6, 0x5fb1fa02ce11d9e9, 0x547462ca50871166) }, 7439 }; 7440 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = 7441 { 7442 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 7443 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 7444 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 7445 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7446 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 7447 /* => */ RTUINT256_INIT_C( 9, 10, 0x6041a0056044a012, 0x6253a2176256a240) }, 7448 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7449 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7450 /* => */ RTUINT256_INIT_C( 13, 14, 0x26d2ea34453fe24f, 0x2592f499ed1f651f) }, 7451 }; 7452 7453 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 7454 { 7455 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7456 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7457 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7458 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7459 7460 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7461 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7462 7463 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7464 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7465 }; 7466 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 7467 { 7468 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7469 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7470 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7471 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7472 7473 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7474 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7475 7476 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7477 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7478 }; 7479 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 7480 { 7481 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7482 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7483 { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7484 { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7485 7486 { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7487 { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7488 { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7489 { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7490 7491 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7492 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7493 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7494 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 7495 7496 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7497 { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7498 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7499 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7395 7500 }; 7396 7501 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 11436 11541 { "[v]blendpd", bs3CpuInstr3_v_blendpd, 0 }, 11437 11542 #endif 11543 #if defined(ALL_TESTS) 11544 { "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 }, 11545 #endif 11438 11546 }; 11439 11547 Bs3TestInit("bs3-cpu-instr-3"); … … 11456 11564 g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1); 11457 11565 g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2); 11566 g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL); 11458 11567 g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); 11459 11568 g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); 11569 g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL) 11570 && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); 11460 11571 11461 11572 if (ASMCpuId_EAX(0) >= 7)
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