Changeset 96439 in vbox

Timestamp:

Aug 23, 2022 1:16:46 PM (2 years ago)

Author:

vboxsync

Message:

ValidationKit/bs3-cpu-instr-3: Add simple [v]phminposuw instructions testcases, ​bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -2585 +2585 @@
  %endif
 
+;
+; [V]PHMINPOSUW
+;
+EMIT_INSTR_PLUS_ICEBP phminposuw,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP phminposuw,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vphminposuw, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP vphminposuw, XMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP phminposuw,  XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP phminposuw,  XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vphminposuw, XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP vphminposuw, XMM9, FSxBX
+ %endif
+
 %endif ; BS3_INSTANTIATING_CMN
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -9656 +9656 @@
     return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
+}
+
+
+/*
+ * [V]PHMINPOSUW
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_phminposuw_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_phminposuw_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vphminposuw_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vphminposuw_XMM9_FSxBX_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phminposuw(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] =
+    {
+        {            RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {            RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ RTUINT256_INIT_C(1, 2, 0x0000000000000000, 0x000000000000ffff) }, /* No 256-bit variant */
+        {            RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
+            /* => */ RTUINT256_INIT_C(5, 6, 0x0000000000000000, 0x0000000000071111) }, /* No 256-bit variant */
+        {            RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /* => */ RTUINT256_INIT_C(9, 10, 0x0000000000000000, 0x0000000000062fa8) }, /* No 256-bit variant */
+    };
+
+    static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_SSE4_1,    1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c16,  255,         RM_MEM, T_SSE4_1,    1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_SSE4_1,    1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c32,  255,         RM_MEM, T_SSE4_1,    1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_SSE4_1,    1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c64,  255,         RM_MEM, T_SSE4_1,    1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_phminposuw_XMM9_XMM8_icebp_c64,   255,         RM_REG, T_SSE4_1,    9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_phminposuw_XMM9_FSxBX_icebp_c64,  255,         RM_MEM, T_SSE4_1,    9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,   9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vphminposuw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
 }
 
@@ -10122 +10180 @@
         { "[v]lddqu",                                       bs3CpuInstr3_v_lddqu, 0 },
 #endif
+#if defined(ALL_TESTS)
+        { "[v]phminposuw",                                  bs3CpuInstr3_v_phminposuw, 0 },
+#endif
     };
     Bs3TestInit("bs3-cpu-instr-3");