Changeset 94051 in vbox
- Timestamp:
- Mar 2, 2022 5:00:49 AM (3 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
-
IEMAllCImpl.cpp.h (modified) (3 diffs)
-
IEMAllCImplVmxInstr.cpp.h (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
r93922 r94051 2757 2757 2758 2758 /** @todo Should probe write access at the new RSP according to AMD. */ 2759 /** @todo Should handle accesses to the VMX APIC-access page. */ 2759 2760 2760 2761 /* Commit it. */ … … 7560 7561 * See Intel spec. 29.4.4 "Instruction-Specific Considerations". 7561 7562 */ 7562 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);7563 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA); 7563 7564 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE 7564 7565 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR) … … 8218 8219 * See Intel spec. 29.4.4 "Instruction-Specific Considerations". 8219 8220 */ 8220 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);8221 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA); 8221 8222 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE 8222 8223 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR) -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
r93922 r94051 181 181 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending) 182 182 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?) 183 * VMX_EXIT_INVEPT184 183 * VMX_EXIT_RDRAND 185 184 * VMX_EXIT_VMFUNC … … 2465 2464 pVmcs->u64RoExitQual.u = u64ExitQual; 2466 2465 2467 Log 3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,2468 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,2469 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));2466 LogFlow(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason, 2467 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0, 2468 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4)); 2470 2469 2471 2470 /* … … 4302 4301 4303 4302 /** 4304 * Virtualizes a memory-based APIC access where the address is not used to access4305 * memory.4303 * Virtualizes a memory-based APIC access by certain instructions even though they 4304 * do not use the address to access memory. 4306 4305 * 4307 4306 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause … … 4310 4309 * @param pVCpu The cross context virtual CPU structure. 4311 4310 * @param pGCPhysAccess Pointer to the guest-physical address accessed. 4311 * @param cbAccess The size of the access in bytes. 4312 4312 * @param fAccess The type of access, see IEM_ACCESS_XXX. 4313 4313 */ 4314 IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, uint32_t fAccess) 4314 IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, 4315 uint32_t fAccess) 4315 4316 { 4316 4317 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); … … 4324 4325 { 4325 4326 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK; 4326 uint16_t const cbAccess = 1;4327 4327 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess); 4328 4328 if (fIntercept) … … 7641 7641 # if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3) 7642 7642 /* Reschedule to IEM-only execution of the nested-guest. */ 7643 Log (("%s: Enabling IEM-only EM execution policy!\n", pszInstr));7643 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr)); 7644 7644 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); 7645 7645 if (rcSched != VINF_SUCCESS) … … 7648 7648 7649 7649 /* Finally, done. */ 7650 Log 3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",7651 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,7652 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,7653 pVCpu->cpum.GstCtx.msrEFER));7650 LogFlow(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n", 7651 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0, 7652 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u, 7653 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u)); 7654 7654 return VINF_SUCCESS; 7655 7655 }
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