Changeset 93290 in vbox
- Timestamp:
- Jan 18, 2022 5:31:29 AM (3 years ago)
- Location:
- trunk
- Files:
-
- 2 edited
-
include/VBox/vmm/cpum.h (modified) (1 diff)
-
src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.h
r93213 r93290 1495 1495 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu); 1496 1496 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu); 1497 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu);1498 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPU pVCpu);1497 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu); 1498 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu); 1499 1499 VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue); 1500 1500 VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue); -
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r93115 r93290 312 312 * @param pVCpu The cross context per CPU structure. 313 313 */ 314 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu)314 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu) 315 315 { 316 316 /* We do not support dual-monitor treatment for SMI and SMM. */ … … 1336 1336 { 1337 1337 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1338 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic; 1338 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1339 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic; 1340 else 1341 *puValue = 0; 1339 1342 return VINF_SUCCESS; 1340 1343 } … … 1345 1348 { 1346 1349 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1347 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.PinCtls.u; 1350 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1351 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.PinCtls.u; 1352 else 1353 *puValue = 0; 1348 1354 return VINF_SUCCESS; 1349 1355 } … … 1353 1359 { 1354 1360 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1355 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls.u; 1361 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1362 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls.u; 1363 else 1364 *puValue = 0; 1356 1365 return VINF_SUCCESS; 1357 1366 } … … 1362 1371 { 1363 1372 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1364 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ExitCtls.u; 1373 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1374 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ExitCtls.u; 1375 else 1376 *puValue = 0; 1365 1377 return VINF_SUCCESS; 1366 1378 } … … 1371 1383 { 1372 1384 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1373 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.EntryCtls.u; 1385 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1386 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.EntryCtls.u; 1387 else 1388 *puValue = 0; 1374 1389 return VINF_SUCCESS; 1375 1390 } … … 1381 1396 { 1382 1397 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1383 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Misc; 1398 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1399 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Misc; 1400 else 1401 *puValue = 0; 1384 1402 return VINF_SUCCESS; 1385 1403 } … … 1399 1417 { 1400 1418 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1401 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed1; 1419 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1420 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr0Fixed1; 1421 else 1422 *puValue = 0; 1402 1423 return VINF_SUCCESS; 1403 1424 } … … 1408 1429 { 1409 1430 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1410 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed0; 1431 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1432 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed0; 1433 else 1434 *puValue = 0; 1411 1435 return VINF_SUCCESS; 1412 1436 } … … 1417 1441 { 1418 1442 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1419 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed1; 1443 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1444 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Cr4Fixed1; 1445 else 1446 *puValue = 0; 1420 1447 return VINF_SUCCESS; 1421 1448 } … … 1426 1453 { 1427 1454 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1428 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmcsEnum; 1455 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1456 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmcsEnum; 1457 else 1458 *puValue = 0; 1429 1459 return VINF_SUCCESS; 1430 1460 } … … 1435 1465 { 1436 1466 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1437 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls2.u; 1467 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1468 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.ProcCtls2.u; 1469 else 1470 *puValue = 0; 1438 1471 return VINF_SUCCESS; 1439 1472 } … … 1446 1479 * @param pVCpu The cross context per CPU structure. 1447 1480 */ 1448 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPU pVCpu) 1449 { 1450 RT_NOREF_PV(pVCpu); 1451 return pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64EptVpidCaps; 1481 VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu) 1482 { 1483 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1484 return pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64EptVpidCaps; 1485 return 0; 1452 1486 } 1453 1487 … … 1456 1490 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1457 1491 { 1458 RT_NOREF_PV( pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);1492 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1459 1493 *puValue = CPUMGetGuestIa32VmxEptVpidCap(pVCpu); 1460 1494 return VINF_SUCCESS; … … 1465 1499 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1466 1500 { 1467 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1468 *puValue = 0; 1501 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1502 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1503 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TruePinCtls.u; 1504 else 1505 *puValue = 0; 1469 1506 return VINF_SUCCESS; 1470 1507 } … … 1474 1511 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1475 1512 { 1476 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1477 *puValue = 0; 1513 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1514 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1515 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueProcCtls.u; 1516 else 1517 *puValue = 0; 1478 1518 return VINF_SUCCESS; 1479 1519 } … … 1483 1523 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1484 1524 { 1485 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1486 *puValue = 0; 1525 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1526 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1527 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueExitCtls.u; 1528 else 1529 *puValue = 0; 1487 1530 return VINF_SUCCESS; 1488 1531 } … … 1492 1535 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1493 1536 { 1494 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1495 *puValue = 0; 1537 RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1538 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1539 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.TrueEntryCtls.u; 1540 else 1541 *puValue = 0; 1496 1542 return VINF_SUCCESS; 1497 1543 } … … 1502 1548 { 1503 1549 RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); 1504 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc; 1550 if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx) 1551 *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64VmFunc; 1552 else 1553 *puValue = 0; 1505 1554 return VINF_SUCCESS; 1506 1555 }
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