- Timestamp:
- Oct 25, 2021 4:05:10 PM (3 years ago)
- Location:
- trunk
- Files:
-
- 7 edited
-
include/VBox/vmm/hm_vmx.h (modified) (5 diffs)
-
src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
-
src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (4 diffs)
-
src/VBox/VMM/VMMAll/PGMAllGst.h (modified) (2 diffs)
-
src/VBox/VMM/VMMR3/PGM.cpp (modified) (2 diffs)
-
src/VBox/VMM/include/PGMGstDefs.h (modified) (5 diffs)
-
src/VBox/VMM/include/PGMInternal.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/hm_vmx.h
r91971 r92046 415 415 * The memory type is only applicable for leaf entries and MBZ for 416 416 * non-leaf (causes miconfiguration exit). */ 417 #define EPT_E_ TYPE_MASKUINT64_C(0x0038)417 #define EPT_E_MEMTYPE_MASK UINT64_C(0x0038) 418 418 /** Bits 3-5 - Memory type shifted mask. */ 419 #define EPT_E_ TYPE_SMASKUINT64_C(0x0007)419 #define EPT_E_MEMTYPE_SMASK UINT64_C(0x0007) 420 420 /** Bits 3-5 - Memory type shift count. */ 421 #define EPT_E_ TYPE_SHIFT3421 #define EPT_E_MEMTYPE_SHIFT 3 422 422 /** Bits 3-5 - Memory type: UC. */ 423 #define EPT_E_ TYPE_UC (UINT64_C(0) << EPT_E_TYPE_SHIFT)423 #define EPT_E_MEMTYPE_UC (UINT64_C(0) << EPT_E_MEMTYPE_SHIFT) 424 424 /** Bits 3-5 - Memory type: WC. */ 425 #define EPT_E_ TYPE_WC (UINT64_C(1) << EPT_E_TYPE_SHIFT)425 #define EPT_E_MEMTYPE_WC (UINT64_C(1) << EPT_E_MEMTYPE_SHIFT) 426 426 /** Bits 3-5 - Memory type: Invalid (2). */ 427 #define EPT_E_ TYPE_INVALID_2 (UINT64_C(2) << EPT_E_TYPE_SHIFT)427 #define EPT_E_MEMTYPE_INVALID_2 (UINT64_C(2) << EPT_E_MEMTYPE_SHIFT) 428 428 /** Bits 3-5 - Memory type: Invalid (3). */ 429 #define EPT_E_ TYPE_INVALID_3 (UINT64_C(3) << EPT_E_TYPE_SHIFT)429 #define EPT_E_MEMTYPE_INVALID_3 (UINT64_C(3) << EPT_E_MEMTYPE_SHIFT) 430 430 /** Bits 3-5 - Memory type: WT. */ 431 #define EPT_E_ TYPE_WT (UINT64_C(4) << EPT_E_TYPE_SHIFT)431 #define EPT_E_MEMTYPE_WT (UINT64_C(4) << EPT_E_MEMTYPE_SHIFT) 432 432 /** Bits 3-5 - Memory type: WP. */ 433 #define EPT_E_ TYPE_WP (UINT64_C(5) << EPT_E_TYPE_SHIFT)433 #define EPT_E_MEMTYPE_WP (UINT64_C(5) << EPT_E_MEMTYPE_SHIFT) 434 434 /** Bits 3-5 - Memory type: WB. */ 435 #define EPT_E_ TYPE_WB (UINT64_C(6) << EPT_E_TYPE_SHIFT)435 #define EPT_E_MEMTYPE_WB (UINT64_C(6) << EPT_E_MEMTYPE_SHIFT) 436 436 /** Bits 3-5 - Memory type: Invalid (7). */ 437 #define EPT_E_ TYPE_INVALID_7 (UINT64_C(7) << EPT_E_TYPE_SHIFT)437 #define EPT_E_MEMTYPE_INVALID_7 (UINT64_C(7) << EPT_E_MEMTYPE_SHIFT) 438 438 439 439 /** Bit 6 - Ignore page attribute table (leaf, MBZ). */ … … 468 468 /* Bit 61, 62 are always ignored at time of writing. */ 469 469 470 /** Bit 63 - Sup ress \#VE (leaf only, ignored).470 /** Bit 63 - Suppress \#VE (leaf only, ignored). 471 471 * @note Ignored if EPT violation to \#VE conversion is disabled. */ 472 #define EPT_E_BIT_IGNORE_VE 63 473 #define EPT_E_IGNORE_VE RT_BIT_64(EPT_E_BIT_IGNORE_VE) /**< @see EPT_E_BIT_IGNORE_VE*/ 472 #define EPT_E_BIT_SUPPRESS_VE 63 473 #define EPT_E_SUPPRESS_VE RT_BIT_64(EPT_E_BIT_SUPPRESS_VE) /**< @see EPT_E_BIT_SUPPRESS_VE*/ 474 /** @} */ 475 476 477 /**@name Bit fields for common EPT attributes. 478 @{ */ 479 /** Read access. */ 480 #define VMX_BF_EPT_PT_READ_SHIFT 0 481 #define VMX_BF_EPT_PT_READ_MASK UINT64_C(0x0000000000000001) 482 /** Write access. */ 483 #define VMX_BF_EPT_PT_WRITE_SHIFT 1 484 #define VMX_BF_EPT_PT_WRITE_MASK UINT64_C(0x0000000000000002) 485 /** Execute access or execute access for supervisor-mode linear-addresses. */ 486 #define VMX_BF_EPT_PT_EXECUTE_SHIFT 2 487 #define VMX_BF_EPT_PT_EXECUTE_MASK UINT64_C(0x0000000000000004) 488 /** EPT memory type. */ 489 #define VMX_BF_EPT_PT_MEMTYPE_SHIFT 3 490 #define VMX_BF_EPT_PT_MEMTYPE_MASK UINT64_C(0x0000000000000038) 491 /** Ignore PAT. */ 492 #define VMX_BF_EPT_PT_IGNORE_PAT_SHIFT 6 493 #define VMX_BF_EPT_PT_IGNORE_PAT_MASK UINT64_C(0x0000000000000040) 494 /** Ignored (bit 7). */ 495 #define VMX_BF_EPT_PT_IGN_7_SHIFT 7 496 #define VMX_BF_EPT_PT_IGN_7_MASK UINT64_C(0x0000000000000080) 497 /** Accessed flag. */ 498 #define VMX_BF_EPT_PT_ACCESSED_SHIFT 8 499 #define VMX_BF_EPT_PT_ACCESSED_MASK UINT64_C(0x0000000000000100) 500 /** Dirty flag. */ 501 #define VMX_BF_EPT_PT_DIRTY_SHIFT 9 502 #define VMX_BF_EPT_PT_DIRTY_MASK UINT64_C(0x0000000000000200) 503 /** Execute access for user-mode linear addresses. */ 504 #define VMX_BF_EPT_PT_EXECUTE_USER_SHIFT 10 505 #define VMX_BF_EPT_PT_EXECUTE_USER_MASK UINT64_C(0x0000000000000400) 506 /** Ignored (bit 59:11). */ 507 #define VMX_BF_EPT_PT_IGN_59_11_SHIFT 11 508 #define VMX_BF_EPT_PT_IGN_59_11_MASK UINT64_C(0x0ffffffffffff800) 509 /** Supervisor shadow stack. */ 510 #define VMX_BF_EPT_PT_SUPER_SHW_STACK_SHIFT 60 511 #define VMX_BF_EPT_PT_SUPER_SHW_STACK_MASK UINT64_C(0x1000000000000000) 512 /** Ignored (bits 62:61). */ 513 #define VMX_BF_EPT_PT_IGN_62_61_SHIFT 61 514 #define VMX_BF_EPT_PT_IGN_62_61_MASK UINT64_C(0x6000000000000000) 515 /** Suppress \#VE. */ 516 #define VMX_BF_EPT_PT_SUPPRESS_VE_SHIFT 63 517 #define VMX_BF_EPT_PT_SUPPRESS_VE_MASK UINT64_C(0x8000000000000000) 518 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_PT_, UINT64_C(0), UINT64_MAX, 519 (READ, WRITE, EXECUTE, MEMTYPE, IGNORE_PAT, IGN_7, ACCESSED, DIRTY, EXECUTE_USER, IGN_59_11, 520 SUPER_SHW_STACK, IGN_62_61, SUPPRESS_VE)); 474 521 /** @} */ 475 522 … … 582 629 AssertCompileSize(EPTPDPTEBITS, 8); 583 630 631 /** Bit 7 - - EPT - PDPTE maps a 1GB page. */ 632 #define EPT_PDPTE1G_SIZE_MASK RT_BIT_64(7) 584 633 /** Bits 12-51 - - EPT - Physical Page number of the next level. */ 585 #define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK 634 #define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK 635 /** Bits 12-51 - - EPT - Physical Page number of the next level. */ 636 #define EPT_PDPTE1G_PG_MASK X86_PDPE_PG_MASK 637 586 638 /** The page shift to get the PDPT index. */ 587 #define EPT_PDPT_SHIFT X86_PDPT_SHIFT639 #define EPT_PDPT_SHIFT X86_PDPT_SHIFT 588 640 /** The PDPT index mask (apply to a shifted page address). */ 589 #define EPT_PDPT_MASK X86_PDPT_MASK_AMD64641 #define EPT_PDPT_MASK X86_PDPT_MASK_AMD64 590 642 /** Bits 3-7 - - EPT - PDPTE MBZ Mask. */ 591 #define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8)643 #define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8) 592 644 /** Bits 12-29 - - EPT - 1GB PDPTE MBZ Mask. */ 593 #define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000) 645 #define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000) 646 /** Mask of all possible EPT PDPTE (1GB) attribute bits. */ 647 #define EPT_PDPTE1G_ATTR_MASK ( EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT \ 648 | EPT_E_ACCESSED | EPT_E_DIRTY | EPT_E_USER_EXECUTE) 649 /** Mask of all possible EPT PDPTE attribute bits. */ 650 #define EPT_PDPTE_ATTR_MASK (EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_ACCESSED | EPT_E_USER_EXECUTE) 594 651 /** */ 595 652 … … 665 722 /** Bits 3-7 - EPT - PDE MBZ Mask. */ 666 723 #define EPT_PDE_MBZ_MASK UINT64_C(0x00000000000000f8) 667 668 724 669 725 … … 819 875 typedef const EPTPT *PCEPTPT; 820 876 877 /** EPTP page mask for the EPT PML4 table. */ 878 #define EPT_EPTP_PG_MASK X86_CR3_AMD64_PAGE_MASK 821 879 /** @} */ 822 880 -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r91989 r92046 2399 2399 PGM_LOCK_VOID(pVM); 2400 2400 2401 RTGCPHYS const GCPhys CR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_EPT_PAGE_MASK;2401 RTGCPHYS const GCPhysEpt = pVCpu->pgm.s.uEptPtr & EPT_EPTP_PG_MASK; 2402 2402 PPGMPAGE pPage; 2403 int rc = pgmPhysGetPageEx(pVM, GCPhys CR3, &pPage);2403 int rc = pgmPhysGetPageEx(pVM, GCPhysEpt, &pPage); 2404 2404 if (RT_SUCCESS(rc)) 2405 2405 { 2406 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys CR3, (void **)ppEptPml4);2406 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysEpt, (void **)ppEptPml4); 2407 2407 if (RT_SUCCESS(rc)) 2408 2408 { -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r91854 r92046 1382 1382 LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage)); 1383 1383 # if PGM_SHW_TYPE == PGM_TYPE_EPT 1384 pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) | EPT_E_READ | EPT_E_EXECUTE | EPT_E_ TYPE_WB | EPT_E_IGNORE_PAT;1384 pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) | EPT_E_READ | EPT_E_EXECUTE | EPT_E_MEMTYPE_WB | EPT_E_IGNORE_PAT; 1385 1385 # else 1386 1386 if (fPteSrc & X86_PTE_A) … … 1410 1410 | EPT_E_WRITE 1411 1411 /* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */ 1412 | EPT_E_ TYPE_INVALID_3;1412 | EPT_E_MEMTYPE_INVALID_3; 1413 1413 # else 1414 1414 /* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */ … … 1568 1568 # if PGM_SHW_TYPE == PGM_TYPE_EPT 1569 1569 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) 1570 | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_ TYPE_WB | EPT_E_IGNORE_PAT;1570 | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_MEMTYPE_WB | EPT_E_IGNORE_PAT; 1571 1571 # else 1572 1572 SHW_PTE_SET(PteDst, fGstShwPteFlags | PGM_PAGE_GET_HCPHYS(pPage)); … … 2905 2905 { 2906 2906 # if PGM_SHW_TYPE == PGM_TYPE_EPT 2907 PdeDst.u = HCPhys | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_LEAF | EPT_E_IGNORE_PAT | EPT_E_ TYPE_WB2907 PdeDst.u = HCPhys | EPT_E_READ | EPT_E_WRITE | EPT_E_EXECUTE | EPT_E_LEAF | EPT_E_IGNORE_PAT | EPT_E_MEMTYPE_WB 2908 2908 | (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */; 2909 2909 # else -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r91993 r92046 186 186 187 187 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt); 188 uint32_t const fEffectiveEpt = ((uint32_t)Pml4e.u & EPT_PML4E_ATTR_MASK) << PGMPTWALK_EFF_EPT_ATTR_SHIFT; 189 uint8_t const fExecute = RT_BF_GET(fEffectiveEpt, PGM_BF_PTWALK_EFF_X_SUPER); 190 uint8_t const fWrite = RT_BF_GET(fEffectiveEpt, PGM_BF_PTWALK_EFF_W); 191 uint8_t const fAccessed = RT_BF_GET(fEffectiveEpt, PGM_BF_PTWALK_EFF_A); 188 uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK; 189 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE); 190 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ); 191 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE); 192 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED); 193 uint32_t const fEffectiveEpt = ((uint32_t)fEptAttrs << PGMPTWALK_EFF_EPT_ATTR_SHIFT) & PGMPTWALK_EFF_EPT_ATTR_MASK; 192 194 pWalk->Core.fEffective = fEffective = RT_BF_MAKE(PGM_BF_PTWALK_EFF_X, fExecute) 193 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_RW, f Write)195 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_RW, fRead & fWrite) 194 196 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_US, 1) 195 197 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_A, fAccessed) … … 233 235 if (RT_SUCCESS(rc)) { /* probable */ } 234 236 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc); 237 238 # elif PGM_GST_TYPE == PGM_TYPE_EPT 239 PEPTPDPTE pPdpte; 240 pWalk->pPdpte = pPdpte = &pWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK]; 241 EPTPDPTE Pdpte; 242 pWalk->Pdpte.u = Pdpte.u = pPdpte->u; 243 244 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ } 245 else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3); 246 247 /* The order of the following 2 "if" statements matter. */ 248 if (GST_IS_PDPE_VALID(pVCpu, Pdpte)) 249 { 250 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK; 251 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE); 252 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE); 253 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED); 254 uint32_t const fEffectiveEpt = ((uint32_t)fEptAttrs << PGMPTWALK_EFF_EPT_ATTR_SHIFT) & PGMPTWALK_EFF_EPT_ATTR_MASK; 255 fEffective &= RT_BF_MAKE(PGM_BF_PTWALK_EFF_X, fExecute) 256 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_RW, fWrite) 257 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_US, 1) 258 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_A, fAccessed) 259 | fEffectiveEpt; 260 pWalk->Core.fEffective = fEffective; 261 } 262 else if (GST_IS_BIG_PDPE_VALID(pVCpu, Pdpte)) 263 { 264 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK; 265 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE); 266 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE); 267 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED); 268 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY); 269 uint16_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE); 270 uint16_t const fIgnorePat = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_IGNORE_PAT); 271 uint32_t const fEffectiveEpt = ((uint32_t)fEptAttrs << PGMPTWALK_EFF_EPT_ATTR_SHIFT) & PGMPTWALK_EFF_EPT_ATTR_MASK; 272 fEffective &= RT_BF_MAKE(PGM_BF_PTWALK_EFF_X, fExecute) 273 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_RW, fWrite) 274 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_US, 1) 275 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_A, fAccessed) 276 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_D, fDirty) 277 | fEffectiveEpt; 278 fEffective |= RT_BF_MAKE(PGM_BF_PTWALK_EFF_MEMTYPE, fMemType) 279 | RT_BF_MAKE(PGM_BF_PTWALK_EFF_IGNORE_PAT, fIgnorePat); 280 281 pWalk->Core.fEffective = fEffective; 282 pWalk->Core.fEffectiveRW = RT_BOOL(fEffective & X86_PTE_RW); 283 pWalk->Core.fEffectiveUS = RT_BOOL(fEffective & X86_PTE_US); 284 pWalk->Core.fEffectiveNX = !fExecute; 285 pWalk->Core.fBigPage = false; 286 pWalk->Core.fGigantPage = true; 287 pWalk->Core.fSucceeded = true; 288 pWalk->Core.GCPhys = GST_GET_BIG_PDPE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pdpte) 289 | (GCPtr & GST_GIGANT_PAGE_OFFSET_MASK); 290 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->Core.GCPhys); 291 return VINF_SUCCESS; 292 } 293 else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3); 235 294 # endif 236 295 } -
trunk/src/VBox/VMM/VMMR3/PGM.cpp
r91939 r92046 1569 1569 */ 1570 1570 uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000); 1571 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT 1572 uint64_t const fEptVpidCap = CPUMGetGuestIa32VmxEptVpidCap(pVM->apCpusR3[0]); /* should be identical for all VCPUs. */ 1573 uint64_t const fGstEptMbzBigPdeMask = EPT_PDE2M_MBZ_MASK 1574 | (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDE_2M) ^ 1) << EPT_E_BIT_LEAF; 1575 uint64_t const fGstEptMbzBigPdpteMask = EPT_PDPTE1G_MBZ_MASK 1576 | (RT_BF_GET(fEptVpidCap, VMX_BF_EPT_VPID_CAP_PDPTE_1G) ^ 1) << EPT_E_BIT_LEAF; 1577 #endif 1571 1578 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) 1572 1579 { … … 1602 1609 pVCpu->pgm.s.fGstEptMbzPteMask = fMbzPageFrameMask | EPT_PTE_MBZ_MASK; 1603 1610 pVCpu->pgm.s.fGstEptMbzPdeMask = fMbzPageFrameMask | EPT_PDE_MBZ_MASK; 1604 pVCpu->pgm.s.fGstEptMbzBigPdeMask = fMbzPageFrameMask | EPT_PDE2M_MBZ_MASK;1605 pVCpu->pgm.s.fGstEptMbzPdp eMask= fMbzPageFrameMask | EPT_PDPTE_MBZ_MASK;1606 pVCpu->pgm.s.fGstEptMbzBigPdp eMask = fMbzPageFrameMask | EPT_PDPTE1G_MBZ_MASK;1611 pVCpu->pgm.s.fGstEptMbzBigPdeMask = fMbzPageFrameMask | fGstEptMbzBigPdeMask; 1612 pVCpu->pgm.s.fGstEptMbzPdpteMask = fMbzPageFrameMask | EPT_PDPTE_MBZ_MASK; 1613 pVCpu->pgm.s.fGstEptMbzBigPdpteMask = fMbzPageFrameMask | fGstEptMbzBigPdpteMask; 1607 1614 pVCpu->pgm.s.fGstEptMbzPml4eMask = fMbzPageFrameMask | EPT_PML4E_MBZ_MASK; 1608 1615 -
trunk/src/VBox/VMM/include/PGMGstDefs.h
r91904 r92046 35 35 #undef GST_BIG_PAGE_SIZE 36 36 #undef GST_BIG_PAGE_OFFSET_MASK 37 #undef GST_GIGANT_PAGE_SIZE 38 #undef GST_GIGANT_PAGE_OFFSET_MASK 39 #undef GST_PDPE_BIG_PG_MASK 37 40 #undef GST_PDE_PG_MASK 38 41 #undef GST_PDE_BIG_PG_MASK … … 51 54 #undef GST_GET_PDE_GCPHYS 52 55 #undef GST_GET_BIG_PDE_GCPHYS 56 #undef GST_GET_BIG_PDPE_GCPHYS 53 57 #undef GST_GET_PDE_SHW_FLAGS 54 58 #undef GST_GET_BIG_PDE_SHW_FLAGS … … 249 253 # define GSTPDE EPTPDE 250 254 # define PGSTPDE PEPTPDE 255 # define GST_GIGANT_PAGE_SIZE X86_PAGE_1G_SIZE 256 # define GST_GIGANT_PAGE_OFFSET_MASK X86_PAGE_1G_OFFSET_MASK 257 # define GST_PDPE_BIG_PG_MASK X86_PDPE1G_PG_MASK 251 258 # define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE 252 259 # define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK … … 269 276 # define GST_GET_PDE_GCPHYS(Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDE_PG_MASK)) 270 277 # define GST_GET_BIG_PDE_GCPHYS(pVM, Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDE_BIG_PG_MASK)) 278 # define GST_GET_BIG_PDPE_GCPHYS(pVM, Pde) PGM_A20_APPLY(pVCpu, ((Pde).u & GST_PDPE_BIG_PG_MASK)) 271 279 # define GST_GET_PTE_SHW_FLAGS(pVCpu, Pte) ((Pte).u & (pVCpu)->pgm.s.fGst64ShadowedPteMask ) // TODO 272 280 # define GST_GET_PDE_SHW_FLAGS(pVCpu, Pde) ((Pde).u & (pVCpu)->pgm.s.fGst64ShadowedPdeMask ) // TODO … … 276 284 # define GST_IS_PDE_VALID(pVCpu, Pde) (!( (Pde).u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask )) // TODO 277 285 # define GST_IS_BIG_PDE_VALID(pVCpu, Pde) (!( (Pde).u & (pVCpu)->pgm.s.fGstAmd64MbzBigPdeMask )) // TODO 278 # define GST_IS_PDPE_VALID(pVCpu, Pdpe) (!( (Pdpe).u & (pVCpu)->pgm.s.fGst Amd64MbzPdpeMask )) // TODO279 # define GST_IS_BIG_PDPE_VALID(pVCpu, Pdpe) (!( (Pdpe).u & (pVCpu)->pgm.s.fGst Amd64MbzBigPdpeMask )) // TODO286 # define GST_IS_PDPE_VALID(pVCpu, Pdpe) (!( (Pdpe).u & (pVCpu)->pgm.s.fGstEptMbzPdpteMask )) 287 # define GST_IS_BIG_PDPE_VALID(pVCpu, Pdpe) (!( (Pdpe).u & (pVCpu)->pgm.s.fGstEptMbzBigPdpteMask )) 280 288 # define GST_IS_PML4E_VALID(pVCpu, Pml4e) (!( (Pml4e).u & (pVCpu)->pgm.s.fGstEptMbzPml4eMask )) 281 289 # define GST_IS_PGENTRY_PRESENT(pVCpu, Entry) (!( (Entry).u & (pVCpu)->pgm.s.fGstEptPresentMask )) -
trunk/src/VBox/VMM/include/PGMInternal.h
r91990 r92046 2413 2413 #define PGM_BF_PTWALK_EFF_X_SUPER_SHIFT 14 2414 2414 #define PGM_BF_PTWALK_EFF_X_SUPER_MASK UINT32_C(0x00004000) 2415 /** Reserved (bits 21:15) unused. */ 2416 #define PGM_BF_PTWALK_EFF_RSVD_21_15_SHIFT 15 2417 #define PGM_BF_PTWALK_EFF_RSVD_21_15_MASK UINT32_C(0x003f8000) 2415 /** Effective EPT memory type - EPT only. */ 2416 #define PGM_BF_PTWALK_EFF_MEMTYPE_SHIFT 15 2417 #define PGM_BF_PTWALK_EFF_MEMTYPE_MASK UINT32_C(0x00038000) 2418 /** Effective ignore PAT memory type - EPT only. */ 2419 #define PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT 18 2420 #define PGM_BF_PTWALK_EFF_IGNORE_PAT_MASK UINT32_C(0x00040000) 2421 /** Reserved (bits 21:19) unused. */ 2422 #define PGM_BF_PTWALK_EFF_RSVD_21_19_SHIFT 19 2423 #define PGM_BF_PTWALK_EFF_RSVD_21_19_MASK UINT32_C(0x00380000) 2418 2424 /** Effective execute access for user-mode - EPT only. */ 2419 2425 #define PGM_BF_PTWALK_EFF_X_USER_SHIFT 22 2420 2426 #define PGM_BF_PTWALK_EFF_X_USER_MASK UINT32_C(0x00400000) 2421 /** Reserved (bits 31:23) . */2427 /** Reserved (bits 31:23) - unused. */ /** @todo When implementing SUPER_SHW_STACK, Suppress \#VE put them in bits 24, 25 which corresponds to bit 12, 13 of EPT attributes. */ 2422 2428 #define PGM_BF_PTWALK_EFF_RSVD_31_23_SHIFT 23 2423 2429 #define PGM_BF_PTWALK_EFF_RSVD_31_23_MASK UINT32_C(0xff800000) 2430 RT_BF_ASSERT_COMPILE_CHECKS(PGM_BF_PTWALK_EFF_, UINT32_C(0), UINT32_MAX, 2431 (X, RW, US, PWT, PCD, A, D, PAT, G, RSVD_11_9, R, W, X_SUPER, MEMTYPE, IGNORE_PAT, RSVD_21_19, 2432 X_USER, RSVD_31_23)); 2424 2433 2425 2434 /** The bit count where the EPT specific bits begin. */ 2426 2435 #define PGMPTWALK_EFF_EPT_ATTR_SHIFT PGM_BF_PTWALK_EFF_R_SHIFT 2427 2428 RT_BF_ASSERT_COMPILE_CHECKS(PGM_BF_PTWALK_EFF_, UINT32_C(0), UINT32_MAX, 2429 (X, RW, US, PWT, PCD, A, D, PAT, G, RSVD_11_9, R, W, X_SUPER, RSVD_21_15, X_USER, RSVD_31_23)); 2436 /** The mask of EPT bits (bits 31:ATTR_SHIFT). In the future we might choose to 2437 * use higher unused EPT bits for something else, in that case reduce this mask. */ 2438 #define PGMPTWALK_EFF_EPT_ATTR_MASK UINT32_C(0xfffff000) 2439 2440 /* Verify bits match the regular PT bits. */ 2430 2441 AssertCompile(PGM_BF_PTWALK_EFF_RW_SHIFT == X86_PTE_BIT_RW); 2431 2442 AssertCompile(PGM_BF_PTWALK_EFF_US_SHIFT == X86_PTE_BIT_US); … … 2435 2446 AssertCompile(PGM_BF_PTWALK_EFF_D_SHIFT == X86_PTE_BIT_D); 2436 2447 AssertCompile(PGM_BF_PTWALK_EFF_PAT_SHIFT == X86_PTE_BIT_PAT); 2437 AssertCompile(PGM_BF_PTWALK_EFF_G_SHIFT == X86_PTE_BIT_G); 2438 AssertCompile(PGM_BF_PTWALK_EFF_RW_MASK == X86_PTE_RW); 2439 AssertCompile(PGM_BF_PTWALK_EFF_US_MASK == X86_PTE_US); 2440 AssertCompile(PGM_BF_PTWALK_EFF_PWT_MASK == X86_PTE_PWT); 2441 AssertCompile(PGM_BF_PTWALK_EFF_PCD_MASK == X86_PTE_PCD); 2442 AssertCompile(PGM_BF_PTWALK_EFF_A_MASK == X86_PTE_A); 2443 AssertCompile(PGM_BF_PTWALK_EFF_D_MASK == X86_PTE_D); 2444 AssertCompile(PGM_BF_PTWALK_EFF_PAT_MASK == X86_PTE_PAT); 2445 AssertCompile(PGM_BF_PTWALK_EFF_G_MASK == X86_PTE_G); 2446 AssertCompile(PGM_BF_PTWALK_EFF_R_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_READ); 2447 AssertCompile(PGM_BF_PTWALK_EFF_W_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_WRITE); 2448 AssertCompile(PGM_BF_PTWALK_EFF_X_SUPER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_EXECUTE); 2449 AssertCompile(PGM_BF_PTWALK_EFF_X_USER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_USER_EXECUTE); 2448 AssertCompile(PGM_BF_PTWALK_EFF_G_SHIFT == X86_PTE_BIT_G); 2449 AssertCompile(PGM_BF_PTWALK_EFF_RW_MASK == X86_PTE_RW); 2450 AssertCompile(PGM_BF_PTWALK_EFF_US_MASK == X86_PTE_US); 2451 AssertCompile(PGM_BF_PTWALK_EFF_PWT_MASK == X86_PTE_PWT); 2452 AssertCompile(PGM_BF_PTWALK_EFF_PCD_MASK == X86_PTE_PCD); 2453 AssertCompile(PGM_BF_PTWALK_EFF_A_MASK == X86_PTE_A); 2454 AssertCompile(PGM_BF_PTWALK_EFF_D_MASK == X86_PTE_D); 2455 AssertCompile(PGM_BF_PTWALK_EFF_PAT_MASK == X86_PTE_PAT); 2456 AssertCompile(PGM_BF_PTWALK_EFF_G_MASK == X86_PTE_G); 2457 2458 /* 2459 * The following bits map 1:1 (left shifted by PGMPTWALK_EFF_EPT_ATTR_SHIFT bits) with 2460 * VMX EPT attribute bits because these are unique to EPT and fit within 32-bits: 2461 * - R, W, X_SUPER, MEMTYPE, IGNORE_PAT, X_USER. 2462 * 2463 * The following bits are moved to the regular PT bit positions because they already 2464 * exist for regular page tables: 2465 * - A, D. 2466 */ 2467 AssertCompile(PGM_BF_PTWALK_EFF_R_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_READ); 2468 AssertCompile(PGM_BF_PTWALK_EFF_W_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_WRITE); 2469 AssertCompile(PGM_BF_PTWALK_EFF_X_SUPER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_EXECUTE); 2470 AssertCompile(PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_IGNORE_PAT); 2471 AssertCompile(PGM_BF_PTWALK_EFF_X_USER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_USER_EXECUTE); 2450 2472 /** @} */ 2451 2473 … … 3578 3600 /** The guest's page directory pointer table, R0 pointer. */ 3579 3601 R0PTRTYPE(PEPTPML4) pGstEptPml4R0; 3580 /** The guest's EPT pointer . */3602 /** The guest's EPT pointer (copy of virtual VMCS). */ 3581 3603 uint64_t uEptPtr; 3582 3604 /** Mask containing the MBZ PTE bits. */ … … 3584 3606 /** Mask containing the MBZ PDE bits. */ 3585 3607 uint64_t fGstEptMbzPdeMask; 3586 /** Mask containing the MBZ big page PDE bits. */3608 /** Mask containing the MBZ big page (2M) PDE bits. */ 3587 3609 uint64_t fGstEptMbzBigPdeMask; 3588 /** Mask containing the MBZ PDP E bits. */3589 uint64_t fGstEptMbzPdp eMask;3590 /** Mask containing the MBZ big page PDPE bits. */3591 uint64_t fGstEptMbzBigPdp eMask;3610 /** Mask containing the MBZ PDPTE bits. */ 3611 uint64_t fGstEptMbzPdpteMask; 3612 /** Mask containing the MBZ big page (1G) PDPTE bits. */ 3613 uint64_t fGstEptMbzBigPdpteMask; 3592 3614 /** Mask containing the MBZ PML4E bits. */ 3593 3615 uint64_t fGstEptMbzPml4eMask;
Note:
See TracChangeset
for help on using the changeset viewer.

