- Timestamp:
- Jun 16, 2021 5:43:38 AM (3 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (3 diffs)
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trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r89726 r89727 1409 1409 #ifdef RT_STRICT 1410 1410 { 1411 P DMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);1411 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR); 1412 1412 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG); 1413 1413 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK … … 2173 2173 Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK)); 2174 2174 2175 /* Mask of valid paging entry bits. */2176 static uint64_t const s_auPtEntity Rsvd[] = {VTD_SL_PTE_VALID_MASK,2177 VTD_SL_PDE_VALID_MASK,2178 VTD_SL_PDPE_VALID_MASK,2179 VTD_SL_PML4E_VALID_MASK,2180 VTD_SL_PML5E_VALID_MASK };2175 /* Mask of reserved paging entry bits. */ 2176 static uint64_t const s_auPtEntityInvMasks[] = { ~VTD_SL_PTE_VALID_MASK, 2177 ~VTD_SL_PDE_VALID_MASK, 2178 ~VTD_SL_PDPE_VALID_MASK, 2179 ~VTD_SL_PML4E_VALID_MASK, 2180 ~VTD_SL_PML5E_VALID_MASK }; 2181 2181 2182 2182 /* Paranoia. */ 2183 2183 Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5); 2184 AssertCompile(RT_ELEMENTS(s_auPtEntity Rsvd) == 5);2184 AssertCompile(RT_ELEMENTS(s_auPtEntityInvMasks) == 5); 2185 2185 2186 2186 /* Second-level translations restricts input address to an implementation-specific MGAW. */ … … 2242 2242 * Validate reserved bits of the current paging entry. 2243 2243 */ 2244 if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))2244 if (!(uPtEntity & s_auPtEntityInvMasks[idxLevel])) 2245 2245 { /* likely */ } 2246 2246 else
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