VirtualBox

Changeset 89668 in vbox for trunk


Ignore:
Timestamp:
Jun 14, 2021 7:57:12 AM (3 years ago)
Author:
vboxsync
Message:

Intel IOMMU: bugref:9967 Should be enough to save just IVA_REG and FRCD_LO_REG offsets since the other two are adjacent registers (defined by the spec).

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

    r89667 r89668  
    110110/** Size of the group 0 (in bytes). */
    111111#define DMAR_MMIO_GROUP_0_SIZE                      (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
    112 /** Number of MMIO register offsets defined by our implementation (for saved
    113  *  states) - IVA_REG, IOTLB_REG, FRCD_LO, FRCD_HI. */
    114 #define DMAR_MMIO_OFF_IMPL_COUNT                    4
     112/** Number of implementation-defined MMIO register offsets - IVA_REG and
     113 *  FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from
     114 *  IVA_REG and FRCD_LO_REG respectively */
     115#define DMAR_MMIO_OFF_IMPL_COUNT                    2
    115116/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
    116117#define DMAR_MMIO_OFF_IVA_REG                       0xe50
    117 /** Implementation-specific MMIO offset of IOTLB_REG (used in saved state). */
     118/** Implementation-specific MMIO offset of IOTLB_REG. */
    118119#define DMAR_MMIO_OFF_IOTLB_REG                     0xe58
    119120/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
    120121#define DMAR_MMIO_OFF_FRCD_LO_REG                   0xe70
    121 /** Implementation-specific MMIO offset of FRCD_HI_REG (used in saved state). */
     122/** Implementation-specific MMIO offset of FRCD_HI_REG. */
    122123#define DMAR_MMIO_OFF_FRCD_HI_REG                   0xe78
    123124AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
     
    39563957     */
    39573958    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
    3958     AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 4);
     3959    AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2);
    39593960    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
    3960     pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IOTLB_REG);
    39613961    pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
    3962     pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_HI_REG);
    39633962
    39643963    /* Save lazily activated registers. */
     
    40624061                               offReg), rcFmtErr);
    40634062        /* IOTLB_REG. */
    4064         pHlp->pfnSSMGetU16(pSSM, &offReg);
    4065         AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IOTLB_REG,
     4063        AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG,
    40664064                              ("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
    40674065                               offReg), rcFmtErr);
     
    40724070                               offReg), rcFmtErr);
    40734071        /* FRCD_HI_REG. */
    4074         pHlp->pfnSSMGetU16(pSSM, &offReg);
    4075         AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_HI_REG,
     4072        AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG,
    40764073                              ("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
    40774074                               offReg), rcFmtErr);
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