- Timestamp:
- Jun 14, 2021 7:57:12 AM (3 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (4 diffs)
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trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r89667 r89668 110 110 /** Size of the group 0 (in bytes). */ 111 111 #define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST) 112 /** Number of MMIO register offsets defined by our implementation (for saved 113 * states) - IVA_REG, IOTLB_REG, FRCD_LO, FRCD_HI. */ 114 #define DMAR_MMIO_OFF_IMPL_COUNT 4 112 /** Number of implementation-defined MMIO register offsets - IVA_REG and 113 * FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from 114 * IVA_REG and FRCD_LO_REG respectively */ 115 #define DMAR_MMIO_OFF_IMPL_COUNT 2 115 116 /** Implementation-specific MMIO offset of IVA_REG (used in saved state). */ 116 117 #define DMAR_MMIO_OFF_IVA_REG 0xe50 117 /** Implementation-specific MMIO offset of IOTLB_REG (used in saved state). */118 /** Implementation-specific MMIO offset of IOTLB_REG. */ 118 119 #define DMAR_MMIO_OFF_IOTLB_REG 0xe58 119 120 /** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */ 120 121 #define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70 121 /** Implementation-specific MMIO offset of FRCD_HI_REG (used in saved state). */122 /** Implementation-specific MMIO offset of FRCD_HI_REG. */ 122 123 #define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78 123 124 AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf)); … … 3956 3957 */ 3957 3958 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT); 3958 AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 4);3959 AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2); 3959 3960 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG); 3960 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IOTLB_REG);3961 3961 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG); 3962 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_HI_REG);3963 3962 3964 3963 /* Save lazily activated registers. */ … … 4062 4061 offReg), rcFmtErr); 4063 4062 /* IOTLB_REG. */ 4064 pHlp->pfnSSMGetU16(pSSM, &offReg); 4065 AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IOTLB_REG, 4063 AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG, 4066 4064 ("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG, 4067 4065 offReg), rcFmtErr); … … 4072 4070 offReg), rcFmtErr); 4073 4071 /* FRCD_HI_REG. */ 4074 pHlp->pfnSSMGetU16(pSSM, &offReg); 4075 AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_HI_REG, 4072 AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG, 4076 4073 ("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG, 4077 4074 offReg), rcFmtErr);
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