Index: /trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp	(revision 88534)
+++ /trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp	(revision 88535)
@@ -60,5 +60,5 @@
  *  minimum number of registers (which is 1).
  *
- *  See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
+ *  See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
 #define DMAR_FRCD_REG_COUNT                         UINT32_C(1)
 
@@ -90,8 +90,12 @@
 #define DMAR_MMIO_GROUP_1_SIZE                      (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
 
+/** DMAR implementation's major version number (exposed to software).
+ *  We report 6 as the major version since we support queued invalidations as
+ *  software may make assumptions based on that.
+ *
+ *  See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
+#define DMAR_VER_MAJOR                              6
 /** DMAR implementation's minor version number (exposed to software). */
 #define DMAR_VER_MINOR                              0
-/** DMAR implementation's major version number (exposed to software). */
-#define DMAR_VER_MAJOR                              1
 /** @} */
 
@@ -125,4 +129,8 @@
     /** @name Register copies for a tiny bit faster and more convenient access.
      *  @{ */
+    /** Copy of VER_REG. */
+    uint8_t                     uVerReg;
+    /** Alignment. */
+    uint8_t                     abPadding[7];
     /** Copy of CAP_REG. */
     uint64_t                    fCap;
@@ -860,7 +868,7 @@
     /* VER_REG */
     {
-        uint8_t const uVer = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
-                           | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
-        dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, uVer);
+        pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
+                       | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
+        dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
     }
 
@@ -907,4 +915,5 @@
                     | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV,    fPsi & fMamv)
                     | RT_BF_MAKE(VTD_BF_CAP_REG_DWD,     1)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_DRD,     1)
                     | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP,   fFlts & fFl1gp)
                     | RT_BF_MAKE(VTD_BF_CAP_REG_PI,      0)     /* Posted Interrupts not supported. */
@@ -1122,5 +1131,5 @@
      * Log some of the features exposed to software.
      */
-    uint32_t const uVerReg         = dmarRegRead32(pThis, VTD_MMIO_OFF_VER_REG);
+    uint32_t const uVerReg         = pThis->uVerReg;
     uint8_t const  cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
     uint8_t const  cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));