Changeset 88521 in vbox

Timestamp:

Apr 15, 2021 10:56:57 AM (3 years ago)

Author:

vboxsync

Message:

Intel IOMMU: bugref:9967 Updates to adjust for changes in Oct 2020 and Apr 2021 Intel VT-d specs.

Location:

trunk

Files:

• include/VBox/iommu-intel.h (modified) (2 diffs)
• src/VBox/Devices/Bus/DevIommuIntel.cpp (modified) (6 diffs)

trunk/include/VBox/iommu-intel.h

@@ -775 +775 @@
 #define VTD_BF_CAP_REG_FL5LP_SHIFT                              60
 #define VTD_BF_CAP_REG_FL5LP_MASK                               UINT64_C(0x1000000000000000)
-/** R: Reserved (bits 63:61). */
-#define VTD_BF_CAP_REG_RSVD_63_61_SHIFT                         61
-#define VTD_BF_CAP_REG_RSVD_63_61_MASK                          UINT64_C(0xe000000000000000)
+/** R: Reserved (bit 61). */
+#define VTD_BF_CAP_REG_RSVD_61_SHIFT                            61
+#define VTD_BF_CAP_REG_RSVD_61_MASK                             UINT64_C(0x2000000000000000)
+/** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
+#define VTD_BF_CAP_REG_ESIRTPS_SHIFT                            62
+#define VTD_BF_CAP_REG_ESIRTPS_MASK                             UINT64_C(0x4000000000000000)
+/** : Enhanced Set Root Table Pointer Support. */
+#define VTD_BF_CAP_REG_ESRTPS_SHIFT                             63
+#define VTD_BF_CAP_REG_ESRTPS_MASK                              UINT64_C(0x8000000000000000)
 RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
                             (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
-                             MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_63_61));
+                             MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
 
 /** RW: Read/write mask. */
@@ -889 +895 @@
 #define VTD_BF_ECAP_REG_RPS_SHIFT                               49
 #define VTD_BF_ECAP_REG_RPS_MASK                                UINT64_C(0x0002000000000000)
-/** R: Reserved (bits 63:50). */
-#define VTD_BF_ECAP_REG_RSVD_63_50_SHIFT                        50
-#define VTD_BF_ECAP_REG_RSVD_63_50_MASK                         UINT64_C(0xfffc000000000000)
+/** R: Reserved (bits 51:50). */
+#define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT                        50
+#define VTD_BF_ECAP_REG_RSVD_51_50_MASK                         UINT64_C(0x000c000000000000)
+/** ADMS: Abort DMA Mode Support. */
+#define VTD_BF_ECAP_REG_ADMS_SHIFT                              52
+#define VTD_BF_ECAP_REG_ADMS_MASK                               UINT64_C(0x0010000000000000)
+/** RPRIVS: RID_PRIV Support. */
+#define VTD_BF_ECAP_REG_RPRIVS_SHIFT                            53
+#define VTD_BF_ECAP_REG_RPRIVS_MASK                             UINT64_C(0x0020000000000000)
+/** R: Reserved (bits 63:54). */
+#define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT                        54
+#define VTD_BF_ECAP_REG_RSVD_63_54_MASK                         UINT64_C(0xffc0000000000000)
 RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
                             (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
                              PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
-                             RSVD_63_50));
+                             RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
 
 /** RW: Read/write mask. */

trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp

@@ -868 +868 @@
     uint8_t const fSlts  = 1;                    /* Second-Level translation support. */
     uint8_t const fPt    = 1;                    /* Pass-Through support. */
+    uint8_t const fSmts  = fFlts & fSlts & fPt;  /* Scalable mode translation support.*/
     uint8_t const fNest  = 0;                    /* Nested translation support. */
-    uint8_t const fSmts  = fFlts & fSlts & fPt;  /* Scalable mode translation support.*/
 
     /* CAP_REG */
@@ -886 +886 @@
                                 X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
         uint8_t const fNd     = 2;                              /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
-                                                                  7=Reserved). */
+                                                                   7=Reserved). */
         uint8_t const fPsi    = 1;                              /* Page selective invalidation. */
         uint8_t const uMgaw   = cGstPhysAddrBits - 1;           /* Maximum guest address width. */
@@ -892 +892 @@
         uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
 
-        pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND,     fNd)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_AFL,    0)      /* Advanced fault logging not supported. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF,   0)      /* Software need not flush write-buffers. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR,   0)      /* Protected Low-Memory Region not supported. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR,   0)      /* Protected High-Memory Region not supported. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_CM,     1)      /** @todo Figure out if required when we impl. caching. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW,  fSlts & uSagaw)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW,   uMgaw)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR,    1)      /** @todo Figure out if/how to support zero-length reads. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_FRO,    offFro)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS,  fSlts & fSllps)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_PSI,    fPsi)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_NFR,    DMAR_FRCD_REG_COUNT - 1)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV,   fPsi & fMamv)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_DWD,    1)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP,  fFlts & fFl1gp)
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_PI,     0)      /* Posted Interrupts not supported. */
-                    | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP,  fFlts & fFl5lp);
+        pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND,      fNd)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_AFL,     0)     /* Advanced fault logging not supported. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF,    0)     /* Software need not flush write-buffers. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR,    0)     /* Protected Low-Memory Region not supported. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR,    0)     /* Protected High-Memory Region not supported. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_CM,      1)     /** @todo Figure out if required when we impl. caching. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW,   fSlts & uSagaw)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW,    uMgaw)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR,     1)     /** @todo Figure out if/how to support zero-length reads. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_FRO,     offFro)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS,   fSlts & fSllps)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_PSI,     fPsi)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_NFR,     DMAR_FRCD_REG_COUNT - 1)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV,    fPsi & fMamv)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_DWD,     1)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP,   fFlts & fFl1gp)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_PI,      0)     /* Posted Interrupts not supported. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP,   fFlts & fFl5lp)
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0)     /* Whether we invalidate interrupt cache on SIRTP flow. */
+                    | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS,  0);    /* Whether we invalidate translation cache on SRTP flow. */
         dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
     }
@@ -921 +923 @@
         uint8_t const  fSrs   = 1;                              /* Supervisor request support. */
         uint8_t const  fEim   = 1;                              /* Extended interrupt mode.*/
+        uint8_t const  fAdms  = 1;                              /* Abort DMA mode support. */
 
         pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C,      0)  /* Accesses don't snoop CPU cache. */
@@ -937 +940 @@
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS,    fSmts & fSrs)
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS,   0)  /* 0 as DT not supported. */
-                       | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS,   0)  /* 0 as PASID not supported. */
+                       | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS,   0)  /** @todo figure out if EAFS is required? */
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS,    0)  /* 0 as PASID not supported. */
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID,  0)  /* PASID support. */
@@ -948 +951 @@
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS,   fFlts)
                        | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0)  /* 0 as PASID not supported. */
-                       | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS,    0); /* 0 as PASID not supported. */
+                       | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS,    0)  /* We don't support RID_PASID field in SM context entry. */
+                       | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS,   fAdms)
+                       | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
         dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
     }