Index: /trunk/src/VBox/Devices/Config.kmk =================================================================== --- /trunk/src/VBox/Devices/Config.kmk (revision 86904) +++ /trunk/src/VBox/Devices/Config.kmk (revision 86905) @@ -28,10 +28,7 @@ endif -# We need the Additions/3D/Config.kmk for the VBOX_PATH_VMSVGA_INC variable. -ifndef VBOX_MESA3D_CONFIG_KMK_INCLUDED - include $(PATH_ROOT)/src/VBox/Additions/3D/Config.kmk -endif +VBOX_PATH_DEVICES_SRC := $(PATH_ROOT)/src/VBox/Devices -VBOX_PATH_DEVICES_SRC := $(PATH_ROOT)/src/VBox/Devices +VBOX_PATH_VMSVGA_DEVICE_INC := $(VBOX_PATH_DEVICES_SRC)/Graphics/vmsvga_include # Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp (revision 86905) @@ -44,41 +44,10 @@ #if defined(LOG_ENABLED) || defined(VBOX_STRICT) # define SVGA_CASE_ID2STR(idx) case idx: return #idx -/** - * FIFO command name lookup - * - * @returns FIFO command string or "UNKNOWN" - * @param u32Cmd FIFO command - */ -const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd) -{ - switch (u32Cmd) - { - SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD); - SVGA_CASE_ID2STR(SVGA_CMD_UPDATE); - SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL); - SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY); - SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY); - SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR); - SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR); - SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR); - SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR); - SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE); - SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL); - SVGA_CASE_ID2STR(SVGA_CMD_FENCE); - SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE); - SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN); - SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN); - SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB); - SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN); - SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB); - SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL); - SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY); - SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2); - SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2); - SVGA_CASE_ID2STR(SVGA_CMD_DEAD); - SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2); - SVGA_CASE_ID2STR(SVGA_CMD_NOP); - SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR); - SVGA_CASE_ID2STR(SVGA_CMD_MAX); + +static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId) +{ + switch (enmCmdId) + { + SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE); SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE); SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY); @@ -113,12 +82,12 @@ SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2); SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_DECODER); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_DECODER); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_START_FRAME); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_RENDER); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_DECODE_END_FRAME); - SVGA_CASE_ID2STR(SVGA_3D_CMD_VIDEO_PROCESS_FRAME); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */ SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE); SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE); @@ -126,10 +95,10 @@ SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD1); SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND); - SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */ + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */ SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE); SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE); @@ -221,5 +190,5 @@ SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION); SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY); - SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_STRETCHBLT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT); SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS); SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE); @@ -264,11 +233,108 @@ SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET); SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET); - SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED1); - SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED2); - SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESERVED3); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET); SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER); - SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MAX); - default: return "UNKNOWN"; - } + SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8); + SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND); + SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3); + SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT); + SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS); + SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE); + SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX); + SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX); + } + return "UNKNOWN_3D"; +} + +/** + * FIFO command name lookup + * + * @returns FIFO command string or "UNKNOWN" + * @param u32Cmd FIFO command + */ +const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd) +{ + switch (u32Cmd) + { + SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD); + SVGA_CASE_ID2STR(SVGA_CMD_UPDATE); + SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL); + SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY); + SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY); + SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR); + SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR); + SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR); + SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR); + SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE); + SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL); + SVGA_CASE_ID2STR(SVGA_CMD_FENCE); + SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE); + SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN); + SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN); + SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB); + SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN); + SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB); + SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL); + SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY); + SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2); + SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2); + SVGA_CASE_ID2STR(SVGA_CMD_DEAD); + SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2); + SVGA_CASE_ID2STR(SVGA_CMD_NOP); + SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR); + SVGA_CASE_ID2STR(SVGA_CMD_MAX); + default: + if ( u32Cmd >= SVGA_3D_CMD_BASE + && u32Cmd < SVGA_3D_CMD_MAX) + return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd); + } + return "UNKNOWN"; } # undef SVGA_CASE_ID2STR @@ -1071,5 +1137,5 @@ RT_ZERO(entry); entry.format = pCmd->format; - entry.surfaceFlags = pCmd->surfaceFlags; + entry.surface1Flags = pCmd->surfaceFlags; entry.numMipLevels = pCmd->numMipLevels; entry.multisampleCount = pCmd->multisampleCount; @@ -2002,13 +2068,13 @@ -/* SVGA_3D_CMD_DX_STRETCHBLT 1180 */ -static void vmsvga3dCmdDXStretchBlt(PVGASTATECC pThisCC, SVGA3dCmdDXStretchBlt const *pCmd) -{ -ASMBreakpoint(); - PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; - if (pSvgaR3State->pFuncsDX) - { - RT_NOREF(pCmd); - pSvgaR3State->pFuncsDX->pfnDXStretchBlt(pThisCC->svga.p3dState); +/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */ +static void vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, SVGA3dCmdDXPresentBlt const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXPresentBlt(pThisCC->svga.p3dState); } } @@ -2561,4 +2627,43 @@ +/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */ +static void vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetHSConstantBufferOffset(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */ +static void vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetDSConstantBufferOffset(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */ +static void vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetCSConstantBufferOffset(pThisCC->svga.p3dState); + } +} + + /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */ static void vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, SVGA3dCmdDXCondBindAllShader const *pCmd) @@ -2570,4 +2675,511 @@ RT_NOREF(pCmd); pSvgaR3State->pFuncsDX->pfnDXCondBindAllShader(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_SCREEN_COPY 1227 */ +static void vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, SVGA3dCmdScreenCopy const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnScreenCopy(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_GROW_OTABLE 1236 */ +static void vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnGrowOTable(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */ +static void vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXGrowCOTable(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */ +static void vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdIntraSurfaceCopy const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnIntraSurfaceCopy(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */ +static void vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v3(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */ +static void vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXResolveCopy const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXResolveCopy(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */ +static void vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, SVGA3dCmdDXPredResolveCopy const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXPredResolveCopy(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */ +static void vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvertRegion const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXPredConvertRegion(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */ +static void vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, SVGA3dCmdDXPredConvert const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXPredConvert(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */ +static void vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, SVGA3dCmdWholeSurfaceCopy const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnWholeSurfaceCopy(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */ +static void vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDefineUAView const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDefineUAView(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */ +static void vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyUAView const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDestroyUAView(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */ +static void vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewUint const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXClearUAViewUint(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */ +static void vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, SVGA3dCmdDXClearUAViewFloat const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXClearUAViewFloat(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */ +static void vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXCopyStructureCount const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXCopyStructureCount(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */ +static void vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetUAViews const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetUAViews(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */ +static void vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstancedIndirect(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */ +static void vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDrawInstancedIndirect const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDrawInstancedIndirect(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DISPATCH 1253 */ +static void vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, SVGA3dCmdDXDispatch const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDispatch(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */ +static void vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, SVGA3dCmdDXDispatchIndirect const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDispatchIndirect(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */ +static void vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdWriteZeroSurface const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnWriteZeroSurface(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */ +static void vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, SVGA3dCmdHintZeroSurface const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnHintZeroSurface(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */ +static void vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferToBuffer const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXTransferToBuffer(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */ +static void vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, SVGA3dCmdDXSetStructureCount const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetStructureCount(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */ +static void vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsBitBlt const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsBitBlt(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */ +static void vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsTransBlt const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsTransBlt(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */ +static void vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsStretchBlt const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsStretchBlt(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */ +static void vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsColorFill const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsColorFill(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */ +static void vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsAlphaBlend const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsAlphaBlend(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */ +static void vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnLogicOpsClearTypeBlend(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */ +static void vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDefineGBSurface_v4(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */ +static void vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, SVGA3dCmdDXSetCSUAViews const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetCSUAViews(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */ +static void vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, SVGA3dCmdDXSetMinLOD const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetMinLOD(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */ +static void vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView_v2(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */ +static void vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutputWithMob(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */ +static void vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXSetShaderIface const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXSetShaderIface(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */ +static void vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, SVGA3dCmdDXBindStreamOutput const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXBindStreamOutput(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */ +static void vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnSurfaceStretchBltNonMSToMS(pThisCC->svga.p3dState); + } +} + + +/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */ +static void vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, SVGA3dCmdDXBindShaderIface const *pCmd) +{ +ASMBreakpoint(); + PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State; + if (pSvgaR3State->pFuncsDX) + { + RT_NOREF(pCmd); + pSvgaR3State->pFuncsDX->pfnDXBindShaderIface(pThisCC->svga.p3dState); } } @@ -3043,54 +3655,12 @@ case SVGA_3D_CMD_DEAD1: case SVGA_3D_CMD_DEAD2: + case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */ + case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */ + case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */ + case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */ + case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */ + case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */ { VMSVGA_3D_CMD_NOTIMPL(); - break; - } - - case SVGA_3D_CMD_LOGICOPS_BITBLT: - { - SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); - break; - } - - case SVGA_3D_CMD_LOGICOPS_TRANSBLT: - { - SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); - break; - } - - case SVGA_3D_CMD_LOGICOPS_STRETCHBLT: - { - SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); - break; - } - - case SVGA_3D_CMD_LOGICOPS_COLORFILL: - { - SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); - break; - } - - case SVGA_3D_CMD_LOGICOPS_ALPHABLEND: - { - SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); - break; - } - - case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND: - { - SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd); break; } @@ -3800,9 +4370,9 @@ } - case SVGA_3D_CMD_DX_STRETCHBLT: - { - SVGA3dCmdDXStretchBlt *pCmd = (SVGA3dCmdDXStretchBlt *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - vmsvga3dCmdDXStretchBlt(pThisCC, pCmd); + case SVGA_3D_CMD_DX_PRESENTBLT: + { + SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXPresentBlt(pThisCC, pCmd); break; } @@ -4144,5 +4714,45 @@ } - case SVGA_3D_CMD_DX_RESERVED1: + case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET: + { + SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET: + { + SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET: + { + SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER: + { + SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXCondBindAllShader(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_SCREEN_COPY: + { + SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdScreenCopy(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_RESERVED1: { VMSVGA_3D_CMD_NOTIMPL(); @@ -4150,5 +4760,5 @@ } - case SVGA_3D_CMD_DX_RESERVED2: + case SVGA_3D_CMD_RESERVED2: { VMSVGA_3D_CMD_NOTIMPL(); @@ -4156,5 +4766,5 @@ } - case SVGA_3D_CMD_DX_RESERVED3: + case SVGA_3D_CMD_RESERVED3: { VMSVGA_3D_CMD_NOTIMPL(); @@ -4162,21 +4772,371 @@ } - case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER: - { - SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd; - VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); - vmsvga3dCmdDXCondBindAllShader(pThisCC, pCmd); + case SVGA_3D_CMD_RESERVED4: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED5: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED6: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED7: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED8: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_GROW_OTABLE: + { + SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdGrowOTable(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_GROW_COTABLE: + { + SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_INTRA_SURFACE_COPY: + { + SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdIntraSurfaceCopy(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3: + { + SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_RESOLVE_COPY: + { + SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXResolveCopy(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY: + { + SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXPredResolveCopy(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_PRED_CONVERT_REGION: + { + SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXPredConvertRegion(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_PRED_CONVERT: + { + SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXPredConvert(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_WHOLE_SURFACE_COPY: + { + SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdWholeSurfaceCopy(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DEFINE_UA_VIEW: + { + SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDefineUAView(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DESTROY_UA_VIEW: + { + SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDestroyUAView(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT: + { + SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXClearUAViewUint(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT: + { + SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXClearUAViewFloat(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT: + { + SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXCopyStructureCount(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_UA_VIEWS: + { + SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetUAViews(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT: + { + SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT: + { + SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DISPATCH: + { + SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDispatch(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DISPATCH_INDIRECT: + { + SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDispatchIndirect(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_WRITE_ZERO_SURFACE: + { + SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdWriteZeroSurface(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_HINT_ZERO_SURFACE: + { + SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdHintZeroSurface(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER: + { + SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXTransferToBuffer(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT: + { + SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetStructureCount(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_BITBLT: + { + SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsBitBlt(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_TRANSBLT: + { + SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsTransBlt(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_STRETCHBLT: + { + SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsStretchBlt(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_COLORFILL: + { + SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsColorFill(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_ALPHABLEND: + { + SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND: + { + SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_RESERVED2_1: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED2_2: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4: + { + SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS: + { + SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetCSUAViews(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_MIN_LOD: + { + SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetMinLOD(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_RESERVED2_3: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_RESERVED2_4: + { + VMSVGA_3D_CMD_NOTIMPL(); + break; + } + + case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2: + { + SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB: + { + SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_SET_SHADER_IFACE: + { + SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXSetShaderIface(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT: + { + SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXBindStreamOutput(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS: + { + SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, pCmd); + break; + } + + case SVGA_3D_CMD_DX_BIND_SHADER_IFACE: + { + SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd; + VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd)); + vmsvga3dCmdDXBindShaderIface(pThisCC, pCmd); break; } /* Unsupported commands. */ - case SVGA_3D_CMD_VIDEO_CREATE_DECODER: - case SVGA_3D_CMD_VIDEO_DESTROY_DECODER: - case SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR: - case SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR: - case SVGA_3D_CMD_VIDEO_DECODE_START_FRAME: - case SVGA_3D_CMD_VIDEO_DECODE_RENDER: - case SVGA_3D_CMD_VIDEO_DECODE_END_FRAME: - case SVGA_3D_CMD_VIDEO_PROCESS_FRAME: + case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */ + case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */ + case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */ + case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */ + case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */ + case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */ + case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */ + case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */ /* Prevent the compiler warning. */ case SVGA_3D_CMD_LEGACY_BASE: Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (revision 86905) @@ -431,4 +431,5 @@ static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg) { + AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */ switch (idxReg) { @@ -459,5 +460,5 @@ SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */ SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */ - SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ID); /* (Deprecated) */ + SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */ SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */ SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */ @@ -493,8 +494,27 @@ SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */ SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW); - SVGA_CASE_ID2STR(SVGA_REG_iCMD_PREPEND_HIGH); + SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH); SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH); SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT); SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE); + SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS); + SVGA_CASE_ID2STR(SVGA_REG_CAP2); + SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP); + SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID); + SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1); + SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2); + SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3); + SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID); + SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE); + SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION); + SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS); + SVGA_CASE_ID2STR(SVGA_REG_FENCE); + SVGA_CASE_ID2STR(SVGA_REG_RESERVED1); + SVGA_CASE_ID2STR(SVGA_REG_RESERVED2); + SVGA_CASE_ID2STR(SVGA_REG_RESERVED3); + SVGA_CASE_ID2STR(SVGA_REG_RESERVED4); + SVGA_CASE_ID2STR(SVGA_REG_RESERVED5); + SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA); + SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB); SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */ @@ -512,4 +532,5 @@ static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap) { + AssertCompile(SVGA3D_DEVCAP_MAX == 260); switch (idxDevCap) { @@ -585,11 +606,11 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_ALPHATOCOVERAGE); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SUPERSAMPLE); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_AYUV); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS); @@ -600,6 +621,6 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VIDEO_DECODE); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VIDEO_PROCESS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */ + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE); @@ -607,9 +628,9 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS); @@ -659,5 +680,5 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_AYUV); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT); @@ -676,6 +697,6 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT); @@ -695,6 +716,6 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS); - SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM); @@ -759,4 +780,20 @@ SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5); + SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X); SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX); @@ -1330,5 +1367,5 @@ /* Mouse cursor support. */ - case SVGA_REG_CURSOR_ID: + case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */ STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd); *pu32 = pThis->svga.uCursorID; @@ -1438,5 +1475,5 @@ break; - case SVGA_REG_iCMD_PREPEND_HIGH: + case SVGA_REG_CMD_PREPEND_HIGH: STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd); *pu32 = 0; /* Not supported. */ @@ -1971,5 +2008,5 @@ /* Mouse cursor support */ - case SVGA_REG_CURSOR_ID: + case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */ STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr); pThis->svga.uCursorID = u32; @@ -2174,5 +2211,5 @@ break; - case SVGA_REG_iCMD_PREPEND_HIGH: + case SVGA_REG_CMD_PREPEND_HIGH: STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr); /* Not supported. */ @@ -2618,15 +2655,15 @@ Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); break; - case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES: - Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); - break; - case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES: - Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); - break; - case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE: - Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); - break; - case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE: - Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); + case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ + Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); + break; + case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ + Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); + break; + case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ + Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); + break; + case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */ + Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); break; case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS: @@ -2636,6 +2673,6 @@ Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); break; - case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV: - Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); + case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ + Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2])); break; case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS: @@ -5784,5 +5821,5 @@ pThis->svga.u32DeviceCaps |= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */ if (pSVGAState->pFuncsDX) - pThis->svga.u32DeviceCaps |= SVGA_CAP_CMD_BUFFERS_3; /* AKA SVGA_CAP_DX. Enable support for DX commands, and command buffers in a mob. */ + pThis->svga.u32DeviceCaps |= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */ # endif } @@ -6215,5 +6252,5 @@ REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes."); REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes."); - REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes."); + REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes."); REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes."); REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes."); @@ -6246,5 +6283,5 @@ REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes."); REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes."); - REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_iCMD_PREPEND_HIGH writes."); + REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes."); REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads."); @@ -6256,5 +6293,5 @@ REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads."); REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads."); - REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads."); + REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads."); REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads."); REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads."); @@ -6306,5 +6343,5 @@ REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads."); REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads."); - REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_iCMD_PREPEND_HIGH reads."); + REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads."); REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads."); REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads."); Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-info.cpp (revision 86905) @@ -95,5 +95,5 @@ { SVGA3D_YUY2 , "YUY2" }, { SVGA3D_NV12 , "NV12" }, - { SVGA3D_AYUV , "AYUV" }, + { SVGA3D_FORMAT_DEAD2 , "DEAD2" }, /* Old SVGA3D_AYUV */ { SVGA3D_ATI1 , "ATI1" }, { SVGA3D_ATI2 , "ATI2" }, @@ -119,5 +119,5 @@ }; -/** SVGA3dSurfaceFlags values, prefix SVGA3D_SURFACE_. */ +/** SVGA3dSurface1Flags values, prefix SVGA3D_SURFACE_. */ static VMSVGAINFOFLAGS32 const g_aSvga3DSurfaceFlags[] = { @@ -131,5 +131,5 @@ { SVGA3D_SURFACE_HINT_DEPTHSTENCIL , "HINT_DEPTHSTENCIL" }, { SVGA3D_SURFACE_HINT_WRITEONLY , "HINT_WRITEONLY" }, - { SVGA3D_SURFACE_MASKABLE_ANTIALIAS , "MASKABLE_ANTIALIAS" }, + { SVGA3D_SURFACE_DEAD2 , "MASKABLE_ANTIALIAS" }, /* SVGA3D_SURFACE_MASKABLE_ANTIALIAS */ { SVGA3D_SURFACE_AUTOGENMIPMAPS , "AUTOGENMIPMAPS" }, }; @@ -1030,5 +1030,5 @@ case SVGA3D_YUY2: case SVGA3D_NV12: - case SVGA3D_AYUV: + case SVGA3D_FORMAT_DEAD2: /* Old SVGA3D_AYUV */ case SVGA3D_ATI1: case SVGA3D_ATI2: Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-internal.h =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-internal.h (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-internal.h (revision 86905) @@ -554,5 +554,5 @@ uint32_t idAssociatedContext; #endif - uint32_t surfaceFlags; + SVGA3dSurface1Flags surfaceFlags; /* @todo SVGA3dSurfaceAllFlags as an union. */ SVGA3dSurfaceFormat format; #ifdef VMSVGA3D_OPENGL Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-ogl.cpp (revision 86905) @@ -1353,5 +1353,5 @@ case SVGA3D_DEVCAP_SURFACEFMT_NV12: - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: + case SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ break; } @@ -1518,14 +1518,14 @@ break; - case SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES: - break; - - case SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES: - break; - - case SVGA3D_DEVCAP_ALPHATOCOVERAGE: - break; - - case SVGA3D_DEVCAP_SUPERSAMPLE: + case SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ + break; + + case SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ + break; + + case SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ + break; + + case SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */ break; @@ -1619,5 +1619,5 @@ case SVGA3D_DEVCAP_SURFACEFMT_YUY2: case SVGA3D_DEVCAP_SURFACEFMT_NV12: - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: + case SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ *pu32Val = vmsvga3dGetSurfaceFormatSupport(idx3dCaps); break; @@ -1960,6 +1960,5 @@ /* Video format with alpha */ - case SVGA3D_AYUV: - return (D3DFORMAT)MAKEFOURCC('A', 'Y', 'U', 'V'); + case SVGA3D_FORMAT_DEAD2: /* Old SVGA3D_AYUV */ case SVGA3D_ATI1: Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-shared.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-shared.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-shared.cpp (revision 86905) @@ -528,11 +528,11 @@ case SVGA3D_DEVCAP_TEXTURE_OPS: return "SVGA3D_DEVCAP_TEXTURE_OPS"; - case SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES: + case SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ return "SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES"; - case SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES: + case SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ return "SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES"; - case SVGA3D_DEVCAP_ALPHATOCOVERAGE: + case SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ return "SVGA3D_DEVCAP_ALPHATOCOVERAGE"; - case SVGA3D_DEVCAP_SUPERSAMPLE: + case SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */ return "SVGA3D_DEVCAP_SUPERSAMPLE"; case SVGA3D_DEVCAP_AUTOGENMIPMAPS: @@ -624,5 +624,5 @@ case SVGA3D_DEVCAP_SURFACEFMT_NV12: return "SVGA3D_DEVCAP_SURFACEFMT_NV12"; - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: + case SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ return "SVGA3D_DEVCAP_SURFACEFMT_AYUV"; case SVGA3D_DEVCAP_SURFACEFMT_ATI1: Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win-dx.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win-dx.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win-dx.cpp (revision 86905) @@ -111,4 +111,9 @@ static DXGI_FORMAT vmsvgaDXSurfaceFormat2Dxgi(SVGA3dSurfaceFormat format) { + /* Ensure that correct headers are used. + * SVGA3D_AYUV was equal to 45, then replaced with SVGA3D_FORMAT_DEAD2 = 45, and redefined as SVGA3D_AYUV = 152. + */ + AssertCompile(SVGA3D_AYUV == 152); + #define DXGI_FORMAT_ DXGI_FORMAT_UNKNOWN /** @todo More formats. */ @@ -159,5 +164,5 @@ case SVGA3D_YUY2: return DXGI_FORMAT_; case SVGA3D_NV12: return DXGI_FORMAT_; - case SVGA3D_AYUV: return DXGI_FORMAT_; + case SVGA3D_FORMAT_DEAD2: break; /* Old SVGA3D_AYUV */ case SVGA3D_R32G32B32A32_TYPELESS: return DXGI_FORMAT_R32G32B32A32_TYPELESS; case SVGA3D_R32G32B32A32_UINT: return DXGI_FORMAT_R32G32B32A32_UINT; @@ -260,4 +265,13 @@ case SVGA3D_BC5_UNORM: return DXGI_FORMAT_BC5_UNORM; + case SVGA3D_B4G4R4A4_UNORM: return DXGI_FORMAT_; + case SVGA3D_BC6H_TYPELESS: return DXGI_FORMAT_; + case SVGA3D_BC6H_UF16: return DXGI_FORMAT_; + case SVGA3D_BC6H_SF16: return DXGI_FORMAT_; + case SVGA3D_BC7_TYPELESS: return DXGI_FORMAT_; + case SVGA3D_BC7_UNORM: return DXGI_FORMAT_; + case SVGA3D_BC7_UNORM_SRGB: return DXGI_FORMAT_; + case SVGA3D_AYUV: return DXGI_FORMAT_; + case SVGA3D_FORMAT_INVALID: case SVGA3D_FORMAT_MAX: break; @@ -309,5 +323,5 @@ case SVGA3D_DEVCAP_SURFACEFMT_YUY2: return SVGA3D_YUY2; case SVGA3D_DEVCAP_SURFACEFMT_NV12: return SVGA3D_NV12; - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: return SVGA3D_AYUV; + case SVGA3D_DEVCAP_DEAD10: return SVGA3D_FORMAT_DEAD2; /* SVGA3D_DEVCAP_SURFACEFMT_AYUV -> SVGA3D_AYUV */ case SVGA3D_DEVCAP_SURFACEFMT_Z_DF16: return SVGA3D_Z_DF16; case SVGA3D_DEVCAP_SURFACEFMT_Z_DF24: return SVGA3D_Z_DF24; @@ -372,5 +386,5 @@ case SVGA3D_DEVCAP_DXFMT_YUY2: return SVGA3D_YUY2; case SVGA3D_DEVCAP_DXFMT_NV12: return SVGA3D_NV12; - case SVGA3D_DEVCAP_DXFMT_AYUV: return SVGA3D_AYUV; + case SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2: return SVGA3D_FORMAT_DEAD2; /* SVGA3D_DEVCAP_DXFMT_AYUV -> SVGA3D_AYUV */ case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS: return SVGA3D_R32G32B32A32_TYPELESS; case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT: return SVGA3D_R32G32B32A32_UINT; @@ -389,6 +403,6 @@ case SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS: return SVGA3D_R32G8X24_TYPELESS; case SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT: return SVGA3D_D32_FLOAT_S8X24_UINT; - case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS: return SVGA3D_R32_FLOAT_X8X24; - case SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT: return SVGA3D_X32_G8X24_UINT; + case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24: return SVGA3D_R32_FLOAT_X8X24; + case SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT: return SVGA3D_X32_G8X24_UINT; case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS: return SVGA3D_R10G10B10A2_TYPELESS; case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT: return SVGA3D_R10G10B10A2_UINT; @@ -408,6 +422,6 @@ case SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS: return SVGA3D_R24G8_TYPELESS; case SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT: return SVGA3D_D24_UNORM_S8_UINT; - case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS: return SVGA3D_R24_UNORM_X8; - case SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT: return SVGA3D_X24_G8_UINT; + case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8: return SVGA3D_R24_UNORM_X8; + case SVGA3D_DEVCAP_DXFMT_X24_G8_UINT: return SVGA3D_X24_G8_UINT; case SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS: return SVGA3D_R8G8_TYPELESS; case SVGA3D_DEVCAP_DXFMT_R8G8_UNORM: return SVGA3D_R8G8_UNORM; @@ -540,13 +554,5 @@ hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 2, &NumQualityLevels); if (SUCCEEDED(hr) && NumQualityLevels != 0) - *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_2; - - hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 4, &NumQualityLevels); - if (SUCCEEDED(hr) && NumQualityLevels != 0) - *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_4; - - hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 8, &NumQualityLevels); - if (SUCCEEDED(hr) && NumQualityLevels != 0) - *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_8; + *pu32DevCap |= SVGA3D_DXFMT_MULTISAMPLE; } else @@ -1252,4 +1258,10 @@ *pu32Val = 0; + + if (idx3dCaps > SVGA3D_DEVCAP_MAX) + { + LogRelMax(16, ("VMSVGA: unsupported SVGA3D_DEVCAP %d\n", idx3dCaps)); + return VERR_NOT_SUPPORTED; + } /* Most values are taken from: @@ -1472,5 +1484,5 @@ case SVGA3D_DEVCAP_SURFACEFMT_YUY2: case SVGA3D_DEVCAP_SURFACEFMT_NV12: - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: + case SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ case SVGA3D_DEVCAP_SURFACEFMT_Z_DF16: case SVGA3D_DEVCAP_SURFACEFMT_Z_DF24: @@ -1502,15 +1514,15 @@ break; - case SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES: - case SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES: + case SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ + case SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ *pu32Val = (1 << (2-1)) | (1 << (4-1)) | (1 << (8-1)); /* 2x, 4x, 8x */ break; - case SVGA3D_DEVCAP_ALPHATOCOVERAGE: - /* Obsolete? */ - break; - - case SVGA3D_DEVCAP_SUPERSAMPLE: - /* Obsolete? */ + case SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ + /* Obsolete */ + break; + + case SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */ + /* Obsolete */ break; @@ -1531,9 +1543,9 @@ break; - case SVGA3D_DEVCAP_VIDEO_DECODE: + case SVGA3D_DEVCAP_DEAD8: /* SVGA3D_DEVCAP_VIDEO_DECODE */ /* Obsolete */ break; - case SVGA3D_DEVCAP_VIDEO_PROCESS: + case SVGA3D_DEVCAP_DEAD9: /* SVGA3D_DEVCAP_VIDEO_PROCESS */ /* Obsolete */ break; @@ -1557,8 +1569,7 @@ break; - case SVGA3D_DEVCAP_LOGICOPS: + case SVGA3D_DEVCAP_DEAD3: /* Old SVGA3D_DEVCAP_LOGICOPS */ /* Deprecated. */ - AssertCompile(SVGA3D_DEVCAP_LOGICOPS == 92); /* Newer SVGA headers redefine this. */ - *pu32Val = 0; /* Supported starting with Direct3D 11.1 */ + AssertCompile(SVGA3D_DEVCAP_DEAD3 == 92); /* Newer SVGA headers redefine this. */ break; @@ -1570,9 +1581,9 @@ break; - case SVGA3D_DEVCAP_DX: + case SVGA3D_DEVCAP_DXCONTEXT: *pu32Val = 1; break; - case SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE: + case SVGA3D_DEVCAP_DEAD11: /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */ *pu32Val = D3D11_REQ_TEXTURE2D_ARRAY_AXIS_DIMENSION; break; @@ -1634,5 +1645,5 @@ case SVGA3D_DEVCAP_DXFMT_YUY2: case SVGA3D_DEVCAP_DXFMT_NV12: - case SVGA3D_DEVCAP_DXFMT_AYUV: + case SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2: /* SVGA3D_DEVCAP_DXFMT_AYUV */ case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS: case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT: @@ -1651,6 +1662,6 @@ case SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS: case SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT: - case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS: - case SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT: + case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24: + case SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT: case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS: case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT: @@ -1670,6 +1681,6 @@ case SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS: case SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT: - case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS: - case SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT: + case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8: + case SVGA3D_DEVCAP_DXFMT_X24_G8_UINT: case SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS: case SVGA3D_DEVCAP_DXFMT_R8G8_UNORM: @@ -1734,4 +1745,10 @@ case SVGA3D_DEVCAP_DXFMT_BC4_UNORM: case SVGA3D_DEVCAP_DXFMT_BC5_UNORM: + case SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS: + case SVGA3D_DEVCAP_DXFMT_BC6H_UF16: + case SVGA3D_DEVCAP_DXFMT_BC6H_SF16: + case SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS: + case SVGA3D_DEVCAP_DXFMT_BC7_UNORM: + case SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB: { SVGA3dSurfaceFormat const enmFormat = vmsvgaDXDevCapDxfmt2Format(idx3dCaps); @@ -1739,4 +1756,43 @@ break; } + + case SVGA3D_DEVCAP_SM41: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_MULTISAMPLE_2X: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_MULTISAMPLE_4X: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_MS_FULL_QUALITY: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_LOGICOPS: + AssertCompile(SVGA3D_DEVCAP_LOGICOPS == 248); + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_LOGIC_BLENDOPS: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_RESERVED_1: + break; + + case SVGA3D_DEVCAP_RESERVED_2: + break; + + case SVGA3D_DEVCAP_SM5: + *pu32Val = 0; /* boolean */ + break; + + case SVGA3D_DEVCAP_MULTISAMPLE_8X: + *pu32Val = 0; /* boolean */ + break; case SVGA3D_DEVCAP_MAX: @@ -2613,5 +2669,5 @@ -static DECLCALLBACK(void) vmsvga3dDXStretchBlt(PVMSVGA3DSTATE p3dState) +static DECLCALLBACK(void) vmsvga3dDXPresentBlt(PVMSVGA3DSTATE p3dState) { PVMSVGA3DBACKEND pBackend = p3dState->pBackend; @@ -3000,5 +3056,383 @@ +static DECLCALLBACK(void) vmsvga3dDXSetHSConstantBufferOffset(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetDSConstantBufferOffset(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetCSConstantBufferOffset(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + static DECLCALLBACK(void) vmsvga3dDXCondBindAllShader(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dScreenCopy(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dGrowOTable(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXGrowCOTable(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dIntraSurfaceCopy(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDefineGBSurface_v3(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXResolveCopy(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXPredResolveCopy(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXPredConvertRegion(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXPredConvert(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dWholeSurfaceCopy(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDefineUAView(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDestroyUAView(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXClearUAViewUint(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXClearUAViewFloat(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXCopyStructureCount(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetUAViews(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDrawIndexedInstancedIndirect(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDrawInstancedIndirect(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDispatch(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDispatchIndirect(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dWriteZeroSurface(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dHintZeroSurface(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXTransferToBuffer(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetStructureCount(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsBitBlt(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsTransBlt(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsStretchBlt(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsColorFill(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsAlphaBlend(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dLogicOpsClearTypeBlend(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDefineGBSurface_v4(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetCSUAViews(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetMinLOD(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDefineDepthStencilView_v2(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXDefineStreamOutputWithMob(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXSetShaderIface(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXBindStreamOutput(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dSurfaceStretchBltNonMSToMS(PVMSVGA3DSTATE p3dState) +{ + PVMSVGA3DBACKEND pBackend = p3dState->pBackend; + + RT_NOREF(pBackend); + AssertFailed(); /** @todo Implement */ +} + + +static DECLCALLBACK(void) vmsvga3dDXBindShaderIface(PVMSVGA3DSTATE p3dState) { PVMSVGA3DBACKEND pBackend = p3dState->pBackend; @@ -3065,5 +3499,5 @@ p->pfnDXPredCopyRegion = vmsvga3dDXPredCopyRegion; p->pfnDXPredCopy = vmsvga3dDXPredCopy; - p->pfnDXStretchBlt = vmsvga3dDXStretchBlt; + p->pfnDXPresentBlt = vmsvga3dDXPresentBlt; p->pfnDXGenMips = vmsvga3dDXGenMips; p->pfnDXUpdateSubResource = vmsvga3dDXUpdateSubResource; @@ -3108,5 +3542,47 @@ p->pfnDXSetPSConstantBufferOffset = vmsvga3dDXSetPSConstantBufferOffset; p->pfnDXSetGSConstantBufferOffset = vmsvga3dDXSetGSConstantBufferOffset; + p->pfnDXSetHSConstantBufferOffset = vmsvga3dDXSetHSConstantBufferOffset; + p->pfnDXSetDSConstantBufferOffset = vmsvga3dDXSetDSConstantBufferOffset; + p->pfnDXSetCSConstantBufferOffset = vmsvga3dDXSetCSConstantBufferOffset; p->pfnDXCondBindAllShader = vmsvga3dDXCondBindAllShader; + p->pfnScreenCopy = vmsvga3dScreenCopy; + p->pfnGrowOTable = vmsvga3dGrowOTable; + p->pfnDXGrowCOTable = vmsvga3dDXGrowCOTable; + p->pfnIntraSurfaceCopy = vmsvga3dIntraSurfaceCopy; + p->pfnDefineGBSurface_v3 = vmsvga3dDefineGBSurface_v3; + p->pfnDXResolveCopy = vmsvga3dDXResolveCopy; + p->pfnDXPredResolveCopy = vmsvga3dDXPredResolveCopy; + p->pfnDXPredConvertRegion = vmsvga3dDXPredConvertRegion; + p->pfnDXPredConvert = vmsvga3dDXPredConvert; + p->pfnWholeSurfaceCopy = vmsvga3dWholeSurfaceCopy; + p->pfnDXDefineUAView = vmsvga3dDXDefineUAView; + p->pfnDXDestroyUAView = vmsvga3dDXDestroyUAView; + p->pfnDXClearUAViewUint = vmsvga3dDXClearUAViewUint; + p->pfnDXClearUAViewFloat = vmsvga3dDXClearUAViewFloat; + p->pfnDXCopyStructureCount = vmsvga3dDXCopyStructureCount; + p->pfnDXSetUAViews = vmsvga3dDXSetUAViews; + p->pfnDXDrawIndexedInstancedIndirect = vmsvga3dDXDrawIndexedInstancedIndirect; + p->pfnDXDrawInstancedIndirect = vmsvga3dDXDrawInstancedIndirect; + p->pfnDXDispatch = vmsvga3dDXDispatch; + p->pfnDXDispatchIndirect = vmsvga3dDXDispatchIndirect; + p->pfnWriteZeroSurface = vmsvga3dWriteZeroSurface; + p->pfnHintZeroSurface = vmsvga3dHintZeroSurface; + p->pfnDXTransferToBuffer = vmsvga3dDXTransferToBuffer; + p->pfnDXSetStructureCount = vmsvga3dDXSetStructureCount; + p->pfnLogicOpsBitBlt = vmsvga3dLogicOpsBitBlt; + p->pfnLogicOpsTransBlt = vmsvga3dLogicOpsTransBlt; + p->pfnLogicOpsStretchBlt = vmsvga3dLogicOpsStretchBlt; + p->pfnLogicOpsColorFill = vmsvga3dLogicOpsColorFill; + p->pfnLogicOpsAlphaBlend = vmsvga3dLogicOpsAlphaBlend; + p->pfnLogicOpsClearTypeBlend = vmsvga3dLogicOpsClearTypeBlend; + p->pfnDefineGBSurface_v4 = vmsvga3dDefineGBSurface_v4; + p->pfnDXSetCSUAViews = vmsvga3dDXSetCSUAViews; + p->pfnDXSetMinLOD = vmsvga3dDXSetMinLOD; + p->pfnDXDefineDepthStencilView_v2 = vmsvga3dDXDefineDepthStencilView_v2; + p->pfnDXDefineStreamOutputWithMob = vmsvga3dDXDefineStreamOutputWithMob; + p->pfnDXSetShaderIface = vmsvga3dDXSetShaderIface; + p->pfnDXBindStreamOutput = vmsvga3dDXBindStreamOutput; + p->pfnSurfaceStretchBltNonMSToMS = vmsvga3dSurfaceStretchBltNonMSToMS; + p->pfnDXBindShaderIface = vmsvga3dDXBindShaderIface; } } Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win.cpp (revision 86905) @@ -600,14 +600,14 @@ break; - case SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES: - break; - - case SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES: - break; - - case SVGA3D_DEVCAP_ALPHATOCOVERAGE: - break; - - case SVGA3D_DEVCAP_SUPERSAMPLE: + case SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */ + break; + + case SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */ + break; + + case SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */ + break; + + case SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */ break; @@ -795,5 +795,5 @@ break; - case SVGA3D_DEVCAP_SURFACEFMT_AYUV: + case SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */ *pu32Val = vmsvga3dGetSurfaceFormatSupport(pState, idx3dCaps, (D3DFORMAT)MAKEFOURCC('A', 'Y', 'U', 'V')); break; @@ -1056,5 +1056,5 @@ /* Video format with alpha */ - case SVGA3D_AYUV: + case SVGA3D_FORMAT_DEAD2: /* Old SVGA3D_AYUV */ return (D3DFORMAT)MAKEFOURCC('A', 'Y', 'U', 'V'); Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.cpp (revision 86905) @@ -55,5 +55,5 @@ * @param pMipLevel0Size . */ -int vmsvga3dSurfaceDefine(PVGASTATECC pThisCC, uint32_t sid, SVGA3dSurfaceFlags surfaceFlags, SVGA3dSurfaceFormat format, +int vmsvga3dSurfaceDefine(PVGASTATECC pThisCC, uint32_t sid, SVGA3dSurface1Flags surfaceFlags, SVGA3dSurfaceFormat format, uint32_t multisampleCount, SVGA3dTextureFilter autogenFilter, uint32_t numMipLevels, SVGA3dSize const *pMipLevel0Size) @@ -169,5 +169,5 @@ case SVGA3D_YUY2: case SVGA3D_NV12: - case SVGA3D_AYUV: + case SVGA3D_FORMAT_DEAD2: /* Old SVGA3D_AYUV */ case SVGA3D_ATI1: case SVGA3D_ATI2: Index: /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h =================================================================== --- /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h (revision 86904) +++ /trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d.h (revision 86905) @@ -85,5 +85,5 @@ int vmsvga3dQueryCaps(PVGASTATECC pThisCC, SVGA3dDevCapIndex idx3dCaps, uint32_t *pu32Val); -int vmsvga3dSurfaceDefine(PVGASTATECC pThisCC, uint32_t sid, SVGA3dSurfaceFlags surfaceFlags, SVGA3dSurfaceFormat format, +int vmsvga3dSurfaceDefine(PVGASTATECC pThisCC, uint32_t sid, SVGA3dSurface1Flags surfaceFlags, SVGA3dSurfaceFormat format, uint32_t multisampleCount, SVGA3dTextureFilter autogenFilter, uint32_t cMipLevels, SVGA3dSize const *pMipLevel0Size); @@ -321,5 +321,5 @@ DECLCALLBACKMEMBER(void, pfnDXPredCopyRegion, (PVMSVGA3DSTATE p3dState)); DECLCALLBACKMEMBER(void, pfnDXPredCopy, (PVMSVGA3DSTATE p3dState)); - DECLCALLBACKMEMBER(void, pfnDXStretchBlt, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXPresentBlt, (PVMSVGA3DSTATE p3dState)); DECLCALLBACKMEMBER(void, pfnDXGenMips, (PVMSVGA3DSTATE p3dState)); DECLCALLBACKMEMBER(void, pfnDXUpdateSubResource, (PVMSVGA3DSTATE p3dState)); @@ -364,5 +364,47 @@ DECLCALLBACKMEMBER(void, pfnDXSetPSConstantBufferOffset, (PVMSVGA3DSTATE p3dState)); DECLCALLBACKMEMBER(void, pfnDXSetGSConstantBufferOffset, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetHSConstantBufferOffset, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetDSConstantBufferOffset, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetCSConstantBufferOffset, (PVMSVGA3DSTATE p3dState)); DECLCALLBACKMEMBER(void, pfnDXCondBindAllShader, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnScreenCopy, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnGrowOTable, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXGrowCOTable, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnIntraSurfaceCopy, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDefineGBSurface_v3, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXResolveCopy, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXPredResolveCopy, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXPredConvertRegion, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXPredConvert, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnWholeSurfaceCopy, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDefineUAView, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDestroyUAView, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXClearUAViewUint, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXClearUAViewFloat, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXCopyStructureCount, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetUAViews, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDrawIndexedInstancedIndirect, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDrawInstancedIndirect, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDispatch, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDispatchIndirect, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnWriteZeroSurface, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnHintZeroSurface, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXTransferToBuffer, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetStructureCount, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsBitBlt, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsTransBlt, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsStretchBlt, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsColorFill, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsAlphaBlend, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnLogicOpsClearTypeBlend, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDefineGBSurface_v4, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetCSUAViews, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetMinLOD, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDefineDepthStencilView_v2, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXDefineStreamOutputWithMob, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXSetShaderIface, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXBindStreamOutput, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnSurfaceStretchBltNonMSToMS, (PVMSVGA3DSTATE p3dState)); + DECLCALLBACKMEMBER(void, pfnDXBindShaderIface, (PVMSVGA3DSTATE p3dState)); } VMSVGA3DBACKENDFUNCSDX; Index: /trunk/src/VBox/Devices/Makefile.kmk =================================================================== --- /trunk/src/VBox/Devices/Makefile.kmk (revision 86904) +++ /trunk/src/VBox/Devices/Makefile.kmk (revision 86905) @@ -301,5 +301,5 @@ ifdef VBOX_WITH_VMSVGA VBoxDD_DEFS += VBOX_WITH_VMSVGA - VBoxDD_INCS += $(VBOX_PATH_VMSVGA_INC) + VBoxDD_INCS += $(VBOX_PATH_VMSVGA_DEVICE_INC) VBoxDD_SOURCES += \ Graphics/DevVGA-SVGA.cpp \ @@ -1147,5 +1147,5 @@ VBoxDDR0_DEFS.win += VBOX_WITH_WIN_PARPORT_SUP VBoxDDR0_INCS = build $(VBOX_GRAPHICS_INCS) - VBoxDDR0_INCS += $(VBOX_PATH_VMSVGA_INC) + VBoxDDR0_INCS += $(VBOX_PATH_VMSVGA_DEVICE_INC) VBoxDDR0_SDKS.win = ReorderCompilerIncs $(VBOX_WINPSDK) $(VBOX_WINDDK) VBoxDDR0_SOURCES = \ Index: /trunk/src/VBox/Devices/testcase/Makefile.kmk =================================================================== --- /trunk/src/VBox/Devices/testcase/Makefile.kmk (revision 86904) +++ /trunk/src/VBox/Devices/testcase/Makefile.kmk (revision 86905) @@ -107,5 +107,5 @@ $(VBOX_DEVICES_TEST_OUT_DIR) \ $(VBOX_GRAPHICS_INCS) \ - $(VBOX_PATH_VMSVGA_INC) + $(VBOX_PATH_VMSVGA_DEVICE_INC) tstDeviceStructSize_SOURCES = tstDeviceStructSize.cpp tstDeviceStructSize_CLEAN = \