- Timestamp:
- Oct 30, 2020 5:29:14 AM (4 years ago)
- Location:
- trunk
- Files:
-
- 2 edited
-
include/VBox/err.h (modified) (1 diff)
-
src/VBox/Devices/Bus/DevIommuAmd.cpp (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/err.h
r86726 r86763 3013 3013 /** Internal processing error \#4 in the IOMMU device code. */ 3014 3014 #define VERR_IOMMU_IPE_4 (-7204) 3015 /** Failed to read the device table entry from guest memory. */ 3016 #define VERR_IOMMU_DTE_READ_FAILED (-7205) 3017 /** Failed to read the device table entry due to an invalid offset. */ 3018 #define VERR_IOMMU_DTE_BAD_OFFSET (-7206) 3015 3019 /** Address translation failed. */ 3016 #define VERR_IOMMU_ADDR_TRANSLATION_FAILED (-720 5)3020 #define VERR_IOMMU_ADDR_TRANSLATION_FAILED (-7207) 3017 3021 /** Access denied for the address. */ 3018 #define VERR_IOMMU_ADDR_ACCESS_DENIED (-720 6)3022 #define VERR_IOMMU_ADDR_ACCESS_DENIED (-7208) 3019 3023 /** Remapping failed for the interrupt. */ 3020 #define VERR_IOMMU_INTR_REMAP_FAILED (-720 7)3024 #define VERR_IOMMU_INTR_REMAP_FAILED (-7209) 3021 3025 /** Remapping denied for the interrupt (might have caused a PCI target abort). */ 3022 #define VERR_IOMMU_INTR_REMAP_DENIED (-72 08)3023 /** Internal error -Command not supported. */3024 #define VERR_IOMMU_CMD_NOT_SUPPORTED (-72 09)3025 /** Internal error -Command format (or reserved bits) invalid. */3026 #define VERR_IOMMU_CMD_INVALID_FORMAT (-721 0)3027 /** Internal error -Command hardware failure. */3028 #define VERR_IOMMU_CMD_HW_ERROR (-721 1)3026 #define VERR_IOMMU_INTR_REMAP_DENIED (-7210) 3027 /** Command not supported. */ 3028 #define VERR_IOMMU_CMD_NOT_SUPPORTED (-7211) 3029 /** Command format (or reserved bits) invalid. */ 3030 #define VERR_IOMMU_CMD_INVALID_FORMAT (-7212) 3031 /** Command hardware failure. */ 3032 #define VERR_IOMMU_CMD_HW_ERROR (-7213) 3029 3033 /** @} */ 3030 3034 -
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r86732 r86763 891 891 /* Update the register. */ 892 892 pThis->aDevTabBaseAddrs[0].u64 = u64Value; 893 894 /* Paranoia. */ 895 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]); 893 896 return VINF_SUCCESS; 894 897 } … … 2667 2670 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis); 2668 2671 2672 /* Figure out which device table segment is being accessed. */ 2669 2673 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn; 2670 2674 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts)); … … 2675 2679 2676 2680 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT; 2677 uint 16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);2681 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T); 2678 2682 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte; 2679 2683 2680 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK)); 2681 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte)); 2682 if (RT_FAILURE(rc)) 2683 { 2684 /* Ensure the DTE falls completely within the device table segment. */ 2685 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT; 2686 if (offDte + sizeof(DTE_T) <= cbDevTabSeg) 2687 { 2688 /* Read the device table entry from guest memory. */ 2689 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK)); 2690 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte)); 2691 if (RT_SUCCESS(rc)) 2692 return rc; 2693 2694 /* Raise a device table hardware error. */ 2684 2695 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc)); 2685 2696 … … 2687 2698 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr); 2688 2699 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr); 2689 return VERR_IOMMU_IPE_1; 2690 } 2691 2692 return rc; 2700 return VERR_IOMMU_DTE_READ_FAILED; 2701 } 2702 2703 /* Raise an I/O page fault for out-of-bounds acccess. */ 2704 EVT_IO_PAGE_FAULT_T EvtIoPageFault; 2705 iommuAmdInitIoPageFaultEvent(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */, 2706 false /* fPermDenied */, enmOp, &EvtIoPageFault); 2707 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_DevId_Invalid); 2708 return VERR_IOMMU_DTE_BAD_OFFSET; 2693 2709 } 2694 2710 … … 3244 3260 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */, 3245 3261 false /* fPermDenied */, enmOp, &EvtIoPageFault); 3246 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, 3247 kIoPageFaultType_IrteAddrInvalid); 3262 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteAddrInvalid); 3248 3263 return VERR_IOMMU_ADDR_TRANSLATION_FAILED; 3249 3264 } … … 3348 3363 { 3349 3364 /* Read the device table entry from memory. */ 3350 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp)); 3365 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId, 3366 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK), 3367 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp)); 3351 3368 3352 3369 DTE_T Dte; … … 3404 3421 { 3405 3422 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl; 3406 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)3407 {3408 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));3409 iommuAmdSetPciTargetAbort(pDevIns);3410 return VERR_IOMMU_INTR_REMAP_DENIED;3411 }3412 3413 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)3414 {3415 fPassThru = true;3416 break;3417 }3418 3419 3423 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP) 3420 3424 { … … 3444 3448 } 3445 3449 3450 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED) 3451 { 3452 fPassThru = true; 3453 break; 3454 } 3455 3456 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT) 3457 { 3458 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n", 3459 pMsiIn->Data.n.u8Vector)); 3460 iommuAmdSetPciTargetAbort(pDevIns); 3461 return VERR_IOMMU_INTR_REMAP_DENIED; 3462 } 3463 3446 3464 /* Paranoia. */ 3447 3465 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); 3448 3466 3449 3467 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl)); 3450 3451 3468 EVT_ILLEGAL_DTE_T Event; 3452 3469 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event); … … 3474 3491 } 3475 3492 3493 LogFunc(("Remapping/passthru disallowed for interrupt (%#x) -> Target abort\n", pMsiIn->Data.n.u8Vector)); 3476 3494 iommuAmdSetPciTargetAbort(pDevIns); 3477 3495 return VERR_IOMMU_INTR_REMAP_DENIED;
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