Index: /trunk/include/VBox/msi.h =================================================================== --- /trunk/include/VBox/msi.h (revision 84650) +++ /trunk/include/VBox/msi.h (revision 84651) @@ -135,4 +135,88 @@ /** @} */ +/** + * MSI Address Register. + * In accordance to the Intel spec. + * See Intel spec. 10.11.1 "Message Address Register Format". + * + * This also conforms to the AMD IOMMU spec. which omits specifying individual + * fields but specifies reserved bits. + */ +typedef union +{ + struct + { + uint32_t u2Ign0 : 2; /**< Bits 1:0 - Ignored (read as 0, writes ignored). */ + uint32_t u1DestMode : 1; /**< Bit 2 - DM: Destination Mode. */ + uint32_t u1RedirHint : 1; /**< Bit 3 - RH: Redirection Hint. */ + uint32_t u8Rsvd0 : 8; /**< Bits 11:4 - Reserved. */ + uint32_t u8DestId : 8; /**< Bits 19:12 - Destination Id. */ + uint32_t u12Addr : 12; /**< Bits 31:20 - Address. */ + uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */ + } n; + /** The 32-bit unsigned integer view. */ + uint32_t au32[2]; + /** The 64-bit unsigned integer view. */ + uint64_t u64; +} MSIADDR; +AssertCompileSize(MSIADDR, 8); +/** Pointer to an MSI address register. */ +typedef MSIADDR *PMSIADDR; +/** Pointer to a const MSI address register. */ +typedef MSIADDR const *PCMSIADDR; + +/** Mask of valid bits in the MSI address register. According to the AMD IOMMU spec. + * and presumably the PCI spec., the top 32-bits are not reserved. From a PCI/IOMMU + * standpoint this makes sense. However, when dealing with the CPU side of things + * we might want to ensure the upper bits are reserved. Does x86/x64 really + * support a 64-bit MSI address? */ +#define VBOX_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc) +#define VBOX_MSI_ADDR_ADDR_MASK UINT64_C(0x00000000fff00000) + +/** + * MSI Data Register (PCI + MMIO). + * In accordance to the Intel spec. + * See Intel spec. 10.11.2 "Message Data Register Format". + * + * This also conforms to the AMD IOMMU spec. which omits specifying individual + * fields but specifies reserved bits. + */ +typedef union +{ + struct + { + uint32_t u8Vector : 8; /**< Bits 7:0 - Vector. */ + uint32_t u3DeliveryMode : 3; /**< Bits 10:8 - Delivery Mode. */ + uint32_t u3Rsvd0 : 3; /**< Bits 13:11 - Reserved. */ + uint32_t u1Level : 1; /**< Bit 14 - Level. */ + uint32_t u1TriggerMode : 1; /**< Bit 15 - Trigger Mode (0=edge, 1=level). */ + uint32_t u16Rsvd0 : 16; /**< Bits 31:16 - Reserved. */ + } n; + /** The 32-bit unsigned integer view. */ + uint32_t u32; +} MSIDATA; +AssertCompileSize(MSIDATA, 4); +/** Pointer to an MSI data register. */ +typedef MSIDATA *PMSIDATA; +/** Pointer to a const MSI data register. */ +typedef MSIDATA const *PCMSIDATA; + +/** Mask of valid bits in the MSI data register. */ +#define VBOX_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff) + +/** + * MSI Message (Address and Data Register Pair). + */ +typedef struct +{ + /** The MSI Address Register. */ + MSIADDR MsiAddr; + /** The MSI Data Register. */ + MSIDATA MsiData; +} MSIMSG; +/** Pointer to an MSI message struct. */ +typedef MSIMSG *PMSIMSG; +/** Pointer to a const MSI message struct. */ +typedef MSIMSG const *PCMSIMSG; #endif /* !VBOX_INCLUDED_msi_h */ Index: /trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp =================================================================== --- /trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (revision 84650) +++ /trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp (revision 84651) @@ -765,4 +765,8 @@ typedef IRTE_T const *PCIRTE_T; +/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI + * interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */ +#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff) + /** * Command: Generic Command Buffer Entry. @@ -1736,74 +1740,4 @@ /** - * MSI Address Register (PCI + MMIO). - * In accordance to the Intel spec. - * See Intel spec. 10.11.1 "Message Address Register Format". - * - * This also conforms to the AMD IOMMU spec. which omits specifying individual - * fields but specifies reserved bits. - */ -typedef union -{ - struct - { - uint32_t u2Ign0 : 2; /**< Bits 1:0 - Ignored (read as 0, writes ignored). */ - uint32_t u1DestMode : 1; /**< Bit 2 - DM: Destination Mode. */ - uint32_t u1RedirHint : 1; /**< Bit 3 - RH: Redirection Hint. */ - uint32_t u8Rsvd0 : 8; /**< Bits 11:4 - Reserved. */ - uint32_t u8DestId : 8; /**< Bits 19:12 - Destination Id. */ - uint32_t u12Addr : 12; /**< Bits 31:20 - Address. */ - uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */ - } n; - /** The 32-bit unsigned integer view. */ - uint32_t au32[2]; - /** The 64-bit unsigned integer view. */ - uint64_t u64; -} MSI_ADDR_T; -AssertCompileSize(MSI_ADDR_T, 8); -/** According to the AMD IOMMU spec. the top 32-bits are not reserved. From a - * PCI/IOMMU standpoint this makes sense. However, when dealing with the CPU side - * of things we might want to ensure the upper bits are reserved. Does x86/x64 - * really support a 64-bit MSI address? */ -#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc) -#define IOMMU_MSI_ADDR_ADDR_MASK UINT64_C(0x00000000fff00000) -/** Pointer to an MSI address register. */ -typedef MSI_ADDR_T *PMSI_ADDR_T; -/** Pointer to a const MSI address register. */ -typedef MSI_ADDR_T const *PCMSI_ADDR_T; - -/** - * MSI Data Register (PCI + MMIO). - * In accordance to the Intel spec. - * See Intel spec. 10.11.2 "Message Data Register Format". - * - * This also conforms to the AMD IOMMU spec. which omits specifying individual - * fields but specifies reserved bits. - */ -typedef union -{ - struct - { - uint32_t u8Vector : 8; /**< Bits 7:0 - Vector. */ - uint32_t u3DeliveryMode : 3; /**< Bits 10:8 - Delivery Mode. */ - uint32_t u3Rsvd0 : 3; /**< Bits 13:11 - Reserved. */ - uint32_t u1Level : 1; /**< Bit 14 - Level. */ - uint32_t u1TriggerMode : 1; /**< Bit 15 - Trigger Mode (0=edge, 1=level). */ - uint32_t u16Rsvd0 : 16; /**< Bits 31:16 - Reserved. */ - } n; - /** The 32-bit unsigned integer view. */ - uint32_t u32; -} MSI_DATA_T; -AssertCompileSize(MSI_DATA_T, 4); -#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff) -/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI - * interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */ -#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff) - -/** Pointer to an MSI data register. */ -typedef MSI_DATA_T *PMSI_DATA_T; -/** Pointer to a const MSI data register. */ -typedef MSI_DATA_T const *PCMSI_DATA_T; - -/** * MSI Mapping Capability Header Register (PCI + MMIO). * In accordance with the AMD spec. @@ -2311,19 +2245,4 @@ /** - * MSI Message (Address and Data Register Pair). - */ -typedef struct -{ - /** The MSI Address Register. */ - MSI_ADDR_T MsiAddr; - /** The MSI Data Register. */ - MSI_DATA_T MsiData; -} MSI_MSG_T; -/** Pointer to an MSI message struct. */ -typedef MSI_MSG_T *PMSI_MSG_T; -/** Pointer to a const MSI message struct. */ -typedef MSI_MSG_T const *PCMSI_MSG_T; - -/** * The shared IOMMU device state. */ @@ -2983,5 +2902,5 @@ PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); - PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK); + PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK); return VINF_SUCCESS; } @@ -3010,5 +2929,5 @@ PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0]; PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); - PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK); + PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK); return VINF_SUCCESS; } @@ -4640,4 +4559,5 @@ IOMMUOP enmOp, PRTGCPHYS pGCPhysOut, uint32_t *puDataOut) { + /** @todo Replace GCPhys[Out|In], uData[Out|In] with MSIMSG. */ Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP); @@ -4652,12 +4572,12 @@ if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO) { - MSI_ADDR_T MsiAddrIn; + MSIADDR MsiAddrIn; MsiAddrIn.u64 = GCPhysIn; - MSI_DATA_T MsiDataIn; + MSIDATA MsiDataIn; MsiDataIn.u32 = uDataIn; - PMSI_ADDR_T pMsiAddrOut = (PMSI_ADDR_T)pGCPhysOut; - PMSI_DATA_T pMsiDataOut = (PMSI_DATA_T)puDataOut; + PMSIADDR pMsiAddrOut = (PMSIADDR)pGCPhysOut; + PMSIDATA pMsiDataOut = (PMSIDATA)puDataOut; /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */ @@ -4760,9 +4680,9 @@ * See Intel spec. 10.11.1 "Message Address Register Format". */ - MSI_ADDR_T MsiAddrIn; + MSIADDR MsiAddrIn; MsiAddrIn.u64 = GCPhysIn; - if ((MsiAddrIn.u64 & IOMMU_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE) + if ((MsiAddrIn.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE) { - MSI_DATA_T MsiDataIn; + MSIDATA MsiDataIn; MsiDataIn.u32 = uDataIn; @@ -5610,5 +5530,5 @@ uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO); uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI); - MSI_ADDR_T MsiAddr; + MSIADDR MsiAddr; MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi); pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64); @@ -5624,5 +5544,5 @@ /* MSI Data. */ { - MSI_DATA_T MsiData; + MSIDATA MsiData; MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA); pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);