Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 81237)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 81238)
@@ -9239,7 +9239,5 @@
             &&  (u64GuestCr0 & X86_CR0_PG)
             && !(u64GuestCr0 & X86_CR0_PE))
-        {
             HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
-        }
 
         /*
@@ -9284,7 +9282,5 @@
         if (   !fLongModeGuest
             || !pCtx->cs.Attr.n.u1Long)
-        {
             HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
-        }
         /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
          *        must be identical if the "IA-32e mode guest" VM-entry
@@ -9324,7 +9320,5 @@
         if (   !fLongModeGuest
             && (u64GuestCr4 & X86_CR4_PCIDE))
-        {
             HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
-        }
 
         /** @todo CR3 field must be such that bits 63:52 and bits in the range
@@ -9333,7 +9327,5 @@
         if (   (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
             && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
-        {
             HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
-        }
 
         rc = VMXReadVmcsNw(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
@@ -9373,7 +9365,5 @@
                     && u8Val != 6 /* WB */
                     && u8Val != 7 /* UC- */)
-                {
                     HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
-                }
                 u64Val >>= 8;
             }
@@ -9434,7 +9424,6 @@
             if (   !(pCtx->cr0 & X86_CR0_PE)
                 || pCtx->cs.Attr.n.u4Type == 3)
-            {
                 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
-            }
+
             if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
             {
@@ -9589,14 +9578,10 @@
         HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
         if (fLongModeGuest)
-        {
             HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11,           /* 64-bit busy TSS. */
                               VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
-        }
         else
-        {
             HMVMX_CHECK_BREAK(   pCtx->tr.Attr.n.u4Type == 3          /* 16-bit busy TSS. */
                               || pCtx->tr.Attr.n.u4Type == 11,        /* 32-bit busy TSS.*/
                               VMX_IGS_TR_ATTR_TYPE_INVALID);
-        }
         HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
         HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
@@ -9644,7 +9629,5 @@
         if (   u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
             || u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
-        {
             HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
-        }
 
         /** @todo Activity state and injecting interrupts. Left as a todo since we
@@ -9683,8 +9666,5 @@
         if (   (pVmcsInfo->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
             && VMX_ENTRY_INT_INFO_IS_XCPT_NMI(u32EntryInfo))
-        {
-            HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI),
-                              VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
-        }
+            HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI), VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
 
         /* Pending debug exceptions. */