Index: /trunk/src/VBox/Devices/Audio/DevHDA.cpp
===================================================================
--- /trunk/src/VBox/Devices/Audio/DevHDA.cpp	(revision 80681)
+++ /trunk/src/VBox/Devices/Audio/DevHDA.cpp	(revision 80682)
@@ -4897,25 +4897,25 @@
 
     /* PCI Device */
-    PCIDevSetVendorId           (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
-    PCIDevSetDeviceId           (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
-
-    PCIDevSetCommand            (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
-    PCIDevSetStatus             (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
-    PCIDevSetRevisionId         (&pThis->PciDev, 0x01);   /* 08 ro - rid. */
-    PCIDevSetClassProg          (&pThis->PciDev, 0x00);   /* 09 ro - pi. */
-    PCIDevSetClassSub           (&pThis->PciDev, 0x03);   /* 0a ro - scc; 03 == HDA. */
-    PCIDevSetClassBase          (&pThis->PciDev, 0x04);   /* 0b ro - bcc; 04 == multimedia. */
-    PCIDevSetHeaderType         (&pThis->PciDev, 0x00);   /* 0e ro - headtyp. */
-    PCIDevSetBaseAddress        (&pThis->PciDev, 0,       /* 10 rw - MMIO */
+    PCIDevSetVendorId(      &pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
+    PCIDevSetDeviceId(      &pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
+
+    PCIDevSetCommand(       &pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
+    PCIDevSetStatus(        &pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
+    PCIDevSetRevisionId(    &pThis->PciDev, 0x01);   /* 08 ro - rid. */
+    PCIDevSetClassProg(     &pThis->PciDev, 0x00);   /* 09 ro - pi. */
+    PCIDevSetClassSub(      &pThis->PciDev, 0x03);   /* 0a ro - scc; 03 == HDA. */
+    PCIDevSetClassBase(     &pThis->PciDev, 0x04);   /* 0b ro - bcc; 04 == multimedia. */
+    PCIDevSetHeaderType(    &pThis->PciDev, 0x00);   /* 0e ro - headtyp. */
+    PCIDevSetBaseAddress(   &pThis->PciDev, 0,       /* 10 rw - MMIO */
                                  false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
-    PCIDevSetInterruptLine      (&pThis->PciDev, 0x00);   /* 3c rw. */
-    PCIDevSetInterruptPin       (&pThis->PciDev, 0x01);   /* 3d ro - INTA#. */
+    PCIDevSetInterruptLine( &pThis->PciDev, 0x00);   /* 3c rw. */
+    PCIDevSetInterruptPin(  &pThis->PciDev, 0x01);   /* 3d ro - INTA#. */
 
 #if defined(HDA_AS_PCI_EXPRESS)
-    PCIDevSetCapabilityList     (&pThis->PciDev, 0x80);
+    PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
 #elif defined(VBOX_WITH_MSI_DEVICES)
-    PCIDevSetCapabilityList     (&pThis->PciDev, 0x60);
+    PCIDevSetCapabilityList(&pThis->PciDev, 0x60);
 #else
-    PCIDevSetCapabilityList     (&pThis->PciDev, 0x50);   /* ICH6 datasheet 18.1.16 */
+    PCIDevSetCapabilityList(&pThis->PciDev, 0x50);   /* ICH6 datasheet 18.1.16 */
 #endif
 
@@ -4923,52 +4923,52 @@
     /// of these values needs to be properly documented!
     /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
-    PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
+    PCIDevSetByte(          &pThis->PciDev, 0x40, 0x01);
 
     /* Power Management */
-    PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
-    PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
-    PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
+    PCIDevSetByte(          &pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
+    PCIDevSetByte(          &pThis->PciDev, 0x50 + 1, 0x0); /* next */
+    PCIDevSetWord(          &pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
 
 #ifdef HDA_AS_PCI_EXPRESS
     /* PCI Express */
-    PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
-    PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
+    PCIDevSetByte(          &pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
+    PCIDevSetByte(          &pThis->PciDev, 0x80 + 1, 0x60); /* next */
     /* Device flags */
-    PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
-                   /* version */ 0x1     |
-                   /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
-                   /* MSI */ (100) << 9 );
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 2,
+                              1 /* version */
+                            | (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) /* Root Complex Integrated Endpoint */
+                            | (100 << 9) /* MSI */ );
     /* Device capabilities */
-    PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
+    PCIDevSetDWord(         &pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
     /* Device control */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 8, 0);
     /* Device status */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 10, 0);
     /* Link caps */
-    PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
+    PCIDevSetDWord(         &pThis->PciDev, 0x80 + 12, 0);
     /* Link control */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 16, 0);
     /* Link status */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 18, 0);
     /* Slot capabilities */
-    PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
+    PCIDevSetDWord(         &pThis->PciDev, 0x80 + 20, 0);
     /* Slot control */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 24, 0);
     /* Slot status */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 26, 0);
     /* Root control */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 28, 0);
     /* Root capabilities */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 30, 0);
     /* Root status */
-    PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
+    PCIDevSetDWord(         &pThis->PciDev, 0x80 + 32, 0);
     /* Device capabilities 2 */
-    PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
+    PCIDevSetDWord(         &pThis->PciDev, 0x80 + 36, 0);
     /* Device control 2 */
-    PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
+    PCIDevSetQWord(         &pThis->PciDev, 0x80 + 40, 0);
     /* Link control 2 */
-    PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
+    PCIDevSetQWord(         &pThis->PciDev, 0x80 + 48, 0);
     /* Slot control 2 */
-    PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
+    PCIDevSetWord(          &pThis->PciDev, 0x80 + 56, 0);
 #endif