Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 80539)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 80540)
@@ -3897,5 +3897,5 @@
  */
 IEM_STATIC VBOXSTRICTRC
-iemTaskSwitch(PVMCPUCC          pVCpu,
+iemTaskSwitch(PVMCPUCC        pVCpu,
               IEMTASKSWITCH   enmTaskSwitch,
               uint32_t        uNextEip,
@@ -3946,5 +3946,5 @@
      * task-switch VM-exit commences.
      *
-     * See Intel spec. 25.4.2 ".Treatment of Task Switches"
+     * See Intel spec. 25.4.2 "Treatment of Task Switches".
      */
     if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
@@ -3999,11 +3999,11 @@
      * and not the entire TSS.
      */
-    void     *pvNewTSS;
-    uint32_t  cbNewTSS    = uNewTSSLimitMin + 1;
-    RTGCPTR   GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);
+    void           *pvNewTSS;
+    uint32_t  const cbNewTSS    = uNewTSSLimitMin + 1;
+    RTGCPTR   const GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);
     AssertCompile(sizeof(X86TSS32) == X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
     /** @todo Handle if the TSS crosses a page boundary. Intel specifies that it may
      *        not perform correct translation if this happens. See Intel spec. 7.2.1
-     *        "Task-State Segment" */
+     *        "Task-State Segment". */
     VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvNewTSS, cbNewTSS, UINT8_MAX, GCPtrNewTSS, IEM_ACCESS_SYS_RW);
     if (rcStrict != VINF_SUCCESS)
@@ -4052,5 +4052,5 @@
      * Save the CPU state into the current TSS.
      */
-    RTGCPTR GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base;
+    RTGCPTR const GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base;
     if (GCPtrNewTSS == GCPtrCurTSS)
     {
@@ -4067,7 +4067,7 @@
          * See Intel spec. 7.2.1 "Task-State Segment (TSS)" for static and dynamic fields.
          */
-        void    *pvCurTSS32;
-        uint32_t offCurTSS = RT_UOFFSETOF(X86TSS32, eip);
-        uint32_t cbCurTSS  = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip);
+        void          *pvCurTSS32;
+        uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS32, eip);
+        uint32_t const cbCurTSS  = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip);
         AssertCompile(RTASSERT_OFFSET_OF(X86TSS32, selLdt) - RTASSERT_OFFSET_OF(X86TSS32, eip) == 64);
         rcStrict = iemMemMap(pVCpu, &pvCurTSS32, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
@@ -4111,7 +4111,7 @@
          * Verify that the current TSS (16-bit) can be accessed. Again, only the minimum required size.
          */
-        void    *pvCurTSS16;
-        uint32_t offCurTSS = RT_UOFFSETOF(X86TSS16, ip);
-        uint32_t cbCurTSS  = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip);
+        void          *pvCurTSS16;
+        uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS16, ip);
+        uint32_t const cbCurTSS  = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip);
         AssertCompile(RTASSERT_OFFSET_OF(X86TSS16, selLdt) - RTASSERT_OFFSET_OF(X86TSS16, ip) == 28);
         rcStrict = iemMemMap(pVCpu, &pvCurTSS16, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
@@ -4169,5 +4169,5 @@
     if (fIsNewTSS386)
     {
-        PX86TSS32 pNewTSS32 = (PX86TSS32)pvNewTSS;
+        PCX86TSS32 pNewTSS32 = (PCX86TSS32)pvNewTSS;
         uNewCr3       = (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG) ? pNewTSS32->cr3 : 0;
         uNewEip       = pNewTSS32->eip;
@@ -4192,5 +4192,5 @@
     else
     {
-        PX86TSS16 pNewTSS16 = (PX86TSS16)pvNewTSS;
+        PCX86TSS16 pNewTSS16 = (PCX86TSS16)pvNewTSS;
         uNewCr3       = 0;
         uNewEip       = pNewTSS16->ip;
@@ -4271,4 +4271,5 @@
     /* Set the busy bit in TR. */
     pVCpu->cpum.GstCtx.tr.Attr.n.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
+
     /* Set EFLAGS.NT (Nested Task) in the eflags loaded from the new TSS, if it's a task switch due to a CALL/INT_XCPT. */
     if (   enmTaskSwitch == IEMTASKSWITCH_CALL
@@ -4401,5 +4402,5 @@
         iemHlpLoadSelectorInV86Mode(&pVCpu->cpum.GstCtx.gs, uNewGS);
 
-        /* quick fix: fake DescSS. */ /** @todo fix the code further down? */
+        /* Quick fix: fake DescSS. */ /** @todo fix the code further down? */
         DescSS.Legacy.u = 0;
         DescSS.Legacy.Gen.u16LimitLow = (uint16_t)pVCpu->cpum.GstCtx.ss.u32Limit;
@@ -4413,5 +4414,5 @@
     else
     {
-        uint8_t uNewCpl = (uNewCS & X86_SEL_RPL);
+        uint8_t const uNewCpl = (uNewCS & X86_SEL_RPL);
 
         /*
@@ -4597,5 +4598,5 @@
     {
         Assert(enmTaskSwitch == IEMTASKSWITCH_INT_XCPT);
-        uint32_t cbLimitSS = X86DESC_LIMIT_G(&DescSS.Legacy);
+        uint32_t      cbLimitSS    = X86DESC_LIMIT_G(&DescSS.Legacy);
         uint8_t const cbStackFrame = fIsNewTSS386 ? 4 : 2;