VirtualBox

Changeset 80540 in vbox


Ignore:
Timestamp:
Sep 2, 2019 7:24:44 AM (5 years ago)
Author:
vboxsync
Message:

VMM/IEM: iemTaskSwitch const nits.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r80510 r80540  
    38973897 */
    38983898IEM_STATIC VBOXSTRICTRC
    3899 iemTaskSwitch(PVMCPUCC          pVCpu,
     3899iemTaskSwitch(PVMCPUCC        pVCpu,
    39003900              IEMTASKSWITCH   enmTaskSwitch,
    39013901              uint32_t        uNextEip,
     
    39463946     * task-switch VM-exit commences.
    39473947     *
    3948      * See Intel spec. 25.4.2 ".Treatment of Task Switches"
     3948     * See Intel spec. 25.4.2 "Treatment of Task Switches".
    39493949     */
    39503950    if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
     
    39993999     * and not the entire TSS.
    40004000     */
    4001     void     *pvNewTSS;
    4002     uint32_t  cbNewTSS    = uNewTSSLimitMin + 1;
    4003     RTGCPTR   GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);
     4001    void           *pvNewTSS;
     4002    uint32_t  const cbNewTSS    = uNewTSSLimitMin + 1;
     4003    RTGCPTR   const GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);
    40044004    AssertCompile(sizeof(X86TSS32) == X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
    40054005    /** @todo Handle if the TSS crosses a page boundary. Intel specifies that it may
    40064006     *        not perform correct translation if this happens. See Intel spec. 7.2.1
    4007      *        "Task-State Segment" */
     4007     *        "Task-State Segment". */
    40084008    VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvNewTSS, cbNewTSS, UINT8_MAX, GCPtrNewTSS, IEM_ACCESS_SYS_RW);
    40094009    if (rcStrict != VINF_SUCCESS)
     
    40524052     * Save the CPU state into the current TSS.
    40534053     */
    4054     RTGCPTR GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base;
     4054    RTGCPTR const GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base;
    40554055    if (GCPtrNewTSS == GCPtrCurTSS)
    40564056    {
     
    40674067         * See Intel spec. 7.2.1 "Task-State Segment (TSS)" for static and dynamic fields.
    40684068         */
    4069         void    *pvCurTSS32;
    4070         uint32_t offCurTSS = RT_UOFFSETOF(X86TSS32, eip);
    4071         uint32_t cbCurTSS  = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip);
     4069        void          *pvCurTSS32;
     4070        uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS32, eip);
     4071        uint32_t const cbCurTSS  = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip);
    40724072        AssertCompile(RTASSERT_OFFSET_OF(X86TSS32, selLdt) - RTASSERT_OFFSET_OF(X86TSS32, eip) == 64);
    40734073        rcStrict = iemMemMap(pVCpu, &pvCurTSS32, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
     
    41114111         * Verify that the current TSS (16-bit) can be accessed. Again, only the minimum required size.
    41124112         */
    4113         void    *pvCurTSS16;
    4114         uint32_t offCurTSS = RT_UOFFSETOF(X86TSS16, ip);
    4115         uint32_t cbCurTSS  = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip);
     4113        void          *pvCurTSS16;
     4114        uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS16, ip);
     4115        uint32_t const cbCurTSS  = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip);
    41164116        AssertCompile(RTASSERT_OFFSET_OF(X86TSS16, selLdt) - RTASSERT_OFFSET_OF(X86TSS16, ip) == 28);
    41174117        rcStrict = iemMemMap(pVCpu, &pvCurTSS16, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
     
    41694169    if (fIsNewTSS386)
    41704170    {
    4171         PX86TSS32 pNewTSS32 = (PX86TSS32)pvNewTSS;
     4171        PCX86TSS32 pNewTSS32 = (PCX86TSS32)pvNewTSS;
    41724172        uNewCr3       = (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG) ? pNewTSS32->cr3 : 0;
    41734173        uNewEip       = pNewTSS32->eip;
     
    41924192    else
    41934193    {
    4194         PX86TSS16 pNewTSS16 = (PX86TSS16)pvNewTSS;
     4194        PCX86TSS16 pNewTSS16 = (PCX86TSS16)pvNewTSS;
    41954195        uNewCr3       = 0;
    41964196        uNewEip       = pNewTSS16->ip;
     
    42714271    /* Set the busy bit in TR. */
    42724272    pVCpu->cpum.GstCtx.tr.Attr.n.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
     4273
    42734274    /* Set EFLAGS.NT (Nested Task) in the eflags loaded from the new TSS, if it's a task switch due to a CALL/INT_XCPT. */
    42744275    if (   enmTaskSwitch == IEMTASKSWITCH_CALL
     
    44014402        iemHlpLoadSelectorInV86Mode(&pVCpu->cpum.GstCtx.gs, uNewGS);
    44024403
    4403         /* quick fix: fake DescSS. */ /** @todo fix the code further down? */
     4404        /* Quick fix: fake DescSS. */ /** @todo fix the code further down? */
    44044405        DescSS.Legacy.u = 0;
    44054406        DescSS.Legacy.Gen.u16LimitLow = (uint16_t)pVCpu->cpum.GstCtx.ss.u32Limit;
     
    44134414    else
    44144415    {
    4415         uint8_t uNewCpl = (uNewCS & X86_SEL_RPL);
     4416        uint8_t const uNewCpl = (uNewCS & X86_SEL_RPL);
    44164417
    44174418        /*
     
    45974598    {
    45984599        Assert(enmTaskSwitch == IEMTASKSWITCH_INT_XCPT);
    4599         uint32_t cbLimitSS = X86DESC_LIMIT_G(&DescSS.Legacy);
     4600        uint32_t      cbLimitSS    = X86DESC_LIMIT_G(&DescSS.Legacy);
    46004601        uint8_t const cbStackFrame = fIsNewTSS386 ? 4 : 2;
    46014602
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