Changeset 80540 in vbox
- Timestamp:
- Sep 2, 2019 7:24:44 AM (5 years ago)
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (12 diffs)
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- Unmodified
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trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r80510 r80540 3897 3897 */ 3898 3898 IEM_STATIC VBOXSTRICTRC 3899 iemTaskSwitch(PVMCPUCC pVCpu,3899 iemTaskSwitch(PVMCPUCC pVCpu, 3900 3900 IEMTASKSWITCH enmTaskSwitch, 3901 3901 uint32_t uNextEip, … … 3946 3946 * task-switch VM-exit commences. 3947 3947 * 3948 * See Intel spec. 25.4.2 " .Treatment of Task Switches"3948 * See Intel spec. 25.4.2 "Treatment of Task Switches". 3949 3949 */ 3950 3950 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) … … 3999 3999 * and not the entire TSS. 4000 4000 */ 4001 void *pvNewTSS;4002 uint32_t c bNewTSS = uNewTSSLimitMin + 1;4003 RTGCPTR GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);4001 void *pvNewTSS; 4002 uint32_t const cbNewTSS = uNewTSSLimitMin + 1; 4003 RTGCPTR const GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy); 4004 4004 AssertCompile(sizeof(X86TSS32) == X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1); 4005 4005 /** @todo Handle if the TSS crosses a page boundary. Intel specifies that it may 4006 4006 * not perform correct translation if this happens. See Intel spec. 7.2.1 4007 * "Task-State Segment" */4007 * "Task-State Segment". */ 4008 4008 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvNewTSS, cbNewTSS, UINT8_MAX, GCPtrNewTSS, IEM_ACCESS_SYS_RW); 4009 4009 if (rcStrict != VINF_SUCCESS) … … 4052 4052 * Save the CPU state into the current TSS. 4053 4053 */ 4054 RTGCPTR GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base;4054 RTGCPTR const GCPtrCurTSS = pVCpu->cpum.GstCtx.tr.u64Base; 4055 4055 if (GCPtrNewTSS == GCPtrCurTSS) 4056 4056 { … … 4067 4067 * See Intel spec. 7.2.1 "Task-State Segment (TSS)" for static and dynamic fields. 4068 4068 */ 4069 void *pvCurTSS32;4070 uint32_t offCurTSS = RT_UOFFSETOF(X86TSS32, eip);4071 uint32_t c bCurTSS = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip);4069 void *pvCurTSS32; 4070 uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS32, eip); 4071 uint32_t const cbCurTSS = RT_UOFFSETOF(X86TSS32, selLdt) - RT_UOFFSETOF(X86TSS32, eip); 4072 4072 AssertCompile(RTASSERT_OFFSET_OF(X86TSS32, selLdt) - RTASSERT_OFFSET_OF(X86TSS32, eip) == 64); 4073 4073 rcStrict = iemMemMap(pVCpu, &pvCurTSS32, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW); … … 4111 4111 * Verify that the current TSS (16-bit) can be accessed. Again, only the minimum required size. 4112 4112 */ 4113 void *pvCurTSS16;4114 uint32_t offCurTSS = RT_UOFFSETOF(X86TSS16, ip);4115 uint32_t c bCurTSS = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip);4113 void *pvCurTSS16; 4114 uint32_t const offCurTSS = RT_UOFFSETOF(X86TSS16, ip); 4115 uint32_t const cbCurTSS = RT_UOFFSETOF(X86TSS16, selLdt) - RT_UOFFSETOF(X86TSS16, ip); 4116 4116 AssertCompile(RTASSERT_OFFSET_OF(X86TSS16, selLdt) - RTASSERT_OFFSET_OF(X86TSS16, ip) == 28); 4117 4117 rcStrict = iemMemMap(pVCpu, &pvCurTSS16, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW); … … 4169 4169 if (fIsNewTSS386) 4170 4170 { 4171 P X86TSS32 pNewTSS32 = (PX86TSS32)pvNewTSS;4171 PCX86TSS32 pNewTSS32 = (PCX86TSS32)pvNewTSS; 4172 4172 uNewCr3 = (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG) ? pNewTSS32->cr3 : 0; 4173 4173 uNewEip = pNewTSS32->eip; … … 4192 4192 else 4193 4193 { 4194 P X86TSS16 pNewTSS16 = (PX86TSS16)pvNewTSS;4194 PCX86TSS16 pNewTSS16 = (PCX86TSS16)pvNewTSS; 4195 4195 uNewCr3 = 0; 4196 4196 uNewEip = pNewTSS16->ip; … … 4271 4271 /* Set the busy bit in TR. */ 4272 4272 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK; 4273 4273 4274 /* Set EFLAGS.NT (Nested Task) in the eflags loaded from the new TSS, if it's a task switch due to a CALL/INT_XCPT. */ 4274 4275 if ( enmTaskSwitch == IEMTASKSWITCH_CALL … … 4401 4402 iemHlpLoadSelectorInV86Mode(&pVCpu->cpum.GstCtx.gs, uNewGS); 4402 4403 4403 /* quick fix: fake DescSS. */ /** @todo fix the code further down? */4404 /* Quick fix: fake DescSS. */ /** @todo fix the code further down? */ 4404 4405 DescSS.Legacy.u = 0; 4405 4406 DescSS.Legacy.Gen.u16LimitLow = (uint16_t)pVCpu->cpum.GstCtx.ss.u32Limit; … … 4413 4414 else 4414 4415 { 4415 uint8_t uNewCpl = (uNewCS & X86_SEL_RPL);4416 uint8_t const uNewCpl = (uNewCS & X86_SEL_RPL); 4416 4417 4417 4418 /* … … 4597 4598 { 4598 4599 Assert(enmTaskSwitch == IEMTASKSWITCH_INT_XCPT); 4599 uint32_t cbLimitSS= X86DESC_LIMIT_G(&DescSS.Legacy);4600 uint32_t cbLimitSS = X86DESC_LIMIT_G(&DescSS.Legacy); 4600 4601 uint8_t const cbStackFrame = fIsNewTSS386 ? 4 : 2; 4601 4602
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