Index: /trunk/src/VBox/Devices/Network/DevPCNet.cpp
===================================================================
--- /trunk/src/VBox/Devices/Network/DevPCNet.cpp	(revision 78457)
+++ /trunk/src/VBox/Devices/Network/DevPCNet.cpp	(revision 78458)
@@ -1604,8 +1604,13 @@
     CSR_CXST(pThis) = CSR_CXBC(pThis) = CSR_NXST(pThis) = CSR_NXBC(pThis) = 0;
 
-    LogRel(("PCnet#%d: Init: ss32=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
-            PCNET_INST_NR, BCR_SSIZE32(pThis),
+    LogRel(("PCnet#%d: Init: SWSTYLE=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
+            PCNET_INST_NR, BCR_SWSTYLE(pThis),
             pThis->GCRDRA, CSR_RCVRL(pThis), pThis->GCTDRA, CSR_XMTRL(pThis),
             !pThis->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""));
+
+    if (pThis->GCRDRA & (pThis->iLog2DescSize - 1))
+        LogRel(("PCnet#%d: Warning: Misaligned RDRA\n", PCNET_INST_NR));
+    if (pThis->GCTDRA & (pThis->iLog2DescSize - 1))
+        LogRel(("PCnet#%d: Warning: Misaligned TDRA\n", PCNET_INST_NR));
 
     pThis->aCSR[0] |=  0x0101;       /* Initialization done */
@@ -3033,4 +3038,6 @@
                 pThis->GCRDRA = (pThis->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
             Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCRDRA));
+            if (pThis->GCRDRA & (pThis->iLog2DescSize - 1))
+                LogRel(("PCnet#%d: Warning: Misaligned RDRA (GCRDRA=%#010x)\n", PCNET_INST_NR, pThis->GCRDRA));
             break;
 
@@ -3051,4 +3058,6 @@
                 pThis->GCTDRA = (pThis->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
             Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCTDRA));
+            if (pThis->GCTDRA & (pThis->iLog2DescSize - 1))
+                LogRel(("PCnet#%d: Warning: Misaligned TDRA (GCTDRA=%#010x)\n", PCNET_INST_NR, pThis->GCTDRA));
             break;