Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 78239)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 78240)
@@ -616,5 +616,5 @@
  * @param   pVCpu   The cross context virtual CPU structure.
  */
-DECL_FORCE_INLINE(uint64_t) hmR0VmxGetFixedCr0Mask(PVMCPU pVCpu)
+DECL_FORCE_INLINE(uint64_t) hmR0VmxGetFixedCr0Mask(PCVMCPU pVCpu)
 {
     /*
@@ -645,5 +645,5 @@
  * @param   pVCpu   The cross context virtual CPU structure.
  */
-DECL_FORCE_INLINE(uint64_t) hmR0VmxGetFixedCr4Mask(PVMCPU pVCpu)
+DECL_FORCE_INLINE(uint64_t) hmR0VmxGetFixedCr4Mask(PCVMCPU pVCpu)
 {
     /*
@@ -1147,8 +1147,8 @@
 
     /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
-    RTCCUINTREG fEFlags = ASMIntDisableFlags();
+    RTCCUINTREG const fEFlags = ASMIntDisableFlags();
 
     /* Enable the VMX bit in CR4 if necessary. */
-    RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
+    RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
 
     /* Enter VMX root mode. */
@@ -1157,5 +1157,5 @@
     {
         if (!(uOldCr4 & X86_CR4_VMXE))
-            SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
+            SUPR0ChangeCR4(0 /* fOrMask */, ~X86_CR4_VMXE);
 
         if (pVM)
@@ -1179,8 +1179,8 @@
 
     /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
-    RTCCUINTREG fEFlags = ASMIntDisableFlags();
+    RTCCUINTREG const fEFlags = ASMIntDisableFlags();
 
     /* If we're for some reason not in VMX root mode, then don't leave it. */
-    RTCCUINTREG uHostCR4 = ASMGetCR4();
+    RTCCUINTREG const uHostCR4 = ASMGetCR4();
 
     int rc;
@@ -1189,5 +1189,5 @@
         /* Exit VMX root mode and clear the VMX bit in CR4. */
         VMXDisable();
-        SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
+        SUPR0ChangeCR4(0 /* fOrMask */, ~X86_CR4_VMXE);
         rc = VINF_SUCCESS;
     }
@@ -1865,5 +1865,5 @@
  * @remarks No-long-jump zone!!!
  */
-static void hmR0VmxUpdateAutoLoadHostMsrs(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
+static void hmR0VmxUpdateAutoLoadHostMsrs(PCVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
 {
     PVMXAUTOMSR pHostMsrLoad = (PVMXAUTOMSR)pVmcsInfo->pvHostMsrLoad;
@@ -1927,5 +1927,5 @@
  * @param   idMsr       The MSR to check.
  */
-static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t idMsr)
+static bool hmR0VmxIsLazyGuestMsr(PCVMCPU pVCpu, uint32_t idMsr)
 {
     NOREF(pVCpu);
@@ -2118,5 +2118,5 @@
  * @param   pVmcsInfo   The VMCS info. object.
  */
-static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
+static void hmR0VmxCheckHostEferMsr(PCVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
 {
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -4164,5 +4164,5 @@
  * @remarks No-long-jump zone!!!
  */
-static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu)
+static bool hmR0VmxShouldSwapEferMsr(PCVMCPU pVCpu)
 {
 #ifdef HMVMX_ALWAYS_SWAP_EFER
@@ -4170,5 +4170,5 @@
     return true;
 #else
-    PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
+    PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
 #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
     /* For 32-bit hosts running 64-bit guests, we always swap EFER MSR in the world-switcher. Nothing to do here. */
@@ -6501,5 +6501,5 @@
     uint64_t     uTscOffset;
     PVM          pVM = pVCpu->CTX_SUFF(pVM);
-    PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);;
+    PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
 
     if (pVM->hm.s.vmx.fUsePreemptTimer)
@@ -9861,5 +9861,5 @@
  * @param   pVmcsInfoGst        The guest VMCS info. object.
  */
-static void hmR0VmxMergeMsrBitmapNested(PVMCPU pVCpu, PVMXVMCSINFO pVmcsInfoNstGst, PCVMXVMCSINFO pVmcsInfoGst)
+static void hmR0VmxMergeMsrBitmapNested(PCVMCPU pVCpu, PVMXVMCSINFO pVmcsInfoNstGst, PCVMXVMCSINFO pVmcsInfoGst)
 {
     uint64_t const *pu64MsrBitmapNstGst = (uint64_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap);
@@ -12801,5 +12801,5 @@
     AssertRCReturn(rc, rc);
 
-    uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
+    uint32_t const uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
     Assert(   !(pVmcsInfo->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
            && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
@@ -12834,6 +12834,6 @@
     }
 
-    uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
-    uint32_t uVector      = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
+    uint32_t const uExitIntInfo = pVmxTransient->uExitIntInfo;
+    uint32_t const uVector      = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
     switch (uIntType)
     {
@@ -14770,6 +14770,7 @@
 
     /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
-    uint64_t uDR6 = X86_DR6_INIT_VAL;
-    uDR6         |= (pVmxTransient->uExitQual & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
+    uint64_t const uDR6 = X86_DR6_INIT_VAL
+                        | (pVmxTransient->uExitQual & (  X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3
+                                                       | X86_DR6_BD | X86_DR6_BS));
 
     PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
@@ -14781,5 +14782,5 @@
          * The exception was for the guest.  Update DR6, DR7.GD and
          * IA32_DEBUGCTL.LBR before forwarding it.
-         * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
+         * See Intel spec. 27.1 "Architectural State before a VM-Exit".
          */
         VMMRZCallRing3Disable(pVCpu);