Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 78228)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 78229)
@@ -2741,8 +2741,10 @@
  *
  * @returns VBox status code.
+ * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pVmcsInfo   The VMCS info. object.
  */
-DECLINLINE(int) hmR0VmxSetupVmcsVirtApicAddr(PCVMXVMCSINFO pVmcsInfo)
-{
+DECLINLINE(int) hmR0VmxSetupVmcsVirtApicAddr(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
+{
+    NOREF(pVCpu);
     RTHCPHYS const HCPhysVirtApic = pVmcsInfo->HCPhysVirtApic;
     Assert(HCPhysVirtApic != NIL_RTHCPHYS);
@@ -2756,8 +2758,10 @@
  *
  * @returns VBox status code.
+ * @param   pVCpu       The cross context virtual CPU structure.
  * @param   pVmcsInfo   The VMCS info. object.
  */
-DECLINLINE(int) hmR0VmxSetupVmcsMsrBitmapAddr(PCVMXVMCSINFO pVmcsInfo)
-{
+DECLINLINE(int) hmR0VmxSetupVmcsMsrBitmapAddr(PVMCPU pVCpu, PCVMXVMCSINFO pVmcsInfo)
+{
+    NOREF(pVCpu);
     RTHCPHYS const HCPhysMsrBitmap = pVmcsInfo->HCPhysMsrBitmap;
     Assert(HCPhysMsrBitmap != NIL_RTHCPHYS);
@@ -2786,8 +2790,10 @@
  *
  * @returns VBox status code.
- * @param   pVmcsInfo       The VMCS info. object.
- */
-DECLINLINE(int) hmR0VmxSetupVmcsLinkPtr(PVMXVMCSINFO pVmcsInfo)
-{
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pVmcsInfo   The VMCS info. object.
+ */
+DECLINLINE(int) hmR0VmxSetupVmcsLinkPtr(PVMCPU pVCpu, PVMXVMCSINFO pVmcsInfo)
+{
+    NOREF(pVCpu);
     uint64_t const u64VmcsLinkPtr = pVmcsInfo->u64VmcsLinkPtr;
     Assert(u64VmcsLinkPtr == UINT64_C(0xffffffffffffffff));  /* Bits 63:0 MB1. */
@@ -2801,8 +2807,10 @@
  *
  * @returns VBox status code.
- * @param   pVmcsInfo       The VMCS info. object.
- */
-DECLINLINE(int) hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(PVMXVMCSINFO pVmcsInfo)
-{
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pVmcsInfo   The VMCS info. object.
+ */
+DECLINLINE(int) hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(PVMCPU pVCpu, PVMXVMCSINFO pVmcsInfo)
+{
+    NOREF(pVCpu);
     RTHCPHYS const HCPhysGuestMsrLoad = pVmcsInfo->HCPhysGuestMsrLoad;
     Assert(HCPhysGuestMsrLoad != NIL_RTHCPHYS);
@@ -3090,5 +3098,5 @@
         Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
         Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
-        int rc = hmR0VmxSetupVmcsVirtApicAddr(pVmcsInfo);
+        int rc = hmR0VmxSetupVmcsVirtApicAddr(pVCpu, pVmcsInfo);
         AssertRCReturn(rc, rc);
     }
@@ -3108,5 +3116,5 @@
     {
         fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
-        int rc = hmR0VmxSetupVmcsMsrBitmapAddr(pVmcsInfo);
+        int rc = hmR0VmxSetupVmcsMsrBitmapAddr(pVCpu, pVmcsInfo);
         AssertRCReturn(rc, rc);
     }
@@ -3161,9 +3169,9 @@
 {
     /* Set the auto-load/store MSR area addresses in the VMCS. */
-    int rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVmcsInfo);
+    int rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVCpu, pVmcsInfo);
     if (RT_SUCCESS(rc))
     {
         /* Set the VMCS link pointer in the VMCS. */
-        rc = hmR0VmxSetupVmcsLinkPtr(pVmcsInfo);
+        rc = hmR0VmxSetupVmcsLinkPtr(pVCpu, pVmcsInfo);
         if (RT_SUCCESS(rc))
         {
@@ -3628,5 +3636,44 @@
     return true;
 }
-# endif
+# endif /* VBOX_ENABLE_64_BITS_GUESTS */
+
+# ifdef VBOX_STRICT
+static bool hmR0VmxIsValidWriteField(uint32_t idxField)
+{
+    switch (idxField)
+    {
+        case VMX_VMCS_GUEST_RIP:
+        case VMX_VMCS_GUEST_RSP:
+        case VMX_VMCS_GUEST_SYSENTER_EIP:
+        case VMX_VMCS_GUEST_SYSENTER_ESP:
+        case VMX_VMCS_GUEST_GDTR_BASE:
+        case VMX_VMCS_GUEST_IDTR_BASE:
+        case VMX_VMCS_GUEST_CS_BASE:
+        case VMX_VMCS_GUEST_DS_BASE:
+        case VMX_VMCS_GUEST_ES_BASE:
+        case VMX_VMCS_GUEST_FS_BASE:
+        case VMX_VMCS_GUEST_GS_BASE:
+        case VMX_VMCS_GUEST_SS_BASE:
+        case VMX_VMCS_GUEST_LDTR_BASE:
+        case VMX_VMCS_GUEST_TR_BASE:
+        case VMX_VMCS_GUEST_CR3:
+            return true;
+    }
+    return false;
+}
+
+static bool hmR0VmxIsValidReadField(uint32_t idxField)
+{
+    switch (idxField)
+    {
+        /* Read-only fields. */
+        case VMX_VMCS_RO_EXIT_QUALIFICATION:
+            return true;
+    }
+    /* Remaining readable fields should also be writable. */
+    return hmR0VmxIsValidWriteField(idxField);
+}
+# endif /* VBOX_STRICT */
+
 
 /**
@@ -5930,5 +5977,5 @@
             if (pVmcsInfo->pfnStartVM != VMXR0StartVM32)
                 Log4Func(("Selected 32-bit switcher\n"));
-            pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
+            pVmcsInfo->pfnStartVM = VMXR0StartVM32;
         }
         else
@@ -6210,45 +6257,7 @@
 
 #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
-#ifndef VMX_USE_CACHED_VMCS_ACCESSES
-# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
-#endif
-#ifdef VBOX_STRICT
-static bool hmR0VmxIsValidWriteField(uint32_t idxField)
-{
-    switch (idxField)
-    {
-        case VMX_VMCS_GUEST_RIP:
-        case VMX_VMCS_GUEST_RSP:
-        case VMX_VMCS_GUEST_SYSENTER_EIP:
-        case VMX_VMCS_GUEST_SYSENTER_ESP:
-        case VMX_VMCS_GUEST_GDTR_BASE:
-        case VMX_VMCS_GUEST_IDTR_BASE:
-        case VMX_VMCS_GUEST_CS_BASE:
-        case VMX_VMCS_GUEST_DS_BASE:
-        case VMX_VMCS_GUEST_ES_BASE:
-        case VMX_VMCS_GUEST_FS_BASE:
-        case VMX_VMCS_GUEST_GS_BASE:
-        case VMX_VMCS_GUEST_SS_BASE:
-        case VMX_VMCS_GUEST_LDTR_BASE:
-        case VMX_VMCS_GUEST_TR_BASE:
-        case VMX_VMCS_GUEST_CR3:
-            return true;
-    }
-    return false;
-}
-
-static bool hmR0VmxIsValidReadField(uint32_t idxField)
-{
-    switch (idxField)
-    {
-        /* Read-only fields. */
-        case VMX_VMCS_RO_EXIT_QUALIFICATION:
-            return true;
-    }
-    /* Remaining readable fields should also be writable. */
-    return hmR0VmxIsValidWriteField(idxField);
-}
-#endif /* VBOX_STRICT */
-
+# ifndef VMX_USE_CACHED_VMCS_ACCESSES
+#  error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
+# endif
 
 /**