Index: /trunk/include/VBox/vmm/iem.h
===================================================================
--- /trunk/include/VBox/vmm/iem.h	(revision 75956)
+++ /trunk/include/VBox/vmm/iem.h	(revision 75957)
@@ -329,5 +329,5 @@
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVirtApicAccessMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
-VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVirtApicWriteEmulation(PVMCPU pVCpu);
+VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVmexitApicWrite(PVMCPU pVCpu);
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVmexitPreemptTimer(PVMCPU pVCpu);
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending);
Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 75956)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 75957)
@@ -15716,5 +15716,6 @@
 
 /**
- * Interface for HM and EM to perform a APIC-write emulation.
+ * Interface for HM and EM to perform an APIC-write emulation which may cause a
+ * VM-exit.
  *
  * @returns Strict VBox status code.
@@ -15722,5 +15723,5 @@
  * @thread  EMT(pVCpu)
  */
-VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicWriteEmulation(PVMCPU pVCpu)
+VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPU pVCpu)
 {
     IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
Index: /trunk/src/VBox/VMM/VMMR3/EM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/EM.cpp	(revision 75956)
+++ /trunk/src/VBox/VMM/VMMR3/EM.cpp	(revision 75957)
@@ -2111,5 +2111,20 @@
         }
 
-        /* SMIs take priority over if we ever support them will have to be injected here. */
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+        /*
+         * VMX Nested-guest APIC-write VM-exit.
+         * Takes priority over SMI, INIT signals.
+         * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
+         */
+        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
+        {
+            rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexitApicWrite(pVCpu));
+            if (rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE)
+                UPDATE_RC();
+        }
+#endif
+
+        /** @todo SMIs. If we implement SMIs, this is where they will have to be
+         *        delivered. */
 
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
@@ -2138,6 +2153,4 @@
 #endif
 
-        /** @todo Enable when I get time to test this specific code path later. */
-#if 0
         /*
          * NMIs.
@@ -2162,11 +2175,10 @@
                 }
             }
-        }
-#endif
+            UPDATE_RC();
+        }
 
         /*
          * Interrupts.
          */
-        bool fWakeupPending = false;
         if (   !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)
             && (!rc || rc >= VINF_EM_RESCHEDULE_HM)