VirtualBox

Changeset 75611 in vbox


Ignore:
Timestamp:
Nov 20, 2018 11:20:25 AM (6 years ago)
Author:
vboxsync
Message:

VMM: Nested VMX: bugref:9180 Move the VMX APIC-access guest-physical page registration into IEM and got rid of the CPUM all context code that does not quite fit because we still have to declare the prototypes in the HM headers anyway, so just keep it in HM all context code for now.

Location:
trunk
Files:
2 deleted
16 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.h

    r75507 r75611  
    20712071VMMDECL(void)           CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
    20722072
    2073 /** @name SVM helpers.
    2074  * @{ */
    2075 VMM_INT_DECL(int)       CPUMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
    2076 VMM_INT_DECL(bool)      CPUMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
    2077                                                    uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
    2078                                                    PSVMIOIOEXITINFO pIoExitInfo);
    2079 /** @} */
    2080 
    2081 /** @name VMX helpers.
    2082  * @{ */
    2083 VMM_INT_DECL(int)       CPUMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
    2084                                                 PVMXMSREXITWRITE penmWrite);
    2085 VMM_INT_DECL(bool)      CPUMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort,
    2086                                                      uint8_t cbAccess);
    2087 VMM_INT_DECL(int)       CPUMVmxApicAccessPageRegister(PVMCPU pVCpu, RTGCPHYS GCPhysApicAccess);
    2088 VMM_INT_DECL(int)       CPUMVmxApicAccessPageDeregister(PVMCPU pVCpu, RTGCPHYS GCPhysApicAccess);
    2089 /** @} */
    2090 
    20912073/** @name Changed flags.
    20922074 * These flags are used to keep track of which important register that

  • trunk/include/VBox/vmm/hm_svm.h

    r73286 r75611  
    11341134    } while (0)
    11351135
    1136 /*
     1136
     1137/** @defgroup grp_hm_svm_c    SVM C Helpers
     1138 *
     1139 * These are functions that strictly only implement SVM functionality that is in
     1140 * accordance to the SVM spec. and thus fit to use by IEM/REM/HM.
     1141 *
     1142 * These are not HM all-context API functions, those are to be placed in hm.h.
     1143 * @{
     1144 */
     1145VMM_INT_DECL(int)       HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
     1146VMM_INT_DECL(bool)      HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
     1147                                                 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
     1148                                                 PSVMIOIOEXITINFO pIoExitInfo);
     1149/** @} */
     1150
     1151
     1152/** @defgroup grp_hm_svm_hwexec    SVM Hardware-assisted execution Helpers
     1153 *
    11371154 * These functions are only here because the inline functions in cpum.h calls them.
    11381155 * Don't add any more functions here unless there is no other option.
     1156 * @{
    11391157 */
    11401158VMM_INT_DECL(bool)     HMHasGuestSvmVmcbCached(PVMCPU pVCpu);
    … …  
    11481166VMM_INT_DECL(bool)     HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu);
    11491167VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu);
    1150 
    11511168/** @} */
    11521169
     1170
     1171/** @} */
     1172
    11531173#endif
    11541174

  • trunk/include/VBox/vmm/hm_vmx.h

    r75493 r75611  
    41914191
    41924192
     4193/** @defgroup grp_hm_vmx_c    VMX Assembly Helpers
     4194 *
     4195 * These are functions that strictly only implement VT-x functionality that is in
     4196 * accordance to the VT-X spec. and thus fit to use by IEM/REM/HM.
     4197 *
     4198 * These are not HM all-context API functions, those are to be placed in hm.h.
     4199 * @{
     4200 */
     4201VMM_INT_DECL(int)   HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
     4202                                          PVMXMSREXITWRITE penmWrite);
     4203VMM_INT_DECL(bool)  HMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort,
     4204                                               uint8_t cbAccess);
     4205/** @} */
     4206
     4207
    41934208/** @defgroup grp_hm_vmx_asm    VMX Assembly Helpers
    41944209 * @{

  • trunk/include/VBox/vmm/iem.h

    r75565 r75611  
    329329#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
    330330VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVirtApicAccessMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
    331 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
    332                                                         bool fWrite);
    333331VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVirtApicUpdate(PVMCPU pVCpu);
    334332VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVmexitPreemptTimer(PVMCPU pVCpu);

  • trunk/src/VBox/VMM/Makefile.kmk

    r75440 r75611  
    171171        VMMAll/CPUMAllRegs.cpp \
    172172        VMMAll/CPUMAllMsrs.cpp \
    173         VMMAll/CPUMAllSvm.cpp \
    174         VMMAll/CPUMAllVmx.cpp \
    175173        VMMAll/CPUMStack.cpp \
    176174        VMMAll/DBGFAll.cpp \
    … …  
    562560        VMMAll/CPUMAllRegs.cpp \
    563561        VMMAll/CPUMAllMsrs.cpp \
    564         VMMAll/CPUMAllSvm.cpp \
    565         VMMAll/CPUMAllVmx.cpp \
    566562        VMMAll/DBGFAll.cpp \
    567563        VMMAll/IEMAll.cpp \
    … …  
    715711        VMMAll/CPUMAllRegs.cpp \
    716712        VMMAll/CPUMAllMsrs.cpp \
    717         VMMAll/CPUMAllSvm.cpp \
    718         VMMAll/CPUMAllVmx.cpp \
    719713        VMMAll/CPUMStack.cpp \
    720714        VMMAll/DBGFAll.cpp \

  • trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp

    r75440 r75611  
    297297#endif /* !IN_RC */
    298298
     299/**
     300 * Gets the MSR permission bitmap byte and bit offset for the specified MSR.
     301 *
     302 * @returns VBox status code.
     303 * @param   idMsr       The MSR being requested.
     304 * @param   pbOffMsrpm  Where to store the byte offset in the MSR permission
     305 *                      bitmap for @a idMsr.
     306 * @param   puMsrpmBit  Where to store the bit offset starting at the byte
     307 *                      returned in @a pbOffMsrpm.
     308 */
     309VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit)
     310{
     311    Assert(pbOffMsrpm);
     312    Assert(puMsrpmBit);
     313
     314    /*
     315     * MSRPM Layout:
     316     * Byte offset          MSR range
     317     * 0x000  - 0x7ff       0x00000000 - 0x00001fff
     318     * 0x800  - 0xfff       0xc0000000 - 0xc0001fff
     319     * 0x1000 - 0x17ff      0xc0010000 - 0xc0011fff
     320     * 0x1800 - 0x1fff              Reserved
     321     *
     322     * Each MSR is represented by 2 permission bits (read and write).
     323     */
     324    if (idMsr <= 0x00001fff)
     325    {
     326        /* Pentium-compatible MSRs. */
     327        uint32_t const bitoffMsr = idMsr << 1;
     328        *pbOffMsrpm = bitoffMsr >> 3;
     329        *puMsrpmBit = bitoffMsr & 7;
     330        return VINF_SUCCESS;
     331    }
     332
     333    if (   idMsr >= 0xc0000000
     334        && idMsr <= 0xc0001fff)
     335    {
     336        /* AMD Sixth Generation x86 Processor MSRs. */
     337        uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
     338        *pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
     339        *puMsrpmBit = bitoffMsr & 7;
     340        return VINF_SUCCESS;
     341    }
     342
     343    if (   idMsr >= 0xc0010000
     344        && idMsr <= 0xc0011fff)
     345    {
     346        /* AMD Seventh and Eighth Generation Processor MSRs. */
     347        uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
     348        *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
     349        *puMsrpmBit = bitoffMsr & 7;
     350        return VINF_SUCCESS;
     351    }
     352
     353    *pbOffMsrpm = 0;
     354    *puMsrpmBit = 0;
     355    return VERR_OUT_OF_RANGE;
     356}
     357
     358
     359/**
     360 * Determines whether an IOIO intercept is active for the nested-guest or not.
     361 *
     362 * @param   pvIoBitmap      Pointer to the nested-guest IO bitmap.
     363 * @param   u16Port         The IO port being accessed.
     364 * @param   enmIoType       The type of IO access.
     365 * @param   cbReg           The IO operand size in bytes.
     366 * @param   cAddrSizeBits   The address size bits (for 16, 32 or 64).
     367 * @param   iEffSeg         The effective segment number.
     368 * @param   fRep            Whether this is a repeating IO instruction (REP prefix).
     369 * @param   fStrIo          Whether this is a string IO instruction.
     370 * @param   pIoExitInfo     Pointer to the SVMIOIOEXITINFO struct to be filled.
     371 *                          Optional, can be NULL.
     372 */
     373VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
     374                                            uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
     375                                            PSVMIOIOEXITINFO pIoExitInfo)
     376{
     377    Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
     378    Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
     379
     380    /*
     381     * The IOPM layout:
     382     * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
     383     * two 4K pages.
     384     *
     385     * For IO instructions that access more than a single byte, the permission bits
     386     * for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
     387     *
     388     * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
     389     * we need 3 extra bits beyond the second 4K page.
     390     */
     391    static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
     392
     393    uint16_t const offIopm   = u16Port >> 3;
     394    uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
     395    uint8_t  const cShift    = u16Port - (offIopm << 3);
     396    uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift);
     397
     398    uint8_t const *pbIopm = (uint8_t *)pvIoBitmap;
     399    Assert(pbIopm);
     400    pbIopm += offIopm;
     401    uint16_t const u16Iopm = *(uint16_t *)pbIopm;
     402    if (u16Iopm & fIopmMask)
     403    {
     404        if (pIoExitInfo)
     405        {
     406            static const uint32_t s_auIoOpSize[] =
     407            { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
     408
     409            static const uint32_t s_auIoAddrSize[] =
     410            { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
     411
     412            pIoExitInfo->u         = s_auIoOpSize[cbReg & 7];
     413            pIoExitInfo->u        |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
     414            pIoExitInfo->n.u1Str   = fStrIo;
     415            pIoExitInfo->n.u1Rep   = fRep;
     416            pIoExitInfo->n.u3Seg   = iEffSeg & 7;
     417            pIoExitInfo->n.u1Type  = enmIoType;
     418            pIoExitInfo->n.u16Port = u16Port;
     419        }
     420        return true;
     421    }
     422
     423    /** @todo remove later (for debugging as VirtualBox always traps all IO
     424     *        intercepts). */
     425    AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
     426    return false;
     427}
     428
    299429
    300430/**

  • trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp

    r75493 r75611  
    880880}
    881881
     882
     883/**
     884 * Gets the permission bits for the specified MSR in the specified MSR bitmap.
     885 *
     886 * @returns VBox status code.
     887 * @param   pvMsrBitmap     Pointer to the MSR bitmap.
     888 * @param   idMsr           The MSR.
     889 * @param   penmRead        Where to store the read permissions. Optional, can be
     890 *                          NULL.
     891 * @param   penmWrite       Where to store the write permissions. Optional, can be
     892 *                          NULL.
     893 */
     894VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
     895                                        PVMXMSREXITWRITE penmWrite)
     896{
     897    AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER);
     898
     899    int32_t iBit;
     900    uint8_t const *pbMsrBitmap = (uint8_t *)pvMsrBitmap;
     901
     902    /*
     903     * MSR Layout:
     904     *   Byte index            MSR range            Interpreted as
     905     * 0x000 - 0x3ff    0x00000000 - 0x00001fff    Low MSR read bits.
     906     * 0x400 - 0x7ff    0xc0000000 - 0xc0001fff    High MSR read bits.
     907     * 0x800 - 0xbff    0x00000000 - 0x00001fff    Low MSR write bits.
     908     * 0xc00 - 0xfff    0xc0000000 - 0xc0001fff    High MSR write bits.
     909     *
     910     * A bit corresponding to an MSR within the above range causes a VM-exit
     911     * if the bit is 1 on executions of RDMSR/WRMSR.
     912     *
     913     * If an MSR falls out of the MSR range, it always cause a VM-exit.
     914     *
     915     * See Intel spec. 24.6.9 "MSR-Bitmap Address".
     916     */
     917    if (idMsr <= 0x00001fff)
     918        iBit = idMsr;
     919    else if (   idMsr >= 0xc0000000
     920             && idMsr <= 0xc0001fff)
     921    {
     922        iBit = (idMsr - 0xc0000000);
     923        pbMsrBitmap += 0x400;
     924    }
     925    else
     926    {
     927        if (penmRead)
     928            *penmRead = VMXMSREXIT_INTERCEPT_READ;
     929        if (penmWrite)
     930            *penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
     931        Log(("CPUMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr));
     932        return VINF_SUCCESS;
     933    }
     934
     935    /* Validate the MSR bit position. */
     936    Assert(iBit <= 0x1fff);
     937
     938    /* Get the MSR read permissions. */
     939    if (penmRead)
     940    {
     941        if (ASMBitTest(pbMsrBitmap, iBit))
     942            *penmRead = VMXMSREXIT_INTERCEPT_READ;
     943        else
     944            *penmRead = VMXMSREXIT_PASSTHRU_READ;
     945    }
     946
     947    /* Get the MSR write permissions. */
     948    if (penmWrite)
     949    {
     950        if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
     951            *penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
     952        else
     953            *penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
     954    }
     955
     956    return VINF_SUCCESS;
     957}
     958
     959
     960/**
     961 * Gets the permission bits for the specified I/O port from the given I/O bitmaps.
     962 *
     963 * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
     964 * @param   pvIoBitmapA     Pointer to I/O bitmap A.
     965 * @param   pvIoBitmapB     Pointer to I/O bitmap B.
     966 * @param   uPort           The I/O port being accessed.
     967 * @param   cbAccess        The size of the I/O access in bytes (1, 2 or 4 bytes).
     968 */
     969VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort,
     970                                                uint8_t cbAccess)
     971{
     972    Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
     973
     974    /*
     975     * If the I/O port access wraps around the 16-bit port I/O space,
     976     * we must cause a VM-exit.
     977     *
     978     * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
     979     */
     980    /** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
     981     *        respectively are valid and do not constitute a wrap around from what I
     982     *        understand. Verify this later. */
     983    uint32_t const uPortLast = uPort + cbAccess;
     984    if (uPortLast > 0x10000)
     985        return true;
     986
     987    /* Read the appropriate bit from the corresponding IO bitmap. */
     988    void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
     989    return ASMBitTest(pvIoBitmap, uPort);
     990}
     991

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r75565 r75611  
    1604716047}
    1604816048
    16049 #endif
     16049
     16050/**
     16051 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
     16052 *
     16053 * @remarks The @a pvUser argument is currently unused.
     16054 */
     16055PGM_ALL_CB2_DECL(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
     16056                                                           void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
     16057                                                           PGMACCESSORIGIN enmOrigin, void *pvUser)
     16058{
     16059    RT_NOREF4(pVM, pvPhys, enmOrigin, pvUser);
     16060
     16061    Assert(CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)));
     16062    Assert(CPUMIsGuestVmxProcCtls2Set(pVCpu, IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
     16063
     16064#ifdef VBOX_STRICT
     16065    RTGCPHYS const GCPhysApicBase   = CPUMGetGuestVmxApicAccessPageAddr(pVCpu, IEM_GET_CTX(pVCpu));
     16066    RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
     16067    Assert(GCPhysApicBase == GCPhysAccessBase);
     16068#endif
     16069
     16070    uint16_t const offAccess = GCPhysFault & PAGE_OFFSET_MASK;
     16071    uint32_t const fAccess   = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_TYPE_WRITE : IEM_ACCESS_TYPE_READ;
     16072
     16073    VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
     16074    if (RT_FAILURE(rcStrict))
     16075        return rcStrict;
     16076
     16077    /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
     16078    return VINF_SUCCESS;
     16079}
     16080
     16081#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
    1605016082
    1605116083#ifdef IN_RING3

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h

    r75440 r75611  
    985985    SVMIOIOEXITINFO IoExitInfo;
    986986    void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
    987     bool const fIntercept = CPUMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep,
     987    bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep,
    988988                                                       fStrIo, &IoExitInfo);
    989989    if (fIntercept)
    … …  
    10341034    uint16_t offMsrpm;
    10351035    uint8_t  uMsrpmBit;
    1036     int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
     1036    int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
    10371037    if (RT_SUCCESS(rc))
    10381038    {

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

    r75565 r75611  
    27292729    PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
    27302730    bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
    2731     bool const fVirtApicAccess = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
    27322731
    27332732    /* We cannot return from a long-mode guest to a host that is not in long mode. */
    … …  
    27572756
    27582757    /* De-register the handler for the APIC-access page. */
    2759     if (fVirtApicAccess)
    2760     {
     2758    if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     2759    {
     2760        PVM pVM = pVCpu->CTX_SUFF(pVM);
    27612761        RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
    2762         int rc = CPUMVmxApicAccessPageDeregister(pVCpu, GCPhysApicAccess);
    2763         if (RT_FAILURE(rc))
    2764             return rc;
     2762        if (PGMHandlerPhysicalIsRegistered(pVM, GCPhysApicAccess))
     2763        {
     2764            /** @todo NSTVMX: This is broken! We cannot simply deregister the handler for the
     2765             *        physical address as other VCPUs executing other nested-VCPUs might have
     2766             *        it registered! */
     2767            int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysApicAccess);
     2768            if (RT_FAILURE(rc))
     2769                return rc;
     2770        }
    27652771    }
    27662772
    … …  
    30443050        Assert(pbIoBitmapA);
    30453051        Assert(pbIoBitmapB);
    3046         return CPUMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
     3052        return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
    30473053    }
    30483054
    … …  
    63346340
    63356341        /* Register the handler for the APIC-access page. */
    6336         int rc = CPUMVmxApicAccessPageRegister(pVCpu, GCPhysApicAccess);
     6342        int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
     6343                                            pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
     6344                                            NIL_RTR0PTR /* pvUserR0 */,  NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
    63376345        if (RT_FAILURE(rc))
    63386346            IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
    … …  
    70577065        {
    70587066            VMXMSREXITREAD enmRead;
    7059             int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
     7067            int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
    70607068                                             NULL /* penmWrite */);
    70617069            AssertRC(rc);
    … …  
    70667074        {
    70677075            VMXMSREXITWRITE enmWrite;
    7068             int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
     7076            int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
    70697077                                             &enmWrite);
    70707078            AssertRC(rc);

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r75440 r75611  
    872872    uint16_t    offMsrpm;
    873873    uint8_t     uMsrpmBit;
    874     int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
     874    int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
    875875    AssertRC(rc);
    876876
    … …  
    51565156    const bool        fStrIo        = pIoExitInfo->n.u1Str;
    51575157
    5158     return CPUMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
     5158    return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
    51595159                                      NULL /* pIoExitInfo */);
    51605160}
    … …  
    52485248                uint16_t offMsrpm;
    52495249                uint8_t  uMsrpmBit;
    5250                 int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
     5250                int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
    52515251                if (RT_SUCCESS(rc))
    52525252                {

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r75440 r75611  
    17381738            VMXMSREXITREAD  enmRead;
    17391739            VMXMSREXITWRITE enmWrite;
    1740             rc = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite);
     1740            rc = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite);
    17411741            AssertMsgReturnVoid(rc == VINF_SUCCESS, ("HMVmxGetMsrPermission! failed. rc=%Rrc\n", rc));
    17421742            if (pGuestMsr->u32Msr == MSR_K6_EFER)
    … …  
    1196311963            VMXMSREXITREAD  enmRead;
    1196411964            VMXMSREXITWRITE enmWrite;
    11965             int rc2 = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
     11965            int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
    1196611966            AssertRCReturn(rc2, rc2);
    1196711967            if (enmRead == VMXMSREXIT_PASSTHRU_READ)
    … …  
    1210812108                        VMXMSREXITREAD  enmRead;
    1210912109                        VMXMSREXITWRITE enmWrite;
    12110                         int rc2 = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
     12110                        int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
    1211112111                        AssertRCReturn(rc2, rc2);
    1211212112                        if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r75493 r75611  
    36423642            /* Register statistic counters for MSRs. */
    36433643            cpumR3MsrRegStats(pVM);
    3644 
    3645 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
    3646             /* Register VMX APIC-access page handler type. */
    3647             if (pVM->cpum.s.GuestFeatures.fVmx)
    3648             {
    3649                 int rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, cpumVmxApicAccessPageHandler,
    3650                                                           NULL /* pszModR0 */,
    3651                                                           "cpumVmxApicAccessPageHandler", NULL /* pszPfHandlerR0 */,
    3652                                                           NULL /* pszModRC */,
    3653                                                           NULL /* pszHandlerRC */, NULL /* pszPfHandlerRC */,
    3654                                                           "VMX APIC-access page", &pVM->cpum.s.hVmxApicAccessPage);
    3655                 AssertRCReturn(rc, rc);
    3656             }
    3657 #endif
    36583644            break;
    36593645        }

  • trunk/src/VBox/VMM/VMMR3/IEMR3.cpp

    r72494 r75611  
    169169            pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
    170170    }
     171
     172#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
     173    /*
     174     * Register the per-VM VMX APIC-access page handler type.
     175     */
     176    if (pVM->cpum.ro.GuestFeatures.fVmx)
     177    {
     178        PVMCPU pVCpu0 = &pVM->aCpus[0];
     179        int rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, iemVmxApicAccessPageHandler,
     180                                                  NULL /* pszModR0 */,
     181                                                  "iemVmxApicAccessPageHandler", NULL /* pszPfHandlerR0 */,
     182                                                  NULL /* pszModRC */,
     183                                                  NULL /* pszHandlerRC */, NULL /* pszPfHandlerRC */,
     184                                                  "VMX APIC-access page", &pVCpu0->iem.s.hVmxApicAccessPage);
     185        AssertLogRelRCReturn(rc, rc);
     186    }
     187#endif
     188
    171189    return VINF_SUCCESS;
    172190}

  • trunk/src/VBox/VMM/include/CPUMInternal.h

    r75493 r75611  
    410410    /** The host MXCSR mask (determined at init). */
    411411    uint32_t                fHostMxCsrMask;
    412 
    413     /** The VMX APIC-access page handler type. */
    414     PGMPHYSHANDLERTYPE      hVmxApicAccessPage;
    415     uint8_t                 abPadding1[16];
     412    uint8_t                 abPadding1[20];
    416413
    417414    /** Host CPU feature information.
    … …  
    423420    /** Guest CPU info. */
    424421    CPUMINFO                GuestInfo;
    425 
    426422
    427423    /** The standard set of CpuId leaves. */
    … …  
    531527PCPUMCPUIDLEAF      cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
    532528PCPUMCPUIDLEAF      cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
    533 # ifdef VBOX_WITH_NESTED_HWVIRT_VMX
    534 PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) cpumVmxApicAccessPageHandler;
    535 # endif
    536529
    537530# ifdef IN_RING3

  • trunk/src/VBox/VMM/include/IEMInternal.h

    r73555 r75611  
    2121#include <VBox/vmm/cpum.h>
    2222#include <VBox/vmm/iem.h>
     23#include <VBox/vmm/pgm.h>
    2324#include <VBox/vmm/stam.h>
    2425#include <VBox/param.h>
    … …  
    558559    /** The CR2 for the current exception / interrupt. */
    559560    uint64_t                uCurXcptCr2;
     561    /** The VMX APIC-access page handler type. */
     562    PGMPHYSHANDLERTYPE      hVmxApicAccessPage;
    560563
    561564    /** @name Statistics
    … …  
    582585    /** Number of long jumps. */
    583586    uint32_t                cLongJumps;
    584     uint32_t                uAlignment6; /**< Alignment padding. */
    585587    /** @} */
    586588
    … …  
    928930} IEMACCESSCRX;
    929931
     932# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
     933PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
     934# endif
    930935
    931936/**
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