Index: /trunk/include/VBox/vmm/cpum.h =================================================================== --- /trunk/include/VBox/vmm/cpum.h (revision 75439) +++ /trunk/include/VBox/vmm/cpum.h (revision 75440) @@ -32,4 +32,6 @@ #include #include +#include +#include RT_C_DECLS_BEGIN @@ -2069,4 +2071,20 @@ VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl); +/** @name SVM helpers. + * @{ */ +VMM_INT_DECL(int) CPUMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit); +VMM_INT_DECL(bool) CPUMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg, + uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, + PSVMIOIOEXITINFO pIoExitInfo); +/** @} */ + +/** @name VMX helpers. + * @{ */ +VMM_INT_DECL(int) CPUMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead, + PVMXMSREXITWRITE penmWrite); +VMM_INT_DECL(bool) CPUMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort, + uint8_t cbAccess); +/** @} */ + /** @name Changed flags. * These flags are used to keep track of which important register that Index: /trunk/include/VBox/vmm/hm.h =================================================================== --- /trunk/include/VBox/vmm/hm.h (revision 75439) +++ /trunk/include/VBox/vmm/hm.h (revision 75440) @@ -141,7 +141,8 @@ /** @name All-context VMX helpers. - * These are VMX functions (based on VMX specs.) that may be used by IEM/REM and - * not VirtualBox functions that are used for hardware-assisted VMX. Those are - * declared below under the !IN_RC section. + * + * These are hardware-assisted VMX functions (used by IEM/REM/CPUM and HM). Helpers + * based purely on the Intel VT-x specification (used by IEM/REM and HM) can be + * found in CPUM. * @{ */ VMM_INT_DECL(int) HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs); @@ -150,21 +151,13 @@ VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress); -VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead, - PVMXMSREXITWRITE penmWrite); -VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort, - uint8_t cbAccess); /** @} */ /** @name All-context SVM helpers. * - * These are SVM functions (based on AMD specs.) that may be used by IEM/REM and - * not VirtualBox functions that are used for hardware-assisted SVM. Those are - * declared below under the !IN_RC section. + * These are hardware-assisted SVM functions (used by IEM/REM/CPUM and HM). Helpers + * based purely on the AMD SVM specification (used by IEM/REM and HM) can be found + * in CPUM. * @{ */ VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pSvmEvent); -VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit); -VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg, - uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, - PSVMIOIOEXITINFO pIoExitInfo); /** @} */ Index: /trunk/src/VBox/VMM/Makefile.kmk =================================================================== --- /trunk/src/VBox/VMM/Makefile.kmk (revision 75439) +++ /trunk/src/VBox/VMM/Makefile.kmk (revision 75440) @@ -171,4 +171,6 @@ VMMAll/CPUMAllRegs.cpp \ VMMAll/CPUMAllMsrs.cpp \ + VMMAll/CPUMAllSvm.cpp \ + VMMAll/CPUMAllVmx.cpp \ VMMAll/CPUMStack.cpp \ VMMAll/DBGFAll.cpp \ @@ -560,4 +562,6 @@ VMMAll/CPUMAllRegs.cpp \ VMMAll/CPUMAllMsrs.cpp \ + VMMAll/CPUMAllSvm.cpp \ + VMMAll/CPUMAllVmx.cpp \ VMMAll/DBGFAll.cpp \ VMMAll/IEMAll.cpp \ @@ -711,4 +715,6 @@ VMMAll/CPUMAllRegs.cpp \ VMMAll/CPUMAllMsrs.cpp \ + VMMAll/CPUMAllSvm.cpp \ + VMMAll/CPUMAllVmx.cpp \ VMMAll/CPUMStack.cpp \ VMMAll/DBGFAll.cpp \ Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllSvm.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllSvm.cpp (revision 75440) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllSvm.cpp (revision 75440) @@ -0,0 +1,156 @@ +/* $Id$ */ +/** @file + * CPUM - SVM. + */ + +/* + * Copyright (C) 2018 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#define LOG_GROUP LOG_GROUP_CPUM +#include +#include + + +/** + * Gets the MSR permission bitmap byte and bit offset for the specified MSR. + * + * @returns VBox status code. + * @param idMsr The MSR being requested. + * @param pbOffMsrpm Where to store the byte offset in the MSR permission + * bitmap for @a idMsr. + * @param puMsrpmBit Where to store the bit offset starting at the byte + * returned in @a pbOffMsrpm. + */ +VMM_INT_DECL(int) CPUMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit) +{ + Assert(pbOffMsrpm); + Assert(puMsrpmBit); + + /* + * MSRPM Layout: + * Byte offset MSR range + * 0x000 - 0x7ff 0x00000000 - 0x00001fff + * 0x800 - 0xfff 0xc0000000 - 0xc0001fff + * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff + * 0x1800 - 0x1fff Reserved + * + * Each MSR is represented by 2 permission bits (read and write). + */ + if (idMsr <= 0x00001fff) + { + /* Pentium-compatible MSRs. */ + uint32_t const bitoffMsr = idMsr << 1; + *pbOffMsrpm = bitoffMsr >> 3; + *puMsrpmBit = bitoffMsr & 7; + return VINF_SUCCESS; + } + + if ( idMsr >= 0xc0000000 + && idMsr <= 0xc0001fff) + { + /* AMD Sixth Generation x86 Processor MSRs. */ + uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1; + *pbOffMsrpm = 0x800 + (bitoffMsr >> 3); + *puMsrpmBit = bitoffMsr & 7; + return VINF_SUCCESS; + } + + if ( idMsr >= 0xc0010000 + && idMsr <= 0xc0011fff) + { + /* AMD Seventh and Eighth Generation Processor MSRs. */ + uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1; + *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3); + *puMsrpmBit = bitoffMsr & 7; + return VINF_SUCCESS; + } + + *pbOffMsrpm = 0; + *puMsrpmBit = 0; + return VERR_OUT_OF_RANGE; +} + + +/** + * Determines whether an IOIO intercept is active for the nested-guest or not. + * + * @param pvIoBitmap Pointer to the nested-guest IO bitmap. + * @param u16Port The IO port being accessed. + * @param enmIoType The type of IO access. + * @param cbReg The IO operand size in bytes. + * @param cAddrSizeBits The address size bits (for 16, 32 or 64). + * @param iEffSeg The effective segment number. + * @param fRep Whether this is a repeating IO instruction (REP prefix). + * @param fStrIo Whether this is a string IO instruction. + * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled. + * Optional, can be NULL. + */ +VMM_INT_DECL(bool) CPUMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg, + uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, + PSVMIOIOEXITINFO pIoExitInfo) +{ + Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64); + Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8); + + /* + * The IOPM layout: + * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or + * two 4K pages. + * + * For IO instructions that access more than a single byte, the permission bits + * for all bytes are checked; if any bit is set to 1, the IO access is intercepted. + * + * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes), + * we need 3 extra bits beyond the second 4K page. + */ + static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 }; + + uint16_t const offIopm = u16Port >> 3; + uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7]; + uint8_t const cShift = u16Port - (offIopm << 3); + uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift); + + uint8_t const *pbIopm = (uint8_t *)pvIoBitmap; + Assert(pbIopm); + pbIopm += offIopm; + uint16_t const u16Iopm = *(uint16_t *)pbIopm; + if (u16Iopm & fIopmMask) + { + if (pIoExitInfo) + { + static const uint32_t s_auIoOpSize[] = + { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 }; + + static const uint32_t s_auIoAddrSize[] = + { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 }; + + pIoExitInfo->u = s_auIoOpSize[cbReg & 7]; + pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7]; + pIoExitInfo->n.u1Str = fStrIo; + pIoExitInfo->n.u1Rep = fRep; + pIoExitInfo->n.u3Seg = iEffSeg & 7; + pIoExitInfo->n.u1Type = enmIoType; + pIoExitInfo->n.u16Port = u16Port; + } + return true; + } + + /** @todo remove later (for debugging as VirtualBox always traps all IO + * intercepts). */ + AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n")); + return false; +} + Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllVmx.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/CPUMAllVmx.cpp (revision 75440) +++ /trunk/src/VBox/VMM/VMMAll/CPUMAllVmx.cpp (revision 75440) @@ -0,0 +1,135 @@ +/* $Id$ */ +/** @file + * CPUM - SVM. + */ + +/* + * Copyright (C) 2018 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#define LOG_GROUP LOG_GROUP_CPUM +#include +#include + + +/** + * Gets the permission bits for the specified MSR in the specified MSR bitmap. + * + * @returns VBox status code. + * @param pvMsrBitmap Pointer to the MSR bitmap. + * @param idMsr The MSR. + * @param penmRead Where to store the read permissions. Optional, can be + * NULL. + * @param penmWrite Where to store the write permissions. Optional, can be + * NULL. + */ +VMM_INT_DECL(int) CPUMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead, + PVMXMSREXITWRITE penmWrite) +{ + AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER); + + int32_t iBit; + uint8_t const *pbMsrBitmap = (uint8_t *)pvMsrBitmap; + + /* + * MSR Layout: + * Byte index MSR range Interpreted as + * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits. + * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits. + * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits. + * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits. + * + * A bit corresponding to an MSR within the above range causes a VM-exit + * if the bit is 1 on executions of RDMSR/WRMSR. + * + * If an MSR falls out of the MSR range, it always cause a VM-exit. + * + * See Intel spec. 24.6.9 "MSR-Bitmap Address". + */ + if (idMsr <= 0x00001fff) + iBit = idMsr; + else if ( idMsr >= 0xc0000000 + && idMsr <= 0xc0001fff) + { + iBit = (idMsr - 0xc0000000); + pbMsrBitmap += 0x400; + } + else + { + if (penmRead) + *penmRead = VMXMSREXIT_INTERCEPT_READ; + if (penmWrite) + *penmWrite = VMXMSREXIT_INTERCEPT_WRITE; + Log(("CPUMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr)); + return VINF_SUCCESS; + } + + /* Validate the MSR bit position. */ + Assert(iBit <= 0x1fff); + + /* Get the MSR read permissions. */ + if (penmRead) + { + if (ASMBitTest(pbMsrBitmap, iBit)) + *penmRead = VMXMSREXIT_INTERCEPT_READ; + else + *penmRead = VMXMSREXIT_PASSTHRU_READ; + } + + /* Get the MSR write permissions. */ + if (penmWrite) + { + if (ASMBitTest(pbMsrBitmap + 0x800, iBit)) + *penmWrite = VMXMSREXIT_INTERCEPT_WRITE; + else + *penmWrite = VMXMSREXIT_PASSTHRU_WRITE; + } + + return VINF_SUCCESS; +} + + +/** + * Gets the permission bits for the specified I/O port from the given I/O bitmaps. + * + * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise. + * @param pvIoBitmapA Pointer to I/O bitmap A. + * @param pvIoBitmapB Pointer to I/O bitmap B. + * @param uPort The I/O port being accessed. + * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes). + */ +VMM_INT_DECL(bool) CPUMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort, + uint8_t cbAccess) +{ + Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4); + + /* + * If the I/O port access wraps around the 16-bit port I/O space, + * we must cause a VM-exit. + * + * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally". + */ + /** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc + * respectively are valid and do not constitute a wrap around from what I + * understand. Verify this later. */ + uint32_t const uPortLast = uPort + cbAccess; + if (uPortLast > 0x10000) + return true; + + /* Read the appropriate bit from the corresponding IO bitmap. */ + void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB; + return ASMBitTest(pvIoBitmap, uPort); +} + Index: /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp (revision 75439) +++ /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp (revision 75440) @@ -325,135 +325,4 @@ /** - * Gets the MSR permission bitmap byte and bit offset for the specified MSR. - * - * @returns VBox status code. - * @param idMsr The MSR being requested. - * @param pbOffMsrpm Where to store the byte offset in the MSR permission - * bitmap for @a idMsr. - * @param puMsrpmBit Where to store the bit offset starting at the byte - * returned in @a pbOffMsrpm. - */ -VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit) -{ - Assert(pbOffMsrpm); - Assert(puMsrpmBit); - - /* - * MSRPM Layout: - * Byte offset MSR range - * 0x000 - 0x7ff 0x00000000 - 0x00001fff - * 0x800 - 0xfff 0xc0000000 - 0xc0001fff - * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff - * 0x1800 - 0x1fff Reserved - * - * Each MSR is represented by 2 permission bits (read and write). - */ - if (idMsr <= 0x00001fff) - { - /* Pentium-compatible MSRs. */ - uint32_t const bitoffMsr = idMsr << 1; - *pbOffMsrpm = bitoffMsr >> 3; - *puMsrpmBit = bitoffMsr & 7; - return VINF_SUCCESS; - } - - if ( idMsr >= 0xc0000000 - && idMsr <= 0xc0001fff) - { - /* AMD Sixth Generation x86 Processor MSRs. */ - uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1; - *pbOffMsrpm = 0x800 + (bitoffMsr >> 3); - *puMsrpmBit = bitoffMsr & 7; - return VINF_SUCCESS; - } - - if ( idMsr >= 0xc0010000 - && idMsr <= 0xc0011fff) - { - /* AMD Seventh and Eighth Generation Processor MSRs. */ - uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1; - *pbOffMsrpm = 0x1000 + (bitoffMsr >> 3); - *puMsrpmBit = bitoffMsr & 7; - return VINF_SUCCESS; - } - - *pbOffMsrpm = 0; - *puMsrpmBit = 0; - return VERR_OUT_OF_RANGE; -} - - -/** - * Determines whether an IOIO intercept is active for the nested-guest or not. - * - * @param pvIoBitmap Pointer to the nested-guest IO bitmap. - * @param u16Port The IO port being accessed. - * @param enmIoType The type of IO access. - * @param cbReg The IO operand size in bytes. - * @param cAddrSizeBits The address size bits (for 16, 32 or 64). - * @param iEffSeg The effective segment number. - * @param fRep Whether this is a repeating IO instruction (REP prefix). - * @param fStrIo Whether this is a string IO instruction. - * @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled. - * Optional, can be NULL. - */ -VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg, - uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, - PSVMIOIOEXITINFO pIoExitInfo) -{ - Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64); - Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8); - - /* - * The IOPM layout: - * Each bit represents one 8-bit port. That makes a total of 0..65535 bits or - * two 4K pages. - * - * For IO instructions that access more than a single byte, the permission bits - * for all bytes are checked; if any bit is set to 1, the IO access is intercepted. - * - * Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes), - * we need 3 extra bits beyond the second 4K page. - */ - static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 }; - - uint16_t const offIopm = u16Port >> 3; - uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7]; - uint8_t const cShift = u16Port - (offIopm << 3); - uint16_t const fIopmMask = (1 << cShift) | (fSizeMask << cShift); - - uint8_t const *pbIopm = (uint8_t *)pvIoBitmap; - Assert(pbIopm); - pbIopm += offIopm; - uint16_t const u16Iopm = *(uint16_t *)pbIopm; - if (u16Iopm & fIopmMask) - { - if (pIoExitInfo) - { - static const uint32_t s_auIoOpSize[] = - { SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 }; - - static const uint32_t s_auIoAddrSize[] = - { 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 }; - - pIoExitInfo->u = s_auIoOpSize[cbReg & 7]; - pIoExitInfo->u |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7]; - pIoExitInfo->n.u1Str = fStrIo; - pIoExitInfo->n.u1Rep = fRep; - pIoExitInfo->n.u3Seg = iEffSeg & 7; - pIoExitInfo->n.u1Type = enmIoType; - pIoExitInfo->n.u16Port = u16Port; - } - return true; - } - - /** @todo remove later (for debugging as VirtualBox always traps all IO - * intercepts). */ - AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n")); - return false; -} - - -/** * Returns whether HM has cached the nested-guest VMCB. * Index: /trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp (revision 75439) +++ /trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp (revision 75440) @@ -442,5 +442,5 @@ /** - * Gets the description of a VMX instruction/Vm-exit diagnostic. + * Gets the descriptive name of a VMX instruction/VM-exit diagnostic code. * * @returns The descriptive string. @@ -879,111 +879,2 @@ } - -/** - * Gets the permission bits for the specified MSR in the specified MSR bitmap. - * - * @returns VBox status code. - * @param pvMsrBitmap Pointer to the MSR bitmap. - * @param idMsr The MSR. - * @param penmRead Where to store the read permissions. Optional, can be - * NULL. - * @param penmWrite Where to store the write permissions. Optional, can be - * NULL. - */ -VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead, - PVMXMSREXITWRITE penmWrite) -{ - AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER); - - int32_t iBit; - uint8_t const *pbMsrBitmap = (uint8_t *)pvMsrBitmap; - - /* - * MSR Layout: - * Byte index MSR range Interpreted as - * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits. - * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits. - * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits. - * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits. - * - * A bit corresponding to an MSR within the above range causes a VM-exit - * if the bit is 1 on executions of RDMSR/WRMSR. - * - * If an MSR falls out of the MSR range, it always cause a VM-exit. - * - * See Intel spec. 24.6.9 "MSR-Bitmap Address". - */ - if (idMsr <= 0x00001fff) - iBit = idMsr; - else if ( idMsr >= 0xc0000000 - && idMsr <= 0xc0001fff) - { - iBit = (idMsr - 0xc0000000); - pbMsrBitmap += 0x400; - } - else - { - if (penmRead) - *penmRead = VMXMSREXIT_INTERCEPT_READ; - if (penmWrite) - *penmWrite = VMXMSREXIT_INTERCEPT_WRITE; - Log(("HMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr)); - return VINF_SUCCESS; - } - - /* Validate the MSR bit position. */ - Assert(iBit <= 0x1fff); - - /* Get the MSR read permissions. */ - if (penmRead) - { - if (ASMBitTest(pbMsrBitmap, iBit)) - *penmRead = VMXMSREXIT_INTERCEPT_READ; - else - *penmRead = VMXMSREXIT_PASSTHRU_READ; - } - - /* Get the MSR write permissions. */ - if (penmWrite) - { - if (ASMBitTest(pbMsrBitmap + 0x800, iBit)) - *penmWrite = VMXMSREXIT_INTERCEPT_WRITE; - else - *penmWrite = VMXMSREXIT_PASSTHRU_WRITE; - } - - return VINF_SUCCESS; -} - - -/** - * Gets the permission bits for the specified I/O port from the given I/O bitmaps. - * - * @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise. - * @param pvIoBitmapA Pointer to I/O bitmap A. - * @param pvIoBitmapB Pointer to I/O bitmap B. - * @param uPort The I/O port being accessed. - * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes). - */ -VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort, uint8_t cbAccess) -{ - Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4); - - /* - * If the I/O port access wraps around the 16-bit port I/O space, - * we must cause a VM-exit. - * - * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally". - */ - /** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc - * respectively are valid and do not constitute a wrap around from what I - * understand. Verify this later. */ - uint32_t const uPortLast = uPort + cbAccess; - if (uPortLast > 0x10000) - return true; - - /* Read the appropriate bit from the corresponding IO bitmap. */ - void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB; - return ASMBitTest(pvIoBitmap, uPort); -} - Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h (revision 75439) +++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h (revision 75440) @@ -985,6 +985,6 @@ SVMIOIOEXITINFO IoExitInfo; void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap); - bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo, - &IoExitInfo); + bool const fIntercept = CPUMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, + fStrIo, &IoExitInfo); if (fIntercept) { @@ -1034,5 +1034,5 @@ uint16_t offMsrpm; uint8_t uMsrpmBit; - int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); + int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); if (RT_SUCCESS(rc)) { Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h (revision 75439) +++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h (revision 75440) @@ -2986,5 +2986,5 @@ Assert(pbIoBitmapA); Assert(pbIoBitmapB); - return HMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess); + return CPUMVmxGetIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess); } @@ -6726,6 +6726,6 @@ { VMXMSREXITREAD enmRead; - int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead, - NULL /* penmWrite */); + int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead, + NULL /* penmWrite */); AssertRC(rc); if (enmRead == VMXMSREXIT_INTERCEPT_READ) @@ -6735,6 +6735,6 @@ { VMXMSREXITWRITE enmWrite; - int rc = HMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */, - &enmWrite); + int rc = CPUMVmxGetMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */, + &enmWrite); AssertRC(rc); if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE) Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (revision 75439) +++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (revision 75440) @@ -872,5 +872,5 @@ uint16_t offMsrpm; uint8_t uMsrpmBit; - int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); + int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); AssertRC(rc); @@ -5156,6 +5156,6 @@ const bool fStrIo = pIoExitInfo->n.u1Str; - return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo, - NULL /* pIoExitInfo */); + return CPUMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo, + NULL /* pIoExitInfo */); } @@ -5248,5 +5248,5 @@ uint16_t offMsrpm; uint8_t uMsrpmBit; - int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); + int rc = CPUMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit); if (RT_SUCCESS(rc)) { Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 75439) +++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 75440) @@ -1738,5 +1738,5 @@ VMXMSREXITREAD enmRead; VMXMSREXITWRITE enmWrite; - rc = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite); + rc = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite); AssertMsgReturnVoid(rc == VINF_SUCCESS, ("HMVmxGetMsrPermission! failed. rc=%Rrc\n", rc)); if (pGuestMsr->u32Msr == MSR_K6_EFER) @@ -11963,5 +11963,5 @@ VMXMSREXITREAD enmRead; VMXMSREXITWRITE enmWrite; - int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite); + int rc2 = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite); AssertRCReturn(rc2, rc2); if (enmRead == VMXMSREXIT_PASSTHRU_READ) @@ -12108,5 +12108,5 @@ VMXMSREXITREAD enmRead; VMXMSREXITWRITE enmWrite; - int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite); + int rc2 = CPUMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite); AssertRCReturn(rc2, rc2); if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)