VirtualBox

Changeset 73111 in vbox


Ignore:
Timestamp:
Jul 13, 2018 7:44:00 AM (6 years ago)
Author:
vboxsync
Message:

VMM/HMSVMR0: Fix vmmcall, pause, TPR patching for CPUs that don't support NRIP_SAVE.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r73097 r73111  
    175175    } while (0)
    176176#endif
    177 
    178 /** Macro which updates interrupt shadow for the current RIP.  */
    179 #define HMSVM_UPDATE_INTR_SHADOW(a_pVCpu) \
    180     do { \
    181         /* Update interrupt shadow. */ \
    182         if (   VMCPU_FF_IS_PENDING((a_pVCpu), VMCPU_FF_INHIBIT_INTERRUPTS) \
    183             && (a_pVCpu)->cpum.GstCtx.rip != EMGetInhibitInterruptsPC((a_pVCpu))) \
    184             VMCPU_FF_CLEAR((a_pVCpu), VMCPU_FF_INHIBIT_INTERRUPTS); \
    185     } while (0)
    186177
    187178/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
    … …  
    60346025
    60356026/**
    6036  * Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
    6037  * supported, otherwise advances the RIP by the number of bytes specified in
    6038  * @a cb.
    6039  *
    6040  * @param   pVCpu       The cross context virtual CPU structure.
    6041  * @param   cb          RIP increment value in bytes when the CPU doesn't support
    6042  *                      NRIP_SAVE.
    6043  */
    6044 DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, uint32_t cb)
    6045 {
    6046     PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
    6047     bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
    6048     if (fSupportsNextRipSave)
    6049     {
    6050         PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
    6051         Assert(pVmcb);
    6052         Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_RIP));
    6053         Assert(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb);
    6054         pCtx->rip = pVmcb->ctrl.u64NextRIP;
    6055     }
    6056     else
    6057         pCtx->rip += cb;
    6058 
    6059     HMSVM_UPDATE_INTR_SHADOW(pVCpu);
    6060 }
    6061 
    6062 
    6063 /**
    6064  * Gets the length of the current instruction when the CPU supports the NRIP_SAVE
    6065  * feature.
    6066  *
    6067  * @returns The current instruction length in bytes.
    6068  * @param   pVCpu       The cross context virtual CPU structure.
    6069  *
    6070  * @remarks Requires the NRIP_SAVE feature to be supported by the CPU.
    6071  */
    6072 DECLINLINE(uint8_t) hmR0SvmGetInstrLength(PVMCPU pVCpu)
    6073 {
    6074     Assert(hmR0SvmSupportsNextRipSave(pVCpu));
    6075     PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
    6076     return pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    6077 }
    6078 
    6079 
    6080 /**
    6081  * Advances the guest RIP by the number of bytes specified in @a cb. This does
    6082  * not make use of any hardware features to determine the instruction length.
     6027 * Advances the guest RIP by the number of bytes specified in @a cb.
    60836028 *
    60846029 * @param   pVCpu       The cross context virtual CPU structure.
    60856030 * @param   cb          RIP increment value in bytes.
    60866031 */
    6087 DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, uint32_t cb)
    6088 {
    6089     pVCpu->cpum.GstCtx.rip += cb;
    6090     HMSVM_UPDATE_INTR_SHADOW(pVCpu);
    6091 }
    6092 #undef HMSVM_UPDATE_INTR_SHADOW
     6032DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPU pVCpu, uint32_t cb)
     6033{
     6034    PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
     6035    pCtx->rip += cb;
     6036
     6037    /* Update interrupt shadow. */
     6038    if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     6039        && pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
     6040        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
     6041}
    60936042
    60946043
    … …  
    61396088    {
    61406089        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    6141         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6090        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6091        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    61426092        rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
    61436093    }
    … …  
    61706120    {
    61716121        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    6172         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6122        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6123        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    61736124        rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
    61746125    }
    … …  
    62066157        if (fSupportsNextRipSave)
    62076158        {
    6208             uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6159            PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6160            uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    62096161            rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
    62106162        }
    … …  
    62546206    {
    62556207        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR4);
    6256         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6208        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6209        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    62576210        rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
    62586211    }
    … …  
    62866239    if (fSupportsNextRipSave)
    62876240    {
    6288         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR4
    6289                                         | CPUMCTX_EXTRN_TSC_AUX);
    6290         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6241        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_TSC_AUX);
     6242        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6243        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    62916244        rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
    62926245    }
    … …  
    63216274    {
    63226275        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR4);
    6323         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6276        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6277        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    63246278        rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
    63256279    }
    … …  
    63556309    {
    63566310        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
    6357         PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
     6311        PCSVMVMCB     pVmcb    = hmR0SvmGetCurrentVmcb(pVCpu);
    63586312        uint8_t const cbInstr   = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    63596313        RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
    … …  
    63886342    {
    63896343        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    6390         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6344        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6345        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    63916346        rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
    63926347    }
    … …  
    64086363    }
    64096364    HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
     6365    STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
    64106366    if (rcStrict != VINF_SUCCESS)
    6411          STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
     6367        STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
    64126368    return VBOXSTRICTRC_VAL(rcStrict);;
    64136369}
    … …  
    64226378
    64236379    /*
    6424      * SVM unfortunately does not provide us with any segment override prefix information.
    6425      *
    6426      * If the instruction length supplied by the CPU is 3 bytes, we can be certain that no
     6380     * If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
    64276381     * segment override prefix is present (and thus use the default segment DS). Otherwise, a
    64286382     * segment override prefix or other prefixes might be used, in which case we fallback to
    6429      * IEMExecOne() to handle it.
     6383     * IEMExecOne() to figure out.
    64306384     */
    64316385    VBOXSTRICTRC  rcStrict;
    6432     bool const    fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
    6433     uint8_t const cbInstr              = fSupportsNextRipSave ? hmR0SvmGetInstrLength(pVCpu) : 0;
    6434     if (cbInstr == 3)
     6386    PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6387    uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
     6388    if (cbInstr)
    64356389    {
    64366390        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_DS);
    … …  
    64666420    {
    64676421        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    6468         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     6422        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     6423        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    64696424        rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
    64706425    }
    … …  
    65456500        if (fMovCRx)
    65466501        {
    6547             HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4
     6502            HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_CR_MASK
    65486503                                            | CPUMCTX_EXTRN_APIC_TPR);
    65496504            uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
    … …  
    66896644         *  can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
    66906645        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
    6691         rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmcb->ctrl.u64NextRIP - pCtx->rip);
     6646        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
     6647        rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
    66926648    }
    66936649    else
    … …  
    67316687     * We utilitize the LSTAR MSR for patching.
    67326688     */
     6689    bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
    67336690    if (   pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
    67346691        && idMsr == MSR_K8_LSTAR)
    67356692    {
     6693        unsigned cbInstr;
     6694        if (fSupportsNextRipSave)
     6695            cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
     6696        else
     6697        {
     6698            PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
     6699            int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
     6700            if (   rc == VINF_SUCCESS
     6701                && pDis->pCurInstr->uOpcode == OP_WRMSR)
     6702                Assert(cbInstr > 0);
     6703            else
     6704                cbInstr = 0;
     6705        }
     6706
     6707        /* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
    67366708        if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
    67376709        {
    6738             /* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
    6739             int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
    6740             AssertRC(rc2);
     6710            int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
     6711            AssertRCReturn(rc, rc);
    67416712            ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
    67426713        }
    67436714
    67446715        int rc = VINF_SUCCESS;
    6745         hmR0SvmAdvanceRipHwAssist(pVCpu, 2);
     6716        hmR0SvmAdvanceRip(pVCpu, cbInstr);
    67466717        HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
    67476718        return rc;
    … …  
    67526723     */
    67536724    VBOXSTRICTRC rcStrict;
    6754     bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
    67556725    if (fSupportsNextRipSave)
    67566726    {
    … …  
    67596729         * clear the applicable extern flags. */
    67606730        HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
    6761         rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmcb->ctrl.u64NextRIP - pCtx->rip);
     6731        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
     6732        rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
    67626733    }
    67636734    else
    … …  
    73857356    if (EMAreHypercallInstructionsEnabled(pVCpu))
    73867357    {
     7358        unsigned cbInstr;
     7359        if (hmR0SvmSupportsNextRipSave(pVCpu))
     7360        {
     7361            PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
     7362            cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
     7363        }
     7364        else
     7365        {
     7366            PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
     7367            int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
     7368            if (   rc == VINF_SUCCESS
     7369                && pDis->pCurInstr->uOpcode == OP_VMMCALL)
     7370                Assert(cbInstr > 0);
     7371            else
     7372                cbInstr = 0;
     7373        }
     7374
    73877375        VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
    73887376        if (RT_SUCCESS(rcStrict))
    … …  
    73917379               of say VINF_GIM_R3_HYPERCALL. */
    73927380            if (rcStrict == VINF_SUCCESS)
    7393                 hmR0SvmAdvanceRipHwAssist(pVCpu, 3 /* cbInstr */);
     7381                hmR0SvmAdvanceRip(pVCpu, cbInstr);
    73947382
    73957383            return VBOXSTRICTRC_VAL(rcStrict);
    … …  
    74107398{
    74117399    HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
    7412     hmR0SvmAdvanceRipHwAssist(pVCpu, 2);
     7400
     7401    VBOXSTRICTRC rcStrict;
     7402    unsigned cbInstr;
     7403    bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
     7404    if (fSupportsNextRipSave)
     7405    {
     7406        PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
     7407        cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
     7408    }
     7409    else
     7410    {
     7411        PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
     7412        int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
     7413        if (   rc == VINF_SUCCESS
     7414            && pDis->pCurInstr->uOpcode == OP_PAUSE)
     7415            Assert(cbInstr > 0);
     7416        else
     7417            cbInstr = 0;
     7418    }
     7419
    74137420    /** @todo The guest has likely hit a contended spinlock. We might want to
    74147421     *        poke a schedule different guest VCPU. */
     7422    hmR0SvmAdvanceRip(pVCpu, cbInstr);
    74157423    return VINF_EM_RAW_INTERRUPT;
    74167424}
    … …  
    76157623        {
    76167624            /* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
    7617             hmR0SvmAdvanceRipDumb(pVCpu, cbInstr);
     7625            hmR0SvmAdvanceRip(pVCpu, cbInstr);
    76187626            rc = VINF_SUCCESS;
    76197627            HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
    … …  
    76607668        PVM       pVM  = pVCpu->CTX_SUFF(pVM);
    76617669        PDISSTATE pDis = &pVCpu->hm.s.DisState;
    7662         unsigned  cbOp;
    7663         int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
     7670        unsigned  cbInstr;
     7671        int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
    76647672        if (RT_SUCCESS(rc))
    76657673        {
    … …  
    76677675            rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq */, 1 /* u8Level */, 0 /* uTagSrc */);
    76687676            if (RT_SUCCESS(rc))
    7669                 pCtx->rip += cbOp;
     7677                hmR0SvmAdvanceRip(pVCpu, cbInstr);
    76707678        }
    76717679        else
    … …  
    78467854    if (fSupportsNextRipSave)
    78477855    {
    7848         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | fImport);
    7849         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     7856        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     7857        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    78507858        rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
    78517859    }
    … …  
    78887896    if (fSupportsNextRipSave)
    78897897    {
    7890         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | fImport);
    7891         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     7898        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    78927899        rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
    78937900    }
    … …  
    79317938    if (fSupportsNextRipSave)
    79327939    {
    7933         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | fImport);
    7934         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     7940        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    79357941        rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
    79367942    }
    … …  
    79757981    if (fSupportsNextRipSave)
    79767982    {
    7977         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    7978         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     7983        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    79797984        rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
    79807985    }
    … …  
    80068011    if (fSupportsNextRipSave)
    80078012    {
    8008         HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
    8009         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     8013        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     8014        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    80108015        rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
    80118016    }
    … …  
    80418046    if (fSupportsNextRipSave)
    80428047    {
    8043         uint8_t const cbInstr = hmR0SvmGetInstrLength(pVCpu);
     8048        PCSVMVMCB     pVmcb   = hmR0SvmGetCurrentVmcb(pVCpu);
     8049        uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
    80448050        rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
    80458051    }
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