Index: /trunk/include/VBox/vmm/em.h =================================================================== --- /trunk/include/VBox/vmm/em.h (revision 72654) +++ /trunk/include/VBox/vmm/em.h (revision 72655) @@ -230,5 +230,5 @@ * * The flags the exit type are combined to a 32-bit number using the - * EMEXIT_MAKE_FLAGS_AND_TYPE() macro. + * EMEXIT_MAKE_FT() macro. * * @{ */ @@ -242,8 +242,8 @@ #define EMEXIT_F_CS_EIP UINT32_C(0x00010000) /**< The PC is EIP in the low dword and CS in the high. */ #define EMEXIT_F_UNFLATTENED_PC UINT32_C(0x00020000) /**< The PC hasn't had CS.BASE added to it. */ -/** Preemption is currently disabled (or we're using preemption hooks). */ -#define EMEXIT_F_PREEMPT_DISABLED UINT32_C(0x00040000) +/** HM is calling (from ring-0). Preemption is currently disabled or we're using preemption hooks. */ +#define EMEXIT_F_HM UINT32_C(0x00040000) /** Combines flags and exit type into EMHistoryAddExit() input. */ -#define EMEXIT_MAKE_FLAGS_AND_TYPE(a_fFlags, a_uType) ((a_fFlags) | (uint32_t)(a_uType)) +#define EMEXIT_MAKE_FT(a_fFlags, a_uType) ((a_fFlags) | (uint32_t)(a_uType)) /** @} */ @@ -273,5 +273,5 @@ /** The flat PC of the exit. */ uint64_t uFlatPC; - /** Flags and type, see EMEXIT_MAKE_FLAGS_AND_TYPE. */ + /** Flags and type, see EMEXIT_MAKE_FT. */ uint32_t uFlagsAndType; /** The action to take (EMEXITACTION). */ Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 72654) +++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp (revision 72655) @@ -603,6 +603,6 @@ { # ifdef IN_RING0 - /* Disregard the preempt disabled flag. */ - uFlagsAndType &= ~EMEXIT_F_PREEMPT_DISABLED; + /* Disregard the hm flag. */ + uFlagsAndType &= ~EMEXIT_F_HM; # endif @@ -775,5 +775,5 @@ # ifdef IN_RING0 && pVCpu->em.s.fExitOptimizationEnabledR0 - && ( !(uFlagsAndType & EMEXIT_F_PREEMPT_DISABLED) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) + && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) # else && pVCpu->em.s.fExitOptimizationEnabled @@ -864,5 +864,5 @@ # ifdef IN_RING0 && pVCpu->em.s.fExitOptimizationEnabledR0 - && ( !(uFlagsAndType & EMEXIT_F_PREEMPT_DISABLED) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) + && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) # else && pVCpu->em.s.fExitOptimizationEnabled @@ -909,5 +909,5 @@ # ifdef IN_RING0 && pVCpu->em.s.fExitOptimizationEnabledR0 - && ( !(uFlagsAndType & EMEXIT_F_PREEMPT_DISABLED) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) + && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled) # else && pVCpu->em.s.fExitOptimizationEnabled Index: /trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h =================================================================== --- /trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h (revision 72654) +++ /trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h (revision 72655) @@ -1892,5 +1892,5 @@ Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "", State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pMsg->Header.InterceptAccessType])); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, uHostTsc); return VINF_SUCCESS; @@ -1914,6 +1914,6 @@ PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, uHostTsc); nemHCWinCopyStateFromX64Header(pVCpu, pCtx, &pMsg->Header); @@ -2000,5 +2000,5 @@ Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "", State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType])); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc); return VINF_SUCCESS; @@ -2022,6 +2022,6 @@ PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc); nemR3WinCopyStateFromX64Header(pVCpu, pCtx, &pExit->VpContext); @@ -2090,9 +2090,9 @@ !pMsg->AccessInfo.StringOp ? ( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)) + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)) : ( pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); if (!pExitRec) @@ -2289,9 +2289,9 @@ !pExit->IoPortAccess.AccessInfo.StringOp ? ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)) + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)) : ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); if (!pExitRec) @@ -2455,5 +2455,5 @@ * Just copy the state we've got and handle it in the loop for now. */ - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); @@ -2492,5 +2492,5 @@ * Just copy the state we've got and handle it in the loop for now. */ - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); @@ -2523,5 +2523,5 @@ { AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength)); - PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID), + PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); if (!pExitRec) @@ -2604,5 +2604,5 @@ { AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength)); - PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID), + PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); if (!pExitRec) @@ -2700,6 +2700,6 @@ PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); @@ -2845,6 +2845,6 @@ PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, pExit->MsrAccess.AccessInfo.IsWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); nemR3WinCopyStateFromX64Header(pVCpu, pCtx, &pExit->VpContext); @@ -3126,5 +3126,5 @@ case X86_XCPT_UD: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUd); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); @@ -3149,5 +3149,5 @@ case X86_XCPT_DB: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionDb); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); Log4(("XcptExit/%u: %04x:%08RX64/%s: #DB - TODO\n", @@ -3157,5 +3157,5 @@ case X86_XCPT_BP: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionBp); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP), pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC()); Log4(("XcptExit/%u: %04x:%08RX64/%s: #BP - TODO - %u\n", pVCpu->idCpu, pMsg->Header.CsSegment.Selector, @@ -3231,5 +3231,5 @@ case X86_XCPT_UD: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUd); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); if (nemHcWinIsInterestingUndefinedOpcode(pExit->VpException.InstructionByteCount, pExit->VpException.InstructionBytes, @@ -3256,5 +3256,5 @@ case X86_XCPT_DB: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionDb); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); Log4(("XcptExit/%u: %04x:%08RX64/%s: #DB - TODO\n", @@ -3264,5 +3264,5 @@ case X86_XCPT_BP: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionBp); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); Log4(("XcptExit/%u: %04x:%08RX64/%s: #BP - TODO - %u\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector, @@ -3323,5 +3323,5 @@ * Let IEM decide whether this is really it. */ - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION), pMsgHdr->Rip + pMsgHdr->CsSegment.Base, ASMReadTSC()); nemHCWinCopyStateFromX64Header(pVCpu, pCtx, pMsgHdr); @@ -3380,5 +3380,5 @@ * Let IEM decide whether this is really it. */ - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); nemR3WinCopyStateFromX64Header(pVCpu, pCtx, &pExit->VpContext); @@ -3451,5 +3451,5 @@ case HvMessageTypeX64Halt: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT), pMsg->X64InterceptHeader.Rip + pMsg->X64InterceptHeader.CsSegment.Base, ASMReadTSC()); Log4(("HaltExit\n")); @@ -3535,5 +3535,5 @@ case WHvRunVpExitReasonX64Halt: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT), pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); Log4(("HaltExit\n")); Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (revision 72654) +++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (revision 72655) @@ -109,5 +109,6 @@ #define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_pCtx, a_fWhat) \ do { \ - hmR0SvmImportGuestState((a_pVCpu), (a_pCtx), (a_fWhat)); \ + if ((a_pCtx)->fExtrn & (a_fWhat)) \ + hmR0SvmImportGuestState((a_pVCpu), (a_pCtx), (a_fWhat)); \ } while (0) @@ -4901,5 +4902,5 @@ HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP); - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK), pCtx->cs.u64Base + pCtx->rip, uHostTsc); } @@ -6498,18 +6499,43 @@ HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(); - PVM pVM = pVCpu->CTX_SUFF(pVM); - int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx)); - if (RT_LIKELY(rc == VINF_SUCCESS)) - { - hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2); - HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS); + VBOXSTRICTRC rcStrict; + PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, + EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_CPUID), + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); + if (!pExitRec) + { + PVM pVM = pVCpu->CTX_SUFF(pVM); + rcStrict = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx)); + if (RT_LIKELY(rcStrict == VINF_SUCCESS)) + { + hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2); + HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict); + } + else + { + AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); + rcStrict = VERR_EM_INTERPRETER; + } } else { - AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc)); - rc = VERR_EM_INTERPRETER; + /* + * Frequent exit or something needing probing. Get state and call EMHistoryExec. + */ + Assert(pCtx == &pVCpu->cpum.GstCtx); + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, IEM_CPUMCTX_EXTRN_MUST_MASK); + + Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx)); + + rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + + Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, + VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); } STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid); - return rc; + return VBOXSTRICTRC_TODO(rcStrict); } @@ -7086,164 +7112,200 @@ } + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS); VBOXSTRICTRC rcStrict; - bool fUpdateRipAlready = false; - if (IoExitInfo.n.u1Str) - { - /* INS/OUTS - I/O String instruction. */ - /** @todo Huh? why can't we use the segment prefix information given by AMD-V - * in EXITINFO1? Investigate once this thing is up and running. */ - Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue, - IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r')); - AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2); - static IEMMODE const s_aenmAddrMode[8] = - { - (IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1 - }; - IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7]; - if (enmAddrMode != (IEMMODE)-1) - { - uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip; - if (cbInstr <= 15 && cbInstr >= 1) + PCEMEXITREC pExitRec = NULL; + if ( !pVCpu->hm.s.fSingleInstruction + && !pVCpu->cpum.GstCtx.eflags.Bits.u1TF) + pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, + !IoExitInfo.n.u1Str + ? IoExitInfo.n.u1Type == SVM_IOIO_READ + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE) + : IoExitInfo.n.u1Type == SVM_IOIO_READ + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE), + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); + if (!pExitRec) + { + bool fUpdateRipAlready = false; + if (IoExitInfo.n.u1Str) + { + /* INS/OUTS - I/O String instruction. */ + /** @todo Huh? why can't we use the segment prefix information given by AMD-V + * in EXITINFO1? Investigate once this thing is up and running. */ + Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue, + IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r')); + AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2); + static IEMMODE const s_aenmAddrMode[8] = { - Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep); - if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE) + (IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1 + }; + IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7]; + if (enmAddrMode != (IEMMODE)-1) + { + uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip; + if (cbInstr <= 15 && cbInstr >= 1) { - /* Don't know exactly how to detect whether u3Seg is valid, currently - only enabling it for Bulldozer and later with NRIP. OS/2 broke on - 2384 Opterons when only checking NRIP. */ - bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx); - if ( fSupportsNextRipSave - && pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First) + Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep); + if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE) { - AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS || cbInstr > 1U + IoExitInfo.n.u1Rep, - ("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep)); - rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, - IoExitInfo.n.u3Seg, true /*fIoChecked*/); + /* Don't know exactly how to detect whether u3Seg is valid, currently + only enabling it for Bulldozer and later with NRIP. OS/2 broke on + 2384 Opterons when only checking NRIP. */ + bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx); + if ( fSupportsNextRipSave + && pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First) + { + AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS || cbInstr > 1U + IoExitInfo.n.u1Rep, + ("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep)); + rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, + IoExitInfo.n.u3Seg, true /*fIoChecked*/); + } + else if (cbInstr == 1U + IoExitInfo.n.u1Rep) + rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, + X86_SREG_DS, true /*fIoChecked*/); + else + rcStrict = IEMExecOne(pVCpu); + STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite); } - else if (cbInstr == 1U + IoExitInfo.n.u1Rep) - rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, - X86_SREG_DS, true /*fIoChecked*/); else - rcStrict = IEMExecOne(pVCpu); - STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite); + { + AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /*=0*/, ("%#x\n", IoExitInfo.n.u3Seg)); + rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, + true /*fIoChecked*/); + STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead); + } } else { - AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /*=0*/, ("%#x\n", IoExitInfo.n.u3Seg)); - rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr, - true /*fIoChecked*/); - STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead); + AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr)); + rcStrict = IEMExecOne(pVCpu); } } else { - AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr)); + AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u)); rcStrict = IEMExecOne(pVCpu); } + fUpdateRipAlready = true; } else { - AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u)); - rcStrict = IEMExecOne(pVCpu); - } - fUpdateRipAlready = true; + /* IN/OUT - I/O instruction. */ + Assert(!IoExitInfo.n.u1Rep); + + if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE) + { + rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue); + STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite); + } + else + { + uint32_t u32Val = 0; + rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue); + if (IOM_SUCCESS(rcStrict)) + { + /* Save result of I/O IN instr. in AL/AX/EAX. */ + /** @todo r=bird: 32-bit op size should clear high bits of rax! */ + pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal); + } + else if (rcStrict == VINF_IOM_R3_IOPORT_READ) + HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue); + + STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead); + } + } + + if (IOM_SUCCESS(rcStrict)) + { + /* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */ + if (!fUpdateRipAlready) + pCtx->rip = pVmcb->ctrl.u64ExitInfo2; + + /* + * If any I/O breakpoints are armed, we need to check if one triggered + * and take appropriate action. + * Note that the I/O breakpoint type is undefined if CR4.DE is 0. + */ + /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the + * execution engines about whether hyper BPs and such are pending. */ + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, CPUMCTX_EXTRN_DR7); + uint32_t const uDr7 = pCtx->dr[7]; + if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK) + && X86_DR7_ANY_RW_IO(uDr7) + && (pCtx->cr4 & X86_CR4_DE)) + || DBGFBpIsHwIoArmed(pVM))) + { + /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */ + VMMRZCallRing3Disable(pVCpu); + HM_DISABLE_PREEMPT(); + + STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck); + CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /*fDr6*/); + + VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue); + if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP) + { + /* Raise #DB. */ + pVmcb->guest.u64DR6 = pCtx->dr[6]; + pVmcb->guest.u64DR7 = pCtx->dr[7]; + pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX; + hmR0SvmSetPendingXcptDB(pVCpu); + } + /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST], + however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */ + else if ( rcStrict2 != VINF_SUCCESS + && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict)) + rcStrict = rcStrict2; + AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE); + + HM_RESTORE_PREEMPT(); + VMMRZCallRing3Enable(pVCpu); + } + + HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict); + } + +#ifdef VBOX_STRICT + if (rcStrict == VINF_IOM_R3_IOPORT_READ) + Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ); + else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE) + Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE); + else + { + /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST + * statuses, that the VMM device and some others may return. See + * IOM_SUCCESS() for guidance. */ + AssertMsg( RT_FAILURE(rcStrict) + || rcStrict == VINF_SUCCESS + || rcStrict == VINF_EM_RAW_EMULATE_INSTR + || rcStrict == VINF_EM_DBG_BREAKPOINT + || rcStrict == VINF_EM_RAW_GUEST_TRAP + || rcStrict == VINF_EM_RAW_TO_R3 + || rcStrict == VINF_TRPM_XCPT_DISPATCHED + || rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); + } +#endif } else { - /* IN/OUT - I/O instruction. */ - Assert(!IoExitInfo.n.u1Rep); - - if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE) - { - rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue); - STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite); - } - else - { - uint32_t u32Val = 0; - rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue); - if (IOM_SUCCESS(rcStrict)) - { - /* Save result of I/O IN instr. in AL/AX/EAX. */ - /** @todo r=bird: 32-bit op size should clear high bits of rax! */ - pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal); - } - else if (rcStrict == VINF_IOM_R3_IOPORT_READ) - HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue); - - STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead); - } - } - - if (IOM_SUCCESS(rcStrict)) - { - /* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */ - if (!fUpdateRipAlready) - pCtx->rip = pVmcb->ctrl.u64ExitInfo2; - /* - * If any I/O breakpoints are armed, we need to check if one triggered - * and take appropriate action. - * Note that the I/O breakpoint type is undefined if CR4.DE is 0. + * Frequent exit or something needing probing. Get state and call EMHistoryExec. */ - /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the - * execution engines about whether hyper BPs and such are pending. */ - HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, CPUMCTX_EXTRN_DR7); - uint32_t const uDr7 = pCtx->dr[7]; - if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK) - && X86_DR7_ANY_RW_IO(uDr7) - && (pCtx->cr4 & X86_CR4_DE)) - || DBGFBpIsHwIoArmed(pVM))) - { - /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */ - VMMRZCallRing3Disable(pVCpu); - HM_DISABLE_PREEMPT(); - - STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck); - CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /*fDr6*/); - - VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue); - if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP) - { - /* Raise #DB. */ - pVmcb->guest.u64DR6 = pCtx->dr[6]; - pVmcb->guest.u64DR7 = pCtx->dr[7]; - pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX; - hmR0SvmSetPendingXcptDB(pVCpu); - } - /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST], - however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */ - else if ( rcStrict2 != VINF_SUCCESS - && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict)) - rcStrict = rcStrict2; - AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE); - - HM_RESTORE_PREEMPT(); - VMMRZCallRing3Enable(pVCpu); - } - - HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict); - } - -#ifdef VBOX_STRICT - if (rcStrict == VINF_IOM_R3_IOPORT_READ) - Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ); - else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE) - Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE); - else - { - /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST - * statuses, that the VMM device and some others may return. See - * IOM_SUCCESS() for guidance. */ - AssertMsg( RT_FAILURE(rcStrict) - || rcStrict == VINF_SUCCESS - || rcStrict == VINF_EM_RAW_EMULATE_INSTR - || rcStrict == VINF_EM_DBG_BREAKPOINT - || rcStrict == VINF_EM_RAW_GUEST_TRAP - || rcStrict == VINF_EM_RAW_TO_R3 - || rcStrict == VINF_TRPM_XCPT_DISPATCHED - || rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); - } -#endif + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, IEM_CPUMCTX_EXTRN_MUST_MASK); + STAM_COUNTER_INC(!IoExitInfo.n.u1Str + ? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead + : IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead); + Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "", + IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth)); + + rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); + + Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, + VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); + } return VBOXSTRICTRC_TODO(rcStrict); } @@ -7307,5 +7369,4 @@ * MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages. */ - int rc; Assert((u32ErrCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD); if ((u32ErrCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) @@ -7316,28 +7377,53 @@ return VINF_EM_RAW_INJECT_TRPM_EVENT; - VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr, - u32ErrCode); - rc = VBOXSTRICTRC_VAL(rc2); - - /* - * If we succeed, resume guest execution. - * If we fail in interpreting the instruction because we couldn't get the guest physical address - * of the page containing the instruction via the guest's page tables (we would invalidate the guest page - * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this - * weird case. See @bugref{6043}. - */ - if ( rc == VINF_SUCCESS - || rc == VERR_PAGE_TABLE_NOT_PRESENT - || rc == VERR_PAGE_NOT_PRESENT) - { - /* Successfully handled MMIO operation. */ - HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE); - rc = VINF_SUCCESS; - } - return rc; + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS); + VBOXSTRICTRC rcStrict; + PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, + EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_MMIO), + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); + if (!pExitRec) + { + + rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr, + u32ErrCode); + + /* + * If we succeed, resume guest execution. + * If we fail in interpreting the instruction because we couldn't get the guest physical address + * of the page containing the instruction via the guest's page tables (we would invalidate the guest page + * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this + * weird case. See @bugref{6043}. + */ + if ( rcStrict == VINF_SUCCESS + || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT + || rcStrict == VERR_PAGE_NOT_PRESENT) + { + /* Successfully handled MMIO operation. */ + HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE); + rcStrict = VINF_SUCCESS; + } + } + else + { + /* + * Frequent exit or something needing probing. Get state and call EMHistoryExec. + */ + Assert(pCtx == &pVCpu->cpum.GstCtx); + HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, pCtx, IEM_CPUMCTX_EXTRN_MUST_MASK); + Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr)); + + rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); + + Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", + pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, + VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); + } + return VBOXSTRICTRC_TODO(rcStrict); } TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode); - rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr); + int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr); TRPMResetTrap(pVCpu); Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 72654) +++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (revision 72655) @@ -9730,5 +9730,5 @@ * by amending the history entry added here. */ - EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK), + EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK), UINT64_MAX, uHostTsc); @@ -12260,9 +12260,7 @@ VBOXSTRICTRC rcStrict; - PCEMEXITREC pExitRec; - pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, - EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_CPUID), - pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); + PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, + EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_CPUID), + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); if (!pExitRec) { @@ -12297,4 +12295,5 @@ rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", @@ -13234,13 +13233,9 @@ !fIOString ? !fIOWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_IO_PORT_READ) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_IO_PORT_WRITE) + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE) : !fIOWrite - ? EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_IO_PORT_STR_READ) - : EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_IO_PORT_STR_WRITE), + ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ) + : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE), pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); if (!pExitRec) @@ -13427,5 +13422,6 @@ int rc2 = hmR0VmxSaveGuestRegsForIemInterpreting(pVCpu); AssertRCReturn(rc2, rc2); - + STAM_COUNTER_INC(!fIOString ? fIOWrite ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead + : fIOWrite ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead); Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, @@ -13434,4 +13430,5 @@ rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", @@ -13731,9 +13728,7 @@ VBOXSTRICTRC rcStrict; - PCEMEXITREC pExitRec; - pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, - EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM | EMEXIT_F_PREEMPT_DISABLED, - EMEXITTYPE_MMIO), - pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); + PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu, + EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_MMIO), + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base); if (!pExitRec) { @@ -13773,4 +13768,5 @@ rcStrict = EMHistoryExec(pVCpu, pExitRec, 0); + HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n", Index: /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp (revision 72654) +++ /trunk/src/VBox/VMM/VMMRC/IOMRC.cpp (revision 72655) @@ -218,19 +218,19 @@ { case OP_IN: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)); return iomRCInterpretIN(pVM, pVCpu, pRegFrame, pCpu); case OP_OUT: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE)); return iomRCInterpretOUT(pVM, pVCpu, pRegFrame, pCpu); case OP_INSB: case OP_INSWD: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)); return iomRCInterpretINS(pVCpu, pCpu); case OP_OUTSB: case OP_OUTSWD: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)); return iomRCInterpretOUTS(pVCpu, pCpu); Index: /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp =================================================================== --- /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 72654) +++ /trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (revision 72655) @@ -333,5 +333,5 @@ LogFlow(("TRPMGC01: cs:eip=%04x:%08x uDr6=%RTreg EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(1); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_DB), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_DB), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); @@ -388,5 +388,5 @@ PVMCPU pVCpu = TRPMCPU_2_VMCPU(pTrpmCpu); TRPM_ENTER_DBG_HOOK_HYPER(1); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_DB), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_DB), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); LogFlow(("TRPMGCHyper01: cs:eip=%04x:%08x uDr6=%RTreg\n", pRegFrame->cs.Sel, pRegFrame->eip, uDr6)); @@ -430,5 +430,5 @@ { LogFlow(("TRPMGCTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip)); - EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI), + EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); #if 0 /* Enable this iff you have a COM port and really want this debug info. */ @@ -458,5 +458,5 @@ { LogFlow(("TRPMGCHyperTrap02Handler: cs:eip=%04x:%08x\n", pRegFrame->cs.Sel, pRegFrame->eip)); - EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI), + EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NMI), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); #if 0 /* Enable this iff you have a COM port and really want this debug info. */ @@ -486,5 +486,5 @@ LogFlow(("TRPMGC03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(3); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_BP), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_BP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); PGMRZDynMapStartAutoSet(pVCpu); @@ -540,5 +540,5 @@ LogFlow(("TRPMGCHyper03: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK_HYPER(3); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_BP), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_BP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); @@ -573,5 +573,5 @@ LogFlow(("TRPMGC06: %04x:%08x EFL=%#x/%#x\n", pRegFrame->cs.Sel, pRegFrame->eip, pRegFrame->eflags.u32, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(6); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_UD), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_UD), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); PGMRZDynMapStartAutoSet(pVCpu); @@ -711,5 +711,5 @@ LogFlow(("TRPMGC07: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(7); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_NM), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NM), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); PGMRZDynMapStartAutoSet(pVCpu); @@ -739,5 +739,5 @@ LogFlow(("TRPMGC0b: %04x:%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(0xb); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_NP), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); PGMRZDynMapStartAutoSet(pVCpu); @@ -864,5 +864,5 @@ case OP_INT: { - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_INT)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INT)); Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8); Assert(!(PATMIsPatchGCAddr(pVM, PC))); @@ -897,5 +897,5 @@ case OP_HLT: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_HLT)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_HLT)); /* If it's in patch code, defer to ring-3. */ @@ -921,7 +921,7 @@ { if (uOpcode == OP_MOV_CR) - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX)); else - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX)); break; } @@ -941,32 +941,32 @@ { case OP_MOV_CR: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_CRX)); break; case OP_MOV_DR: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MOV_DRX)); break; case OP_INVLPG: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_INVLPG)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INVLPG)); break; case OP_LLDT: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_LLDT)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_LLDT)); break; case OP_STI: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_STI)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_STI)); break; case OP_RDPMC: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_RDPMC)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_RDPMC)); break; case OP_CLTS: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS)); break; case OP_WBINVD: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CLTS)); break; case OP_RDMSR: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)); break; case OP_WRMSR: - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE)); break; } @@ -1020,5 +1020,5 @@ case OP_INT: { - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_INT)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_INT)); Assert(pCpu->Param1.fUse & DISUSE_IMMEDIATE8); rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)pCpu->Param1.uValue, pCpu->cbInstr, TRPM_TRAP_NO_ERRORCODE, TRPM_SOFTWARE_INT, 0xd); @@ -1041,7 +1041,7 @@ case OP_SYSENTER: if (uOpcode == OP_SYSCALL) - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSCALL)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSCALL)); else - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSENTER)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_SYSENTER)); #ifdef PATM_EMULATE_SYSENTER rc = PATMSysCall(pVM, CPUMCTX_FROM_CORE(pRegFrame), pCpu); @@ -1187,5 +1187,5 @@ if (Cpu.pCurInstr->uOpcode == OP_RDTSC) { - EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_EM, EMEXITTYPE_RDTSC)); + EMHistoryUpdateFlagsAndType(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_RDTSC)); return trpmGCTrap0dHandlerRdTsc(pVM, pVCpu, pRegFrame); } @@ -1258,5 +1258,5 @@ LogFlow(("TRPMGC0d: %04x:%08x err=%x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(0xd); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_GP), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_GP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); @@ -1325,5 +1325,5 @@ LogFlow(("TRPMGC0e: %04x:%08x err=%x cr2=%08x EFL=%x\n", pRegFrame->cs.Sel, pRegFrame->eip, (uint32_t)pVCpu->trpm.s.uActiveErrorCode, (uint32_t)pVCpu->trpm.s.uActiveCR2, CPUMRawGetEFlags(pVCpu))); TRPM_ENTER_DBG_HOOK(0xe); - EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_PF), + EMRCHistoryAddExitCsEip(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_PF), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); @@ -1442,5 +1442,5 @@ DECLASM(int) TRPMGCHyperTrap0bHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame) { - EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_NP), + EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_NP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0bHandlers, g_aTrap0bHandlersEnd); @@ -1463,5 +1463,5 @@ DECLASM(int) TRPMGCHyperTrap0dHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame) { - EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_GP), + EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_GP), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd); @@ -1484,5 +1484,5 @@ DECLASM(int) TRPMGCHyperTrap0eHandler(PTRPMCPU pTrpmCpu, PCPUMCTXCORE pRegFrame) { - EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_XCPT, X86_XCPT_PF), + EMRCHistoryAddExitCsEip(TRPMCPU_2_VMCPU(pTrpmCpu), EMEXIT_MAKE_FT(EMEXIT_F_KIND_XCPT, X86_XCPT_PF), pRegFrame->cs.Sel, pRegFrame->eip, ASMReadTSC()); return trpmGCHyperGeneric(TRPMCPU_2_VM(pTrpmCpu), pRegFrame, g_aTrap0dHandlers, g_aTrap0dHandlersEnd);