Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 71835)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 71836)
@@ -1147,16 +1147,15 @@
  * Flushes the appropriate tagged-TLB entries.
  *
- * @param   pVCpu   The cross context virtual CPU structure.
- * @param   pCtx    Pointer to the guest-CPU or nested-guest-CPU context.
- * @param   pVmcb   Pointer to the VM control block.
- */
-static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   pCtx        Pointer to the guest-CPU or nested-guest-CPU context.
+ * @param   pVmcb       Pointer to the VM control block.
+ * @param   pHostCpu    Pointer to the HM host-CPU info.
+ */
+static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, PHMGLOBALCPUINFO pHostCpu)
 {
 #ifndef VBOX_WITH_NESTED_HWVIRT
     RT_NOREF(pCtx);
 #endif
-
-    PVM pVM               = pVCpu->CTX_SUFF(pVM);
-    PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
 
     /*
@@ -1171,7 +1170,7 @@
      */
     bool fNewAsid = false;
-    Assert(pCpu->idCpu != NIL_RTCPUID);
-    if (   pVCpu->hm.s.idLastCpu   != pCpu->idCpu
-        || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
+    Assert(pHostCpu->idCpu != NIL_RTCPUID);
+    if (   pVCpu->hm.s.idLastCpu   != pHostCpu->idCpu
+        || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
 #ifdef VBOX_WITH_NESTED_HWVIRT
         || CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
@@ -1200,15 +1199,12 @@
     if (pVM->hm.s.svm.fAlwaysFlushTLB)
     {
-        pCpu->uCurrentAsid               = 1;
+        pHostCpu->uCurrentAsid           = 1;
         pVCpu->hm.s.uCurrentAsid         = 1;
-        pVCpu->hm.s.cTlbFlushes          = pCpu->cTlbFlushes;
+        pVCpu->hm.s.cTlbFlushes          = pHostCpu->cTlbFlushes;
+        pVCpu->hm.s.idLastCpu            = pHostCpu->idCpu;
         pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
 
         /* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
         pVmcb->ctrl.u32VmcbCleanBits    &= ~HMSVM_VMCB_CLEAN_NP;
-
-        /* Keep track of last CPU ID even when flushing all the time. */
-        if (fNewAsid)
-            pVCpu->hm.s.idLastCpu = pCpu->idCpu;
     }
     else
@@ -1222,24 +1218,24 @@
             if (fNewAsid)
             {
-                ++pCpu->uCurrentAsid;
+                ++pHostCpu->uCurrentAsid;
 
                 bool fHitASIDLimit = false;
-                if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
+                if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
                 {
-                    pCpu->uCurrentAsid = 1;      /* Wraparound at 1; host uses 0 */
-                    pCpu->cTlbFlushes++;         /* All VCPUs that run on this host CPU must use a new ASID. */
+                    pHostCpu->uCurrentAsid = 1;      /* Wraparound at 1; host uses 0 */
+                    pHostCpu->cTlbFlushes++;         /* All VCPUs that run on this host CPU must use a new ASID. */
                     fHitASIDLimit      = true;
                 }
 
                 if (   fHitASIDLimit
-                    || pCpu->fFlushAsidBeforeUse)
+                    || pHostCpu->fFlushAsidBeforeUse)
                 {
                     pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
-                    pCpu->fFlushAsidBeforeUse = false;
+                    pHostCpu->fFlushAsidBeforeUse = false;
                 }
 
-                pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
-                pVCpu->hm.s.idLastCpu    = pCpu->idCpu;
-                pVCpu->hm.s.cTlbFlushes  = pCpu->cTlbFlushes;
+                pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
+                pVCpu->hm.s.idLastCpu    = pHostCpu->idCpu;
+                pVCpu->hm.s.cTlbFlushes  = pHostCpu->cTlbFlushes;
             }
             else
@@ -1262,12 +1258,12 @@
     }
 
-    AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
-              ("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
-    AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
-              ("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
-    AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
-              ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
+    AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
+              ("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
+    AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
+              ("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
+    AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
+              ("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
     AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
-              ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
+              ("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
 
 #ifdef VBOX_WITH_STATISTICS
@@ -4355,11 +4351,11 @@
     AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 
-    PHMGLOBALCPUINFO pHostCpu  = hmR0GetCurrentCpu();
-    RTCPUID const idCurrentCpu = pHostCpu->idCpu;
-    bool const    fMigratedCpu = idCurrentCpu != pVCpu->hm.s.idLastCpu;
+    PHMGLOBALCPUINFO pHostCpu      = hmR0GetCurrentCpu();
+    RTCPUID const idHostCpu        = pHostCpu->idCpu;
+    bool const    fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
 
     /* Setup TSC offsetting. */
     if (   pSvmTransient->fUpdateTscOffsetting
-        || fMigratedCpu)
+        || fMigratedHostCpu)
     {
         hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcbNstGst);
@@ -4368,5 +4364,5 @@
 
     /* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
-    if (fMigratedCpu)
+    if (fMigratedHostCpu)
         pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
 
@@ -4394,6 +4390,6 @@
     /* The TLB flushing would've already been setup by the nested-hypervisor. */
     ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);    /* Used for TLB flushing, set this across the world switch. */
-    hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
-    Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
+    hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst, pHostCpu);
+    Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
 
     STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
@@ -4481,8 +4477,11 @@
     AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
 
+    PHMGLOBALCPUINFO pHostCpu      = hmR0GetCurrentCpu();
+    RTCPUID const idHostCpu        = pHostCpu->idCpu;
+    bool const    fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
+
     /* Setup TSC offsetting. */
-    RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
     if (   pSvmTransient->fUpdateTscOffsetting
-        || idCurrentCpu != pVCpu->hm.s.idLastCpu)
+        || fMigratedHostCpu)
     {
         hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
@@ -4491,5 +4490,5 @@
 
     /* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
-    if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
+    if (fMigratedHostCpu)
         pVmcb->ctrl.u32VmcbCleanBits = 0;
 
@@ -4511,6 +4510,6 @@
     /* Flush the appropriate tagged-TLB entries. */
     ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);    /* Used for TLB flushing, set this across the world switch. */
-    hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
-    Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
+    hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb, pHostCpu);
+    Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
 
     STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);