Index: /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 71767)
+++ /trunk/src/VBox/Devices/Bus/DevPciIch9.cpp	(revision 71768)
@@ -791,9 +791,9 @@
     int rc;
 
-    rc = MsiInit(pPciDev, pMsiReg);
+    rc = MsiR3Init(pPciDev, pMsiReg);
     if (RT_FAILURE(rc))
         return rc;
 
-    rc = MsixInit(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
+    rc = MsixR3Init(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp), pPciDev, pMsiReg);
     if (RT_FAILURE(rc))
         return rc;
@@ -2544,12 +2544,12 @@
         if (   pciDevIsMsiCapable(pPciDev)
             && uAddress - (uint32_t)pPciDev->Int.s.u8MsiCapOffset < (uint32_t)pPciDev->Int.s.u8MsiCapSize)
-            MsiPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
-                              pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
-                              pPciDev, uAddress, u32Value, cb);
+            MsiR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
+                                pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
+                                pPciDev, uAddress, u32Value, cb);
         else if (   pciDevIsMsixCapable(pPciDev)
                  && uAddress - (uint32_t)pPciDev->Int.s.u8MsixCapOffset < (uint32_t)pPciDev->Int.s.u8MsixCapSize)
-            MsixPciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
-                               pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
-                               pPciDev, uAddress, u32Value, cb);
+            MsixR3PciConfigWrite(pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pDevIns),
+                                 pPciDev->Int.s.CTX_SUFF(pBus)->CTX_SUFF(pPciHlp),
+                                 pPciDev, uAddress, u32Value, cb);
         else
         {
Index: /trunk/src/VBox/Devices/Bus/MsiCommon.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/MsiCommon.cpp	(revision 71767)
+++ /trunk/src/VBox/Devices/Bus/MsiCommon.cpp	(revision 71768)
@@ -17,4 +17,5 @@
  * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
  */
+
 #define LOG_GROUP LOG_GROUP_DEV_PCI
 #define PDMPCIDEV_INCLUDE_PRIVATE  /* Hack to get pdmpcidevint.h included at the right point. */
@@ -27,11 +28,11 @@
 #include "PciInline.h"
 
+
 DECLINLINE(uint16_t) msiGetMessageControl(PPDMPCIDEV pDev)
 {
     uint32_t idxMessageControl = pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL;
 #ifdef IN_RING3
-    if (pciDevIsPassthrough(pDev)) {
+    if (pciDevIsPassthrough(pDev))
         return pDev->Int.s.pfnConfigRead(pDev->Int.s.CTX_SUFF(pDevIns), pDev, idxMessageControl, 2);
-    }
 #endif
     return PCIDevGetWord(pDev, idxMessageControl);
@@ -46,5 +47,5 @@
  * up to date, which is a wrong assumption for the "emulate passthrough" case
  * where only the callbacks give the correct data. */
-DECLINLINE(uint32_t*) msiGetMaskBits(PPDMPCIDEV pDev)
+DECLINLINE(uint32_t *) msiGetMaskBits(PPDMPCIDEV pDev)
 {
     uint8_t iOff = msiIs64Bit(pDev) ? VBOX_MSI_CAP_MASK_BITS_64 : VBOX_MSI_CAP_MASK_BITS_32;
@@ -87,8 +88,5 @@
         return RT_MAKE_U64(lo, hi);
     }
-    else
-    {
-        return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
-    }
+    return PCIDevGetDWord(pDev, pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_ADDRESS_32);
 }
 
@@ -109,25 +107,21 @@
 #ifdef IN_RING3
 
-DECLINLINE(bool) msiBitJustCleared(uint32_t uOldValue,
-                                   uint32_t uNewValue,
-                                   uint32_t uMask)
-{
-    return (!!(uOldValue & uMask) && !(uNewValue & uMask));
-}
-
-DECLINLINE(bool) msiBitJustSet(uint32_t uOldValue,
-                               uint32_t uNewValue,
-                               uint32_t uMask)
-{
-    return (!(uOldValue & uMask) && !!(uNewValue & uMask));
-}
-
-void     MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev,
-                           uint32_t u32Address, uint32_t val, unsigned len)
+DECLINLINE(bool) msiR3BitJustCleared(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
+{
+    return !!(uOldValue & uMask) && !(uNewValue & uMask);
+}
+
+DECLINLINE(bool) msiR3BitJustSet(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
+{
+    return !(uOldValue & uMask) && !!(uNewValue & uMask);
+}
+
+void MsiR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev,
+                         uint32_t u32Address, uint32_t val, unsigned len)
 {
     int32_t iOff = u32Address - pDev->Int.s.u8MsiCapOffset;
     Assert(iOff >= 0 && (pciDevIsMsiCapable(pDev) && iOff < pDev->Int.s.u8MsiCapSize));
 
-    Log2(("MsiPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
+    Log2(("MsiR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
 
     uint32_t uAddr = u32Address;
@@ -181,5 +175,5 @@
                             uint32_t uVector = maskUpdated*8 + iBitNum;
 
-                            if (msiBitJustCleared(pDev->abConfig[uAddr], u8Val, iBit))
+                            if (msiR3BitJustCleared(pDev->abConfig[uAddr], u8Val, iBit))
                             {
                                 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated));
@@ -193,5 +187,5 @@
                                 }
                             }
-                            if (msiBitJustSet(pDev->abConfig[uAddr], u8Val, iBit))
+                            if (msiR3BitJustSet(pDev->abConfig[uAddr], u8Val, iBit))
                             {
                                 Log(("msi: mask vector: %d\n", uVector));
@@ -208,5 +202,5 @@
 }
 
-int MsiInit(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
+int MsiR3Init(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
 {
     if (pMsiReg->cMsiVectors == 0)
@@ -272,5 +266,5 @@
 
 
-bool     MsiIsEnabled(PPDMPCIDEV pDev)
+bool MsiIsEnabled(PPDMPCIDEV pDev)
 {
     return pciDevIsMsiCapable(pDev) && msiIsEnabled(pDev);
@@ -326,2 +320,3 @@
     pPciHlp->pfnIoApicSendMsi(pDevIns, GCAddr, u32Value, uTagSrc);
 }
+
Index: /trunk/src/VBox/Devices/Bus/MsiCommon.h
===================================================================
--- /trunk/src/VBox/Devices/Bus/MsiCommon.h	(revision 71767)
+++ /trunk/src/VBox/Devices/Bus/MsiCommon.h	(revision 71768)
@@ -3,4 +3,5 @@
  * Header for MSI/MSI-X support routines.
  */
+
 /*
  * Copyright (C) 2010-2017 Oracle Corporation
@@ -30,5 +31,5 @@
 #ifdef IN_RING3
 /* Init MSI support in the device. */
-int      MsiInit(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg);
+int      MsiR3Init(PPDMPCIDEV pDev, PPDMMSIREG pMsiReg);
 #endif
 
@@ -41,10 +42,10 @@
 #ifdef IN_RING3
 /* PCI config space accessors for MSI registers */
-void     MsiPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len);
+void     MsiR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len);
 #endif
 
 #ifdef IN_RING3
 /* Init MSI-X support in the device. */
-int      MsixInit(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg);
+int      MsixR3Init(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg);
 #endif
 
@@ -57,4 +58,4 @@
 #ifdef IN_RING3
 /* PCI config space accessors for MSI-X */
-void     MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len);
+void     MsixR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len);
 #endif
Index: /trunk/src/VBox/Devices/Bus/MsixCommon.cpp
===================================================================
--- /trunk/src/VBox/Devices/Bus/MsixCommon.cpp	(revision 71767)
+++ /trunk/src/VBox/Devices/Bus/MsixCommon.cpp	(revision 71768)
@@ -15,4 +15,6 @@
  * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
  */
+
+
 #define LOG_GROUP LOG_GROUP_DEV_PCI
 #define PDMPCIDEV_INCLUDE_PRIVATE  /* Hack to get pdmpcidevint.h included at the right point. */
@@ -28,5 +30,4 @@
 #include "PciInline.h"
 
-#pragma pack(1)
 typedef struct
 {
@@ -37,5 +38,5 @@
 } MsixTableRecord;
 AssertCompileSize(MsixTableRecord, VBOX_MSIX_ENTRY_SIZE);
-#pragma pack()
+
 
 /** @todo use accessors so that raw PCI devices work correctly with MSI-X. */
@@ -114,5 +115,5 @@
 #ifdef IN_RING3
 
-PDMBOTHCBDECL(int) msixMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
+PDMBOTHCBDECL(int) msixR3MMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
     LogFlowFunc(("\n"));
@@ -130,9 +131,9 @@
                     VINF_IOM_MMIO_UNUSED_FF);
 
-    *(uint32_t*)pv = *(uint32_t*)msixGetPageOffset(pPciDev, off);
+    *(uint32_t *)pv = *(uint32_t *)msixGetPageOffset(pPciDev, off);
     return VINF_SUCCESS;
 }
 
-PDMBOTHCBDECL(int) msixMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
+PDMBOTHCBDECL(int) msixR3MMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
 {
     LogFlowFunc(("\n"));
@@ -149,5 +150,5 @@
                     VINF_IOM_MMIO_UNUSED_FF);
 
-    *(uint32_t*)msixGetPageOffset(pPciDev, off) = *(uint32_t*)pv;
+    *(uint32_t *)msixGetPageOffset(pPciDev, off) = *(uint32_t *)pv;
 
     msixCheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
@@ -158,6 +159,6 @@
  * @callback_method_impl{FNPCIIOREGIONMAP}
  */
-static DECLCALLBACK(int) msixMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
-                                 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
+static DECLCALLBACK(int) msixR3Map(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
+                                   RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
 {
     Assert(enmType == PCI_ADDRESS_SPACE_MEM);
@@ -166,5 +167,5 @@
     int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, pPciDev,
                                    IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
-                                   msixMMIOWrite, msixMMIORead, "MSI-X tables");
+                                   msixR3MMIOWrite, msixR3MMIORead, "MSI-X tables");
 
     if (RT_FAILURE(rc))
@@ -174,8 +175,8 @@
 }
 
-int MsixInit(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
+int MsixR3Init(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
 {
     if (pMsiReg->cMsixVectors == 0)
-         return VINF_SUCCESS;
+        return VINF_SUCCESS;
 
      /* We cannot init MSI-X on raw devices yet. */
@@ -205,5 +206,5 @@
     if (!pciDevIsPassthrough(pDev))
     {
-        rc = PDMDevHlpPCIIORegionRegister(pDev->Int.s.CTX_SUFF(pDevIns), iBar, cbMsixRegion, PCI_ADDRESS_SPACE_MEM, msixMap);
+        rc = PDMDevHlpPCIIORegionRegister(pDev->Int.s.CTX_SUFF(pDevIns), iBar, cbMsixRegion, PCI_ADDRESS_SPACE_MEM, msixR3Map);
         if (RT_FAILURE (rc))
             return rc;
@@ -244,5 +245,5 @@
 #endif
 
-bool     MsixIsEnabled(PPDMPCIDEV pDev)
+bool MsixIsEnabled(PPDMPCIDEV pDev)
 {
     return pciDevIsMsixCapable(pDev) && msixIsEnabled(pDev);
@@ -292,10 +293,10 @@
 
 
-void MsixPciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len)
+void MsixR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len)
 {
     int32_t iOff = u32Address - pDev->Int.s.u8MsixCapOffset;
     Assert(iOff >= 0 && (pciDevIsMsixCapable(pDev) && iOff < pDev->Int.s.u8MsixCapSize));
 
-    Log2(("MsixPciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
+    Log2(("MsixR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
 
     uint32_t uAddr = u32Address;